4263f791f6
Fix part select of width-1 vector
...
Signals of width 1 are declared in VHDL as std_logic, as this
is the usual way to represent them. Unfortunately, we cannot
distinguish between
reg [0:0] a;
and
reg a;
This patch avoids trying to slice a std_logic so a[0] is equivalent to a.
2008-11-26 13:14:27 -08:00
fd4018cb33
Fix IVL_LPM_MUX where inputs are different signedness to outputs
2008-10-05 17:08:19 +01:00
b40de5ccb0
Implement IVL_LPM_CMP_NE(E)
...
Looks like I forgot this one
2008-10-05 17:04:19 +01:00
ff766899b0
Add IVL_LPM_CMP_GT
2008-09-02 19:07:38 +01:00
122890fef4
Make sure LPM expression is cast to the output type
...
This fixes some signed/unsigned bugs identified by the signedX tests.
2008-09-02 19:02:54 +01:00
7865264de0
Implement IVL_LPM_REPEAT
2008-08-18 15:34:58 +01:00
e4d0a92d7c
Division and modulus operators
2008-08-07 14:18:26 +01:00
8d7b03576c
Correctly implement unary XNOR
...
Forgot to negate the output.
2008-08-05 10:38:43 +01:00
0e2628a3fb
Minimal implementation of IVL_LPM_MUX
...
This handles the (common) case of the select being only
1 bit wide. Implemented as a concurrent assignment with
a `when' clause.
2008-08-03 12:46:50 +01:00
45dfa28dba
Remember signal pin a nexus was attached to
...
Also modify nexus_to_var_ref to set the correct array
offset when the signal is an array (the offset comes
from the pin).
2008-08-03 11:41:26 +01:00
09f3eb4a36
Don't bother calling reduction function if argument is std_logic
2008-08-01 16:27:55 +01:00
d94dac28a8
Remove redundant lpm_output
2008-07-29 13:08:13 +01:00
b9cecbef64
Make sure LPM comparison result is std_logic not Boolean
2008-07-27 19:05:49 +01:00
3ca85491ee
Unary AND and XOR
2008-07-20 16:41:57 +01:00
77508b9afa
Reduction OR operator
2008-07-20 15:10:00 +01:00
df4a380e42
Fix implementation of IVL_LPM_UFUNC
...
Function name was not correct.
2008-07-18 14:31:12 +01:00
8b6b111541
Add IVL_LPM_CMP_EQ
2008-07-18 11:58:26 +01:00
fd8f01e317
Add IVL_LPM_CMP_GE
2008-07-18 11:56:00 +01:00
7677b59650
Make sure offset of IVL_LPM_ARRAY is integer
2008-07-17 16:41:34 +01:00
f62a00bedb
Fix LPM binop with different signedness
...
Need to explicitly cast between signed/unsigned to
make sure both arguments have the same type or the
VHDL won't compile.
2008-07-16 16:20:08 +01:00
646a6056a2
Add IVL_LPM_CMP_EEQ support
2008-07-16 12:50:55 +01:00
45e289d32d
Implement IVL_LPM_SHIFTL/R
2008-07-15 18:01:37 +01:00
b8e758edf0
Refactor LPM code
2008-07-15 14:09:24 +01:00
e331e4831b
Fix nexus_to_expr where nexus has IVL_LPM_SELECT_PV
2008-07-14 11:53:38 +01:00
bd5cc96956
Correct vector sizes for bit select
2008-07-08 00:20:31 +01:00
a0dbb1aa5d
Fix more bugs in part selects
2008-07-07 21:45:27 +01:00
860a74ddd8
Allow LPMs in port maps
2008-07-07 20:41:29 +01:00
2bb645e0bc
Refactor LPM code to allow lpm->expr function
2008-07-07 19:46:18 +01:00
47db80315c
Add sign extension LPM
2008-07-07 19:27:52 +01:00
6b73cc39a5
Add Active_High support func and fix LPM part select
2008-07-07 16:17:54 +01:00
89cdbf63be
Reduction LPM types
2008-07-07 15:45:20 +01:00
bdf5ee7ab7
Concat LPM
2008-07-07 14:48:57 +01:00
4fac825457
Add PV part select type
2008-07-03 14:45:54 +01:00
edfae1abfb
PV LPM part select type
2008-07-01 11:02:49 +01:00
e08e29c8b4
Add UFUNC LPM type
2008-06-30 16:35:29 +01:00
b82ca28190
Add XOR logic type and fix part select
2008-06-30 16:18:55 +01:00
081f397460
Implement LPM part select
2008-06-27 14:58:03 +01:00
63b1887ff2
Refactor code to use the new vhdl_scope class
2008-06-24 18:52:25 +01:00
8d0afa632d
Subtraction and multiplication LPM devices
2008-06-16 19:49:24 +01:00
561953e494
Minial LPM to support continuous assignments
2008-06-16 19:41:01 +01:00
Nick Gasson