cb73accd84
Spelling fixes
2015-08-17 11:34:58 -07:00
775904ab0f
vhdlpp: ExpName::elaborate_rval accepts enum values.
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Fix for br986.
2015-08-09 18:48:59 +02:00
0ae3414ec5
vhdlpp: ExpUnary::elaborate_expr() elaborates its operand as well.
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Fix for br985.
2015-08-09 18:48:15 +02:00
5858e1bbac
vhdlpp: ExpName::probe_type() checks Subprogram parameters.
2015-06-24 23:53:33 +02:00
d39f692cfd
vhdlpp: Refactored the way of handling standard types.
2015-06-24 23:53:32 +02:00
b3c1fa3e85
vhdlpp: Elaborate prefix & indices for ExpName.
2015-06-24 23:53:32 +02:00
169228ad0f
vhdlpp: Refactored the way of handling standard VHDL library functions.
2015-06-24 23:53:31 +02:00
47c5ce0ab6
vhdlpp: Subprogram split to SubprogramHeader and SubprogramBody.
2015-06-24 23:53:31 +02:00
5a0d967682
vhdlpp: More renaming in ExpConditional.
2015-06-24 23:53:31 +02:00
49efe6573c
vhdlpp: Minor ExpConditional refactoring.
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Merged cond_ and true_clause_ to else_clause_ list to make
code more generic.
2015-06-24 23:53:31 +02:00
ea12c0fe23
vhdlp: Renamed ExpConditional::else_t to ExpConditional::option_t.
2015-06-24 23:53:31 +02:00
d6ff1946f9
vhdlpp: Support for time expressions.
2015-06-08 18:42:52 +02:00
7aab315ce5
vhdlpp: Allow assigning values to inout ports.
2015-05-20 17:30:07 +02:00
7db01d8ded
vhdlpp: ScopeBase::is_enum_name() returns VTypeEnum* instead of bool.
2015-05-07 16:28:30 +02:00
4304fd503e
vhdlpp: and_reduce() and or_reduce() functions.
2015-05-06 10:03:02 +02:00
ab9a8ccbf3
vhdlpp: Added fit_type() & probe_type() for ExpFunc.
2015-03-27 18:57:40 +01:00
e6525ec35f
vhdlpp: Added a constructor for VTypeArray that takes integers as ranges.
2015-03-27 18:57:40 +01:00
3b14797075
vhdlpp: Prefix probe for VTypeArray.
2015-03-27 14:53:43 +01:00
807ad8002d
vhdlpp: Check generics when searching through constants.
2015-03-06 20:39:10 +01:00
1852c5ab9d
Revert "vhdlpp: Support for accessing words in constant arrays."
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This reverts commit 9ca754b6db
2015-03-06 17:32:25 +01:00
9ca754b6db
vhdlpp: Support for accessing words in constant arrays.
2015-02-19 17:07:41 +01:00
e569e07d4e
vhdlpp: Type 'NATURAL' is translated to 'int unsigned'.
2015-02-19 17:07:41 +01:00
763c6fe3c9
vhdlpp: Support for shift operators (SRL, SRR, SRA, SLA).
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To be done: ROR & ROL.
2015-02-17 10:15:57 +01:00
12b4914b63
vhdlpp: ExpName resolves enum values.
2015-02-17 10:15:57 +01:00
19ff6a434b
vhdlpp: Alternative way of dealing with unbounded vectors in fuctions (instances).
2015-02-05 12:00:25 +01:00
1a367c84b6
vhdlpp: Subprograms can have instances that take a different set of parameter types.
2015-02-05 11:25:03 +01:00
60077f4f06
vhdlpp: ExpBitstring elaborate_expr().
2015-02-05 11:25:03 +01:00
25c3798248
vhdlpp: Elaborate and emit functions work with ScopeBase instead of Architecture.
2015-02-04 16:57:43 +01:00
9ba7694484
vhdlpp: Minor assert.
2015-02-04 16:57:43 +01:00
962330f20a
vhdlpp: Functions support unbounded vectors as return type and parameters.
2015-02-04 16:57:43 +01:00
95faed8e9d
vhdlpp: Added basic support for concatenated expressions.
2014-10-15 10:51:21 +02:00
76aab15798
vhdlpp: Minor code cleaning.
2014-10-15 10:51:21 +02:00
1333bc54a2
vhdlpp: Support for 'left & 'right attributes.
2014-10-08 10:05:04 +02:00
fde6525acb
vhdlpp: Libraries are searched for subprograms during the ExpFunc elaboration.
2014-10-01 14:56:32 +02:00
194a950f8d
vhdlpp: Elaboration of ExpFunc parameters fallbacks to the types given in the Subprogram header.
2014-09-30 15:59:46 +02:00
f5dd2ac87e
vhdlpp: Aggregate expressions for records can be specified in any order.
2014-09-17 16:32:56 +02:00
54696e0127
vhdlpp: Elaboration & emit support for aggregate initializer expressions in records.
2014-09-17 11:24:16 +02:00
69b145e216
Minor cleaning for valgrind output.
2014-08-06 15:01:28 +02:00
5ed60a151f
Added support for real type in vhdlpp.
2014-08-06 15:00:35 +02:00
21b24c7725
Fix more compile warnings and a minor bug
2013-07-11 19:10:25 -07:00
8487cb5616
Do a better job of figuring the vtype of an expression.
2013-06-12 14:21:36 -07:00
d630e4dfe9
Elaborate VHDL entity port types/expressions.
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We need to elaborate expressions so that function calls in
expressions (i.e. ranges) get bound to their proper scope.
This binding is in turn used to emit package scopes. This
is particularly interesting for ports of entities.
2013-06-12 14:21:35 -07:00
11682fc7eb
Harmless cleanup of comments / initialization warnings.
2013-04-18 18:18:40 -07:00
c14134aa2e
Handle genvar variables in expressions.
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In generate for blocks, there is a genvar that can be used in
expressions within the generate block. Generate this genvar in
the generated output, matched to the generate scope.
2012-09-07 15:14:48 -07:00
85e000ed0c
Handle prefix expressions that include array index expressions.
2012-09-03 16:00:10 -07:00
f5aafc32f9
updated FSF-address
2012-08-29 10:12:10 -07:00
369a0b9eca
VHDL named types work in more places.
2012-05-22 17:31:27 -07:00
63b7fe059d
Reword concat to handle aggregate arguments.
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When concatenation expressions have aggregate arguments, we need to
get the type of the result down to the aggregate expressions so that
it can know how to interpret the elements.
2012-05-22 17:31:26 -07:00
71d2401221
Handle VHDL records.
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Elaborate records and emit them as packed SV records. Also handle
record members so handle name prefixes.
While we are at it, handle some cases of array aggregate expressions.
2012-05-22 17:31:26 -07:00
ae06863db1
Elaborate prefix names which may be structure variables.
2012-05-22 17:31:26 -07:00
Larry Doolittle
Maciej Suminski
Cary R
Stephen Williams
Arun Persaud