Nick Gasson
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aa91186119
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Add AST elements for unary/binary expressions to model logic gates
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2008-06-09 14:39:58 +01:00 |
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Nick Gasson
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d08f5af9c6
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Add concurrent assignments
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2008-06-09 14:21:55 +01:00 |
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Nick Gasson
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b96e471fa2
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Stub code for handling logic gates
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2008-06-09 14:08:27 +01:00 |
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Nick Gasson
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110a1b2ac7
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Replace type classes with enumeration
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2008-06-08 12:48:56 +01:00 |
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Nick Gasson
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fbf85398da
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Support converting bit strings to std_logic
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2008-06-07 16:19:10 +01:00 |
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Nick Gasson
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8c3461f0ff
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Generate sensitivity lists properly and add signal declarations
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2008-06-07 11:48:38 +01:00 |
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Nick Gasson
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c3ac1aac8c
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Remove debugging messages from output
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2008-06-04 21:07:50 +01:00 |
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Nick Gasson
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7bd1565cfb
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$display now (mostly) working
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2008-06-04 20:42:44 +01:00 |
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Nick Gasson
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ab6ae621cb
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Remove useless comments in output
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2008-06-02 20:24:25 +01:00 |
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Nick Gasson
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17ae0a6a09
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Fix a bug where the same instantiation appeared multiple times
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2008-06-02 18:05:39 +01:00 |
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Nick Gasson
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041925c123
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Component instantiation to replicate Verilog hierarchy
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2008-06-02 17:45:58 +01:00 |
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Nick Gasson
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9292a087e8
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Generate VHDL processes from Verilog processes
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2008-06-02 16:17:01 +01:00 |
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Nick Gasson
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7c9d154461
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Forgot source files for entity generation
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2008-05-31 15:31:48 +01:00 |