In synthesis we transform registers into wires, but if there is bad
Verilog code where the register is written from non-synthesized code
then we can't do this! This patch adds a check in the code generator
for this and prints a error message instead of generating a .resolv
to combine the two, which is certainly not correct.
This patch reworks the NetLatch class to better match the NetFF class
(e.g. it adds a place for the async controls and value, adds a dump
routine, etc.) and moves it into the normal netlist.{h,cc} files. It
removes the unused Aload and Sload routines, etc. from the NetFF class.
It switches the latch to use the existing ff object to pass information
to the target and uses the existing FF routines as applicable.
ivl_lpm_async_clr()
ivl_lpm_async_set()
ivl_lpm_aset_value()
ivl_lpm_clk() for the gate
ivl_lpm_data()
ivl_lpm_q()
It adds support for generating a latch UDP just like is done for the
D flip-flop in the tgt-vvp code generator and fixes a bug in the
generation of the clear signal when both the Aclr and Aset signals
clear the register.
If both the async. clr and set pins clear a flip-flop then we need to
create an OR gate to combine the two signals to connect to the single
DFF clr pin. This patch fixes the tgt-vvp code generator to implement
this functionality.
This patch removes #ident since it is deprecated in recent gcc
versions. It also removes all the CVS comments and fixes a few
other compilation warnings. There are still a few compilation
warnings, but this takes care of most of them. Fixing the rest
will require a bit more thought.
scaled to the local units. Change the internal
implementation of vpiSystemTime the $time functions
to properly account for this. Also add $simtime
to get the simulation time.
Larry Doolittle
Cary R
steve