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V0.8: Fix dffsynth code generation bug. 

If both the async. clr and set pins clear a flip-flop then we need to
create an OR gate to combine the two signals to connect to the single
DFF clr pin. This patch fixes the tgt-vvp code generator to implement
this functionality.
This commit is contained in:
Cary R 2010-12-20 14:34:27 -08:00 committed by Stephen Williams
parent 5f3e5f6b35
commit 3a162ea69f
1 changed files with 23 additions and 5 deletions
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28
tgt-vvp/vvp_scope.c
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@ -1466,7 +1466,7 @@ static void draw_lpm_ff(ivl_lpm_t net)
draw_input_from_net(ivl_lpm_enable(net));
fprintf(vvp_out, ", ");
draw_input_from_net(ivl_lpm_sync_clr(net));
fprintf(vvp_out, ";\n");
fprintf(vvp_out, ", C<0>, C<0>;\n");
}
if (ivl_lpm_enable(net) && ivl_lpm_sync_set(net)) {
@ -1476,7 +1476,21 @@ static void draw_lpm_ff(ivl_lpm_t net)
draw_input_from_net(ivl_lpm_enable(net));
fprintf(vvp_out, ", ");
draw_input_from_net(ivl_lpm_sync_set(net));
fprintf(vvp_out, ";\n");
fprintf(vvp_out, ", C<0>, C<0>;\n");
}
for (idx = 0 ; idx < width ; idx += 1) {
if (ivl_lpm_async_clr(net) &&
aset_bits && (aset_bits[idx] == '0')) {
fprintf(vvp_out, "L_%s.%s/clr_or .functor OR, ",
vvp_mangle_id(ivl_scope_name(ivl_lpm_scope(net))),
vvp_mangle_id(ivl_lpm_basename(net)));
draw_input_from_net(ivl_lpm_async_clr(net));
fprintf(vvp_out, ", ");
draw_input_from_net(ivl_lpm_async_set(net));
fprintf(vvp_out, ", C<0>, C<0>;\n");
break;
}
}
for (idx = 0 ; idx < width ; idx += 1) {
@ -1590,11 +1604,15 @@ static void draw_lpm_ff(ivl_lpm_t net)
fprintf(vvp_out, ", ");
tmp = ivl_lpm_async_clr(net);
if (tmp) {
draw_input_from_net(tmp);
} else {
tmp = ivl_lpm_async_set(net);
if (aset_bits && (aset_bits[idx] == '0'))
fprintf(vvp_out, "L_%s.%s/clr_or",
vvp_mangle_id(ivl_scope_name(ivl_lpm_scope(net))),
vvp_mangle_id(ivl_lpm_basename(net)));
else
draw_input_from_net(tmp);
} else {
if (aset_bits && (aset_bits[idx] == '0'))
draw_input_from_net(ivl_lpm_async_set(net));
else
fprintf(vvp_out, "C<0>");
}