Nick Gasson
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1d3ac6bc1f
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Generate VHDL array type declarations of Verilog arrays
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2008-07-17 13:08:55 +01:00 |
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Nick Gasson
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553f3d77a9
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Code for VHDL array type
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2008-07-17 11:43:59 +01:00 |
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Nick Gasson
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bd5cc96956
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Correct vector sizes for bit select
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2008-07-08 00:20:31 +01:00 |
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Nick Gasson
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a0dbb1aa5d
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Fix more bugs in part selects
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2008-07-07 21:45:27 +01:00 |
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Nick Gasson
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050aa277ae
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Make vhdl_element::emit a little more generic
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2008-07-01 10:37:22 +01:00 |
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Nick Gasson
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d7bb5658f2
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Translate IVL_ST_DELAYX statements
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2008-06-19 12:16:19 +01:00 |
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Nick Gasson
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2fb57805ea
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Use signed rather than std_logic_vector
Arithmetic operators now working correctly
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2008-06-14 18:03:25 +01:00 |
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Nick Gasson
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919c1d695c
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Adding binary +
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2008-06-14 17:09:31 +01:00 |
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Nick Gasson
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0df3eabe26
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Convert `if (foo) ..' to `if foo = '1' then ..'
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2008-06-12 11:36:21 +01:00 |
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Nick Gasson
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7eb41304e6
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Generate rising/falling edge detectors
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2008-06-12 10:36:38 +01:00 |
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Nick Gasson
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120b5dc80e
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Add constant integers
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2008-06-09 12:46:55 +01:00 |
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Nick Gasson
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1d28b935e8
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Split vhdl_element.cc into multiple files
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2008-06-08 13:27:48 +01:00 |