Cary R
|
fbe42f13e2
|
Update tgt- directories with cppcheck suggested fixes
|
2021-01-02 13:31:26 -08:00 |
Stephen Williams
|
ec49f10e2d
|
Revert bad merge from vhdl branch
|
2010-10-02 11:02:27 -07:00 |
Nick Gasson
|
43f904f793
|
Add uwire support to VHDL backend
Implemented as std_ulogic which behaves almost identically.
|
2010-09-30 12:22:39 +01:00 |
|
Cary R
|
c0a592bec2
|
Don't place a trailing ',' after the last enum item.
The SunPro compiler does not like having a ',' after the last
enum item.
|
2010-05-13 18:56:44 -07:00 |
|
Nick Gasson
|
1d3ac6bc1f
|
Generate VHDL array type declarations of Verilog arrays
|
2008-07-17 13:08:55 +01:00 |
|
Nick Gasson
|
553f3d77a9
|
Code for VHDL array type
|
2008-07-17 11:43:59 +01:00 |
|
Nick Gasson
|
bd5cc96956
|
Correct vector sizes for bit select
|
2008-07-08 00:20:31 +01:00 |
|
Nick Gasson
|
a0dbb1aa5d
|
Fix more bugs in part selects
|
2008-07-07 21:45:27 +01:00 |
|
Nick Gasson
|
050aa277ae
|
Make vhdl_element::emit a little more generic
|
2008-07-01 10:37:22 +01:00 |
|
Nick Gasson
|
d7bb5658f2
|
Translate IVL_ST_DELAYX statements
|
2008-06-19 12:16:19 +01:00 |
|
Nick Gasson
|
2fb57805ea
|
Use signed rather than std_logic_vector
Arithmetic operators now working correctly
|
2008-06-14 18:03:25 +01:00 |
|
Nick Gasson
|
919c1d695c
|
Adding binary +
|
2008-06-14 17:09:31 +01:00 |
|
Nick Gasson
|
7eb41304e6
|
Generate rising/falling edge detectors
|
2008-06-12 10:36:38 +01:00 |
|
Nick Gasson
|
120b5dc80e
|
Add constant integers
|
2008-06-09 12:46:55 +01:00 |
|
Nick Gasson
|
1d28b935e8
|
Split vhdl_element.cc into multiple files
|
2008-06-08 13:27:48 +01:00 |