Commit Graph

15 Commits

Author SHA1 Message Date
Cary R 26c01e7f0a Use preincrement instead of post in for loop incr 2025-06-20 12:48:01 -07:00
Stephen Williams 03f912dc55 Clean up warnings
Clean up warnings that show up on newer compilers. Many of these warnings
are related to obsolete c library features or language features. This does
not clear up warnings in code generated by bison or flex.
2022-12-18 10:18:10 -05:00
Lars-Peter Clausen 5ef847ea87 Support type parameters
SystemVerilog supports type parameters. These are similar to value
parameters, but they allow to pass a type to a module or similar when
instantiating it.

E.g.

```
module A #(parameter type T = int);
endmodule

module B;
  A #(.T(real)) i_a;
endmodule
```

Add support for handling type parameters.

For the vlog95 and vhdl backends type parameters, similar to typedefs, get
replaced with their actual value. For modules with non-local type
parameters for each module instance a unique module or architecture is
generated with the actual type.

Querying type parameters through VPI is not yet supported.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2022-12-11 13:50:14 -08:00
Christian Taedcke 6d5aabd4f0 Make a few constructors explicit.
This removes cppcheck warnings.
2015-10-22 12:33:33 +02:00
Cary R 2a0d33608f Fix spacing problems.
This patch fixes spacing problems in the source code, space/tab at
the end of line and space before tab.
2011-03-03 11:21:31 -08:00
Nick Gasson 0144b5a2bb Basic parameter support in VHDL target
This is a fix for pr2555831. A separate entity/architecture pair is
generated for each module that is instantiated with a unique
parameter combination.
2010-10-05 20:03:08 +01:00
Stephen Williams ec49f10e2d Revert bad merge from vhdl branch 2010-10-02 11:02:27 -07:00
Nick Gasson d9bf96d8fa Basic parameter support in VHDL target
This is a fix for pr2555831. A separate entity/architecture pair is
generated for each module that is instantiated with a unique
parameter combination.
2010-09-11 12:17:06 +01:00
Cary R 3f12a401eb Add some casts in tgt-vhdl to remove warnings.
The Cygwin compiler is a bit picky. This patch adds some casts
to remove compilation warnings. In the past I have had warnings
off because of problems with the STL, but we may as well get
rid of the warnings we can. It also does not recognize that an
assert(0) or assert(false) ends a routine so it complains about
no return at end of function or variables not being defined.
2009-12-11 21:46:49 -08:00
Nick Gasson 388c9c6747 Handle generate scopes with signals in VHDL target
This uniques the name of each copy of a signal and adds
it to the containing VHDL entity.
2009-09-03 17:13:33 -07:00
Nick Gasson 2115e87f78 Fix VHDL naming collisions with modules
This fixes a bug where the renaming rules for modules
would generate entity names that collided with already
existing module names.
2009-02-05 14:40:47 -08:00
Nick Gasson f89f3dcbaf More VHDL naming fixes
This handles the cases where:
    * Instance names contain leading/trailing underscores
    * Instance names contain consecutive underscores
    * Module names contain consecutive underscores
    * Module names contain leading/trailing underscores
	* Ports may be inconsistently renamed
2009-02-02 19:41:50 -08:00
Nick Gasson babc9c1352 Various signal naming fixes for VHDL target
This avoids generating invalid VHDL signal names in the
following cases:
	- The name begins or ends with an underscore
	- The name contains two consecutive underscores
	- The name is the same as a component declaration
	- The name differs from another only in case
2009-01-28 17:44:14 -08:00
Nick Gasson e6846ea3a7 Improve memory management in VHDL target
Previously the VHDL code generator managed memory for
the AST objects by requiring that each AST element be
responsible for deleting its children. The disadvantages
of this are that it's quite easy to accidentally leak
memory by forgetting to delete a child, and no AST pointers
may be shared by multiple parents (or we'd end up with
double-deletes) -- this results in unnecessary copies of
objects being made.

There's no real need for fine-grained memory management of
AST objects since once they're allocated they tend to
persist until the code generator is about to terminate, when
they should all be freed.

This patch provides a custom new/delete operator for
vhdl_element which logs the vhdl_element objects allocated
in a std::vector (after calling the default operator new).
Once the code generator is finished a single free_all_objects
call deletes all the AST objects in one go. The custom delete
operator is required so that we can still explicitly deallocate
vhdl_element objects before the code generator completes.

There are also some allocation statistics printed at the end
when -pdebug=1 is specified.
2009-01-18 16:42:10 -08:00
Nick Gasson f1f9274bb9 Move VHDL global state management to a single file
The new state.cc/hh file now manages all the global
state that we maintain while generating VHDL. This
should make the code a bit tidier.
2009-01-17 09:19:58 -08:00