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Merge pull request #644 from larsclausen/port-range-mismatch-recover 

Recover from port and signal vector range mismatch
This commit is contained in:
Stephen Williams 2022-03-13 14:36:31 -07:00 committed by GitHub
parent 5bc1c08c67 a9c0469b2b
commit 15e1a7a3f2
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GPG Key ID: 4AEE18F83AFDEB23
4 changed files with 36 additions and 3 deletions
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3
elab_sig.cc
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@ -1100,7 +1100,6 @@ NetNet* PWire::elaborate_sig(Design*des, NetScope*scope) const
<< "'' has a vectored net declaration " << "'' has a vectored net declaration "
<< nlist << "." << endl; << nlist << "." << endl;
des->errors += 1; des->errors += 1;
return 0;
} }
} }
@ -1112,7 +1111,6 @@ NetNet* PWire::elaborate_sig(Design*des, NetScope*scope) const
<< " has a scalar net declaration at " << " has a scalar net declaration at "
<< get_fileline() << "." << endl; << get_fileline() << "." << endl;
des->errors += 1; des->errors += 1;
return 0;
} }
/* Both vectored, but they have different ranges. */ /* Both vectored, but they have different ranges. */
@ -1124,7 +1122,6 @@ NetNet* PWire::elaborate_sig(Design*des, NetScope*scope) const
<< " at " << net_.front().first->get_fileline() << " at " << net_.front().first->get_fileline()
<< " that does not match." << endl; << " that does not match." << endl;
des->errors += 1; des->errors += 1;
return 0;
} }
} }

16
ivtest/ivltests/module_port_range_mismatch.v Normal file
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@ -0,0 +1,16 @@
// Check that range mismatches between port direction and data type are detected
// for module ports. An error should be reported and no crash should occur.
module test;
input [1:0] x;
wire [3:0] x;
wire [3:0] y;
assign y = x;
initial begin
$display("FAILED");
end
endmodule

18
ivtest/ivltests/task_port_range_mismatch.v Normal file
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@ -0,0 +1,18 @@
// Check that range mismatches between port direction and data type are detected
// for task ports. An error should be reported and no crash should occur.
module test;
task t;
input [1:0] x;
reg [3:0] x;
reg [3:0] y;
y = x;
$display("FAILED");
endtask
initial begin
t(4'b1001);
end
endmodule

2
ivtest/regress-vlg.list
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@ -648,6 +648,7 @@ module_inout_port_type CE ivltests
module_input_port_type CE ivltests module_input_port_type CE ivltests
module_output_port_var1 normal ivltests module_output_port_var1 normal ivltests
module_output_port_var2 normal ivltests module_output_port_var2 normal ivltests
module_port_range_mismatch CE ivltests
modulus normal ivltests # wire % and reg % operators modulus normal ivltests # wire % and reg % operators
modulus2 normal ivltests # reg % operators modulus2 normal ivltests # reg % operators
monitor normal ivltests gold=monitor.gold monitor normal ivltests gold=monitor.gold
@ -1609,6 +1610,7 @@ task_noop normal ivltests # Task with no contents.
task_noop2 CO ivltests # Task *really* with no contents. task_noop2 CO ivltests # Task *really* with no contents.
task_omemw2 normal ivltests task_omemw2 normal ivltests
task_omemw3 CO ivltests # Pass bit selected from vector to task task_omemw3 CO ivltests # Pass bit selected from vector to task
task_port_range_mismatch CE ivltests
task_port_size normal ivltests # truncate task port connections task_port_size normal ivltests # truncate task port connections
task_scope normal ivltests task_scope normal ivltests
tern1 normal ivltests # Finds problems with ?: using different sizes tern1 normal ivltests # Finds problems with ?: using different sizes