19 lines
328 B
Verilog
19 lines
328 B
Verilog
// Check that range mismatches between port direction and data type are detected
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// for task ports. An error should be reported and no crash should occur.
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module test;
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task t;
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input [1:0] x;
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reg [3:0] x;
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reg [3:0] y;
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y = x;
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$display("FAILED");
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endtask
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initial begin
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t(4'b1001);
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end
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endmodule
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