diff --git a/elab_sig.cc b/elab_sig.cc
index 66275b46b..f472c7595 100644
--- a/elab_sig.cc
+++ b/elab_sig.cc
@@ -1100,7 +1100,6 @@ NetNet* PWire::elaborate_sig(Design*des, NetScope*scope) const
 			           << "'' has a vectored net declaration "
 				   << nlist << "." << endl;
 			      des->errors += 1;
-			      return 0;
 			}
 		  }
 
@@ -1112,7 +1111,6 @@ NetNet* PWire::elaborate_sig(Design*des, NetScope*scope) const
 			     << " has a scalar net declaration at "
 			     << get_fileline() << "." << endl;
 			des->errors += 1;
-			return 0;
 		  }
 
 		  /* Both vectored, but they have different ranges. */
@@ -1124,7 +1122,6 @@ NetNet* PWire::elaborate_sig(Design*des, NetScope*scope) const
 			     << " at " << net_.front().first->get_fileline()
 			     << " that does not match." << endl;
 			des->errors += 1;
-			return 0;
 		  }
             }
 
diff --git a/ivtest/ivltests/module_port_range_mismatch.v b/ivtest/ivltests/module_port_range_mismatch.v
new file mode 100644
index 000000000..07cd1082d
--- /dev/null
+++ b/ivtest/ivltests/module_port_range_mismatch.v
@@ -0,0 +1,16 @@
+// Check that range mismatches between port direction and data type are detected
+// for module ports. An error should be reported and no crash should occur.
+
+module test;
+  input [1:0] x;
+  wire [3:0] x;
+
+  wire [3:0] y;
+
+  assign y = x;
+
+  initial begin
+    $display("FAILED");
+  end
+
+endmodule
diff --git a/ivtest/ivltests/task_port_range_mismatch.v b/ivtest/ivltests/task_port_range_mismatch.v
new file mode 100644
index 000000000..6ba4abc25
--- /dev/null
+++ b/ivtest/ivltests/task_port_range_mismatch.v
@@ -0,0 +1,18 @@
+// Check that range mismatches between port direction and data type are detected
+// for task ports. An error should be reported and no crash should occur.
+
+module test;
+
+  task t;
+    input [1:0] x;
+    reg [3:0] x;
+    reg [3:0] y;
+    y = x;
+    $display("FAILED");
+  endtask
+
+  initial begin
+    t(4'b1001);
+  end
+
+endmodule
diff --git a/ivtest/regress-vlg.list b/ivtest/regress-vlg.list
index 09d213229..de57a69b8 100644
--- a/ivtest/regress-vlg.list
+++ b/ivtest/regress-vlg.list
@@ -648,6 +648,7 @@ module_inout_port_type	CE			ivltests
 module_input_port_type	CE			ivltests
 module_output_port_var1	normal			ivltests
 module_output_port_var2	normal			ivltests
+module_port_range_mismatch CE			ivltests
 modulus			normal			ivltests # wire % and reg % operators
 modulus2		normal			ivltests # reg % operators
 monitor			normal			ivltests gold=monitor.gold
@@ -1609,6 +1610,7 @@ task_noop		normal			ivltests # Task with no contents.
 task_noop2		CO			ivltests # Task *really* with no contents.
 task_omemw2		normal			ivltests
 task_omemw3		CO			ivltests # Pass bit selected from vector to task
+task_port_range_mismatch CE			ivltests
 task_port_size		normal			ivltests # truncate task port connections
 task_scope		normal			ivltests
 tern1			normal			ivltests # Finds problems with ?: using different sizes