From 0328fc5a6f451e8ec607e86e0c2467921d6c1043 Mon Sep 17 00:00:00 2001 From: Lars-Peter Clausen Date: Sat, 12 Mar 2022 11:11:43 +0100 Subject: [PATCH 1/3] Recover from port and signal vector range mismatch When using non-ANSI style port declarations it is possible to have both a port and net or variable declaration for the same signal. In this case the range specification for the two declarations have to match. In the current implementation if the range specifications do not match an error is reported and no signal is created. This generates follow up errors about the signal not being declared when it is used. In some cases it even causes the application to crash. E.g. the task elaboration expects the port signal to exist. If it does not it will crash. To avoid this still create the signal, even when an error is detected. Use the range specification of the net or variable in this case. Overall elaboration will still fail due to the error, but the application will not crash. Signed-off-by: Lars-Peter Clausen --- elab_sig.cc | 3 --- 1 file changed, 3 deletions(-) diff --git a/elab_sig.cc b/elab_sig.cc index 47edb73d8..8115e4abb 100644 --- a/elab_sig.cc +++ b/elab_sig.cc @@ -1042,7 +1042,6 @@ NetNet* PWire::elaborate_sig(Design*des, NetScope*scope) const << "'' has a vectored net declaration " << nlist << "." << endl; des->errors += 1; - return 0; } } @@ -1054,7 +1053,6 @@ NetNet* PWire::elaborate_sig(Design*des, NetScope*scope) const << " has a scalar net declaration at " << get_fileline() << "." << endl; des->errors += 1; - return 0; } /* Both vectored, but they have different ranges. */ @@ -1066,7 +1064,6 @@ NetNet* PWire::elaborate_sig(Design*des, NetScope*scope) const << " at " << net_.front().first->get_fileline() << " that does not match." << endl; des->errors += 1; - return 0; } } From 026d552be143d583540b33b35ad991c12a299b84 Mon Sep 17 00:00:00 2001 From: Lars-Peter Clausen Date: Sun, 13 Mar 2022 11:01:09 +0100 Subject: [PATCH 2/3] Add regression test for module port range mismatch Check that a range mismatch is detected for non-ANSI module ports when port direction and data type are declared separately. An error should be reported and no crash should occur. Signed-off-by: Lars-Peter Clausen --- ivtest/ivltests/module_port_range_mismatch.v | 16 ++++++++++++++++ ivtest/regress-vlg.list | 1 + 2 files changed, 17 insertions(+) create mode 100644 ivtest/ivltests/module_port_range_mismatch.v diff --git a/ivtest/ivltests/module_port_range_mismatch.v b/ivtest/ivltests/module_port_range_mismatch.v new file mode 100644 index 000000000..07cd1082d --- /dev/null +++ b/ivtest/ivltests/module_port_range_mismatch.v @@ -0,0 +1,16 @@ +// Check that range mismatches between port direction and data type are detected +// for module ports. An error should be reported and no crash should occur. + +module test; + input [1:0] x; + wire [3:0] x; + + wire [3:0] y; + + assign y = x; + + initial begin + $display("FAILED"); + end + +endmodule diff --git a/ivtest/regress-vlg.list b/ivtest/regress-vlg.list index 09d213229..5306833bc 100644 --- a/ivtest/regress-vlg.list +++ b/ivtest/regress-vlg.list @@ -648,6 +648,7 @@ module_inout_port_type CE ivltests module_input_port_type CE ivltests module_output_port_var1 normal ivltests module_output_port_var2 normal ivltests +module_port_range_mismatch CE ivltests modulus normal ivltests # wire % and reg % operators modulus2 normal ivltests # reg % operators monitor normal ivltests gold=monitor.gold From a9c0469b2b7a14d057cab399556dd519e2d03970 Mon Sep 17 00:00:00 2001 From: Lars-Peter Clausen Date: Sun, 13 Mar 2022 10:37:26 +0100 Subject: [PATCH 3/3] Add regression test for task port range mismatch Check that a range mismatch is detected for non-ANSI task ports when port direction and data type are declared separately. An error should be reported and no crash should occur. Signed-off-by: Lars-Peter Clausen --- ivtest/ivltests/task_port_range_mismatch.v | 18 ++++++++++++++++++ ivtest/regress-vlg.list | 1 + 2 files changed, 19 insertions(+) create mode 100644 ivtest/ivltests/task_port_range_mismatch.v diff --git a/ivtest/ivltests/task_port_range_mismatch.v b/ivtest/ivltests/task_port_range_mismatch.v new file mode 100644 index 000000000..6ba4abc25 --- /dev/null +++ b/ivtest/ivltests/task_port_range_mismatch.v @@ -0,0 +1,18 @@ +// Check that range mismatches between port direction and data type are detected +// for task ports. An error should be reported and no crash should occur. + +module test; + + task t; + input [1:0] x; + reg [3:0] x; + reg [3:0] y; + y = x; + $display("FAILED"); + endtask + + initial begin + t(4'b1001); + end + +endmodule diff --git a/ivtest/regress-vlg.list b/ivtest/regress-vlg.list index 5306833bc..de57a69b8 100644 --- a/ivtest/regress-vlg.list +++ b/ivtest/regress-vlg.list @@ -1610,6 +1610,7 @@ task_noop normal ivltests # Task with no contents. task_noop2 CO ivltests # Task *really* with no contents. task_omemw2 normal ivltests task_omemw3 CO ivltests # Pass bit selected from vector to task +task_port_range_mismatch CE ivltests task_port_size normal ivltests # truncate task port connections task_scope normal ivltests tern1 normal ivltests # Finds problems with ?: using different sizes