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Update header files to use a more standard name to prevent rereading This is from github report #16. There are likely a few more issues that need to be addressed though this takes care of the major ones.
2014-07-23 22:39:29 +02:00
#ifndef IVL_pform_H
#define IVL_pform_H
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/*
Add initial parsing for let construct
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* Copyright (c) 1998-2021 Stephen Williams (steve@icarus.com)
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*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
updated FSF-address
2012-08-29 03:41:23 +02:00
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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*/
# include "netlist.h"
Parser and pform use hierarchical names as hname_t objects instead of encoded strings.
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# include "HName.h"
Support named parameter override lists.
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# include "named.h"
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# include "Module.h"
# include "Statement.h"
Infrastructure for parsing analog process statements. Organize the parsing infrastructure for parsing analog processes, including holding them in scopes, and collecting analog statements.
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# include "AStatement.h"
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# include "PGate.h"
# include "PExpr.h"
Elaborate user defined tasks.
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# include "PTask.h"
Parse UDP primitives all the way to pform.
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# include "PUdp.h"
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# include "PWire.h"
Handle delayed signals in timing checks as assignments
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# include "PTimingCheck.h"
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# include "verinum.h"
Attach natures to disciplines Pform parse enough of the natures that they can be mapped and the disciplines can bind to them. Since Verilog-AMS expects natures to be declared before use, we can do the binding early.
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# include "discipline.h"
Use standard name for iostream.
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# include <iostream>
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# include <string>
# include <list>
Finish up parser code for enum types This gets the parser syntax actions done, up to the pform code. It is ready for generating pform structures.
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# include <memory>
Remove malloc.h support and for C++ files use <c...> include files. The functions (malloc, free, etc.) that used to be provided in malloc.h are now provided in cstdlib for C++ files and stdlib.h for C files. Since we require a C99 compliant compiler it makes sense that malloc.h is no longer needed. This patch also modifies all the C++ files to use the <c...> version of the standard C header files (e.g. <cstdlib> vs <stdlib.h>). Some of the files used the C++ version and others did not. There are still a few other header changes that could be done, but this takes care of much of it.
2010-05-31 22:12:06 +02:00
# include <cstdio>
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/*
* These classes implement the parsed form (P-form for short) of the
Spelling fixes only comments and documentation some punctuation and capitalization for good measure Changelogs are purposefully untouched
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* original Verilog source. the parser generates the pform for the
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* convenience of later processing steps.
*/
/*
* Wire objects represent the named wires (of various flavor) declared
* in the source.
*
* Gate objects are the functional modules that are connected together
* by wires.
*
* Wires and gates, connected by joints, represent a netlist. The
* netlist is therefore a representation of the desired circuit.
*/
class PGate;
class PExpr;
Parse more package items Rework lexical support for PACKAGE_IDENTIFIER so that the lexor can help with package scoped identifiers. Pform package types and package functions up to elaboration.
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class PPackage;
Basic support for specify timing.
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class PSpecPath;
Get the scope of class methods right Class methods belong in a class scope, not the containing module. So create a lexical scope that carries tasks and functions and create a PClass to represent classes.
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class PClass;
Parse (with sorry message) package declarations.
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class PPackage;
Line information with nets.
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struct vlltype;
lgate: Inherit from LineInfo The lgate struct has its own fields for tracking file and line number, while everything else that has this information attached inherits from the LineInfo class. Make lgate also inherit from LineInfo for consistency. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
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struct lgate;
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Introduce min:typ:max support.
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/*
* The min:typ:max expression s selected at parse time using the
Spelling fixes.
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* enumeration. When the compiler makes a choice, it also prints a
Introduce min:typ:max support.
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* warning if min_typ_max_warn > 0.
*/
extern enum MIN_TYP_MAX { MIN, TYP, MAX } min_typ_max_flag;
extern unsigned min_typ_max_warn;
PExpr* pform_select_mtm_expr(PExpr*min, PExpr*typ, PExpr*max);
Add support for -v flag in command file.
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/*
* This flag is true if the lexor thinks we are in a library source
* file.
*/
extern bool pform_library_flag;
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/*
* These type are lexical types -- that is, types that are used as
* lexical values to decorate the parse tree during parsing. They are
* not in any way preserved once parsing is done.
*/
module parameter bind by name.
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/* This is information about port name information for named port
connections. */
Support named parameter override lists.
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struct parmvalue_t {
Remove "using namespace std" from compiler header files and fix the fallout.
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std::list<PExpr*>*by_order;
std::list<named_pexpr_t>*by_name;
module parameter bind by name.
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};
Remove Link::strength_t and PGate::strength_t types. These types are useless repetition of the ivl_drive_t type. This is also another chapter in the series to push ivl_target generation further upstream.
2010-03-16 23:16:53 +01:00
struct str_pair_t { ivl_drive_t str0, str1; };
Carry assignment strength to pform.
2000-05-06 17:41:56 +02:00
Parse attributes on statements within event statements. Statements can have attributes attached to them. Handle a few cases in the parser where attributes may be attached to statements, and get them as far as the pform.
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/* Use this function to transform the parted form of the attribute
list to the attribute map that is used later. */
Remove "using namespace std" from compiler header files and fix the fallout.
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extern void pform_bind_attributes(std::map<perm_string,PExpr*>&attributes,
std::list<named_pexpr_t>*attr,
Enumeration element values can be expressions Allow more complex enumeration expressions, which means putting off the evaluation of the expression values until elaboration.
2010-11-13 03:47:06 +01:00
bool keep_attr =false);
Parse disciplines and contribution statements Parse discipline declarations, net discipline declarations, and analog contribution statements. Don't yet do anything useful with these, just give a sorry message where they are encountered.
2008-05-11 21:00:11 +02:00
Add support for the default_nettype directive.
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/* The lexor calls this function to change the default nettype. */
extern void pform_set_default_nettype(NetNet::Type net,
const char*file,
unsigned lineno);
Prevent non-blocking assignment in program blocks.
2012-05-06 19:21:51 +02:00
/* Return true if currently processing a program block. This can be
used to reject statements that cannot exist in program blocks. */
extern bool pform_in_program_block(void);
Added support for interface declaration and instantiation. modport and extern tf declarations are not yet supported.
2014-12-20 00:10:14 +01:00
/* Return true if currently processing an interface. This can be
used to reject statements that cannot exist in interfaces. */
extern bool pform_in_interface(void);
Attach disciplines to wires Allow discipline declaration of nets that attaches the discipline to a new wire or a wire that is already declared.
2008-05-12 02:30:33 +02:00
/*
* Look for the given wire in the current lexical scope. If the wire
* (including variables of any type) cannot be found in the current
* scope, then return 0.
*/
extern PWire* pform_get_wire_in_scope(perm_string name);
Output an error message when a SV variable declaration reuses a name. Assertion failures are not the right way to handle user code errors.
2018-02-18 18:51:56 +01:00
extern PWire* pform_get_make_wire_in_scope(const struct vlltype&li,
perm_string name,
NetNet::Type net_type,
ivl_variable_type_t vt_type);
Parse support for struct variables.
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Introduce verilog to CVS.
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/*
* The parser uses startmodule and endmodule together to build up a
* module as it parses it. The startmodule tells the pform code that a
* module has been noticed in the source file and the following events
* are to apply to the scope of that module. The endmodule causes the
* pform to close up and finish the named module.
Basic support for program blocks.
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*
Added support for interface declaration and instantiation. modport and extern tf declarations are not yet supported.
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* The program_block flag indicates that the module is actually a program
* block. The is_interface flag indicates that the module is actually
* an interface. These flags have implications during parse and during
Basic support for program blocks.
2012-05-01 06:12:59 +02:00
* elaboration/code generation.
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*/
Basic support for program blocks.
2012-05-01 06:12:59 +02:00
extern void pform_startmodule(const struct vlltype&loc, const char*name,
Added support for interface declaration and instantiation. modport and extern tf declarations are not yet supported.
2014-12-20 00:10:14 +01:00
bool program_block, bool is_interface,
Added support for default subroutine lifetimes (SystemVerilog).
2016-03-19 18:27:27 +01:00
LexicalScope::lifetime_t lifetime,
Remove "using namespace std" from compiler header files and fix the fallout.
2021-11-04 17:12:04 +01:00
std::list<named_pexpr_t>*attr);
extern void pform_module_set_ports(std::vector<Module::port_t*>*);
Rework handling of timescales in parser. This implements and enforces the full set of rules for determining timescales in SystemVerilog. The previous relaxation of the rules that allowed timescales to be redefined within the compilation unit scope has been removed. Time unit and precision redeclarations are now recognised after a nested module declaration.
2017-11-05 18:50:05 +01:00
extern void pform_set_scope_timescale(const struct vlltype&loc);
Add ranges and signed to port list declarations.
2002-05-20 04:06:01 +02:00
Fix for br974 - support SV types in non-ansi port declarations.
2016-04-04 21:40:30 +02:00
/* These functions are used when we have a complete port definition, either
in an ansi style or non-ansi style declaration. In this case, we have
everything needed to define the port, all in one place. */
Add ranges and signed to port list declarations.
2002-05-20 04:06:01 +02:00
extern void pform_module_define_port(const struct vlltype&li,
Rework handling of lexical scope Move the storage of wires (signals) out of the Module class into the PScope base class, and instead of putting the PWires all into the Module object, distribute them into the various lexical scopes (derived from PScope) so that the wire names do not need to carry scope information. This required some rewiring of elaboration of signals, and rewriting of lexical scope handling.
2008-02-25 04:40:54 +01:00
perm_string name,
Add ranges and signed to port list declarations.
2002-05-20 04:06:01 +02:00
NetNet::PortType,
NetNet::Type type,
Rework port input and inout to use data_type_or_implicit rule for types.
2012-04-13 05:20:37 +02:00
data_type_t*vtype,
Correctly handle unpacked array typedefs for ports If the type of a port is an array type it currently always gets evaluated in the scope where the port is declared. But if the type is a typedef it might be declared in a different scope and must be evaluated in that scope. E.g. the following will declare an array port with 10 entries and an element type of a 5 bit vector, while it should declare one with 4 entries and an element type of a 2 bit vector. ``` localparam A = 2; localparam B = 4; typedef [A-1:0] T[B]; module test ( T x ); localparam A = 5; localparam B = 10; endmodule ``` This is in part due to array types being given special handling. This was necessary before because each base type required slightly different handling and so the base type had to be extracted from the array type. This has now been consolidated and all data types are treated the same. The only exception is the vector type which still needs special handling to support separate definition of port direction and type. As a result it is possible to remove the special handling of the array type. This solves the problem of evaluating the type in the wrong scope. Some special handling needs to be retained though to be able to differentiate between array dimensions that are part of a type and array dimensions that are part of port declaration. This is again necessary to correctly support separate definition of port direction and type. E.g. in the example below port `x` and `y` get treated slightly differently, even though the resulting signals will be identical. ``` typedef logic [7:0] T[1:0]; ... input T x; input [7:0] y[1:0]; ``` Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2022-04-11 09:48:29 +02:00
std::list<pform_range_t>*urange,
Remove "using namespace std" from compiler header files and fix the fallout.
2021-11-04 17:12:04 +01:00
std::list<named_pexpr_t>*attr,
Fix for br974 - support SV types in non-ansi port declarations.
2016-04-04 21:40:30 +02:00
bool keep_attr =false);
extern void pform_module_define_port(const struct vlltype&li,
Remove "using namespace std" from compiler header files and fix the fallout.
2021-11-04 17:12:04 +01:00
std::list<pform_port_t>*ports,
Fix for br974 - support SV types in non-ansi port declarations.
2016-04-04 21:40:30 +02:00
NetNet::PortType,
NetNet::Type type,
data_type_t*vtype,
Remove "using namespace std" from compiler header files and fix the fallout.
2021-11-04 17:12:04 +01:00
std::list<named_pexpr_t>*attr);
Add ranges and signed to port list declarations.
2002-05-20 04:06:01 +02:00
parser: Consistently pass line information as `vlltype` Currently there is a mix of passing line information either as `struct vlltype` or as a separate `const char *file` and `unsigned lineno`. For consistency always use the struct vlltype variant. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2022-01-10 11:21:14 +01:00
extern Module::port_t* pform_module_port_reference(const struct vlltype&loc,
perm_string name);
Fix some definition/implementation name differences. Update some of the definition argument names to match the recent implementation name changes
2010-06-02 04:24:09 +02:00
extern void pform_endmodule(const char*, bool inside_celldefine,
Module::UCDriveType uc_drive_def);
Introduce verilog to CVS.
1998-11-04 00:28:49 +01:00
Get the scope of class methods right Class methods belong in a class scope, not the containing module. So create a lexical scope that carries tasks and functions and create a PClass to represent classes.
2012-03-11 21:18:24 +01:00
extern void pform_start_class_declaration(const struct vlltype&loc,
Parse/elaborate class derivation This gets us down to working classes, but does not yet implement calls to the parent constructor, implicitly or explicitly.
2013-10-31 02:35:00 +01:00
class_type_t*type,
Implement class extends arguments. This implements constructor arguments right after the base class name in the class extends syntax.
2013-11-10 17:21:22 +01:00
data_type_t*base_type,
Added support for default subroutine lifetimes (SystemVerilog).
2016-03-19 18:27:27 +01:00
std::list<PExpr*>*base_exprs,
Do not allow to create objects of virtual classes It is not allowed to create objects of virtual classes. Currently the virtual keyword is accepted by the parser, but otherwise ignored. Keep track of whether a class is virtual and generate an error when the class new operator is used for a virtual type. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2022-09-19 20:23:02 +02:00
bool virtual_class);
Stub to pform class properties and null expressions.
2012-11-04 01:41:11 +01:00
extern void pform_class_property(const struct vlltype&loc,
property_qualifier_t pq,
data_type_t*data_type,
std::list<decl_assignment_t*>*decls);
Elaborate class task and function methods. The parse of class methods already works, this patch forms the methods into their own scopes, and elaborates those scopes. The "this"
2013-03-15 04:08:32 +01:00
extern void pform_set_this_class(const struct vlltype&loc, PTaskFunc*net);
Generalize user defined function return type handling. I'm gonna need functions to return class objects, so generalize the output types of user defined functions.
2013-04-15 03:03:21 +02:00
extern void pform_set_constructor_return(PFunction*net);
Handle this as special identifier strings. / Organize pform class member binding
2013-03-02 23:51:44 +01:00
Elaborate implicit initializers Remaining pform fixup of property initializers, and elaboration and code generation for implicit constructor.
2013-06-17 00:14:50 +02:00
extern void pform_end_class_declaration(const struct vlltype&loc);
Support non-overridable parameters in classes SystemVerilog allows `parameter` and `localparam` to declare constants within a class scope. E.g. ```SystemVerilog class C; localparam A = 10; endclass ``` In this context both declare a local parameter that can not be overwritten. Supporting this can be achieved for the most part by adding a parser sub-rule in class declaration rule. In addition some extra support code is needed to mark the parameter as non-overridable. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2022-02-05 11:29:27 +01:00
extern bool pform_in_class();
Get the scope of class methods right Class methods belong in a class scope, not the containing module. So create a lexical scope that carries tasks and functions and create a PClass to represent classes.
2012-03-11 21:18:24 +01:00
parser: Consistently pass line information as `vlltype` Currently there is a mix of passing line information either as `struct vlltype` or as a separate `const char *file` and `unsigned lineno`. For consistency always use the struct vlltype variant. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2022-01-10 11:21:14 +01:00
extern void pform_make_udp(const struct vlltype&loc, perm_string name,
std::list<perm_string>*parms,
Remove "using namespace std" from compiler header files and fix the fallout.
2021-11-04 17:12:04 +01:00
std::vector<PWire*>*decl, std::list<std::string>*table,
parser: Consistently pass line information as `vlltype` Currently there is a mix of passing line information either as `struct vlltype` or as a separate `const char *file` and `unsigned lineno`. For consistency always use the struct vlltype variant. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2022-01-10 11:21:14 +01:00
Statement*init);
Parse UDP primitives all the way to pform.
1998-11-25 03:35:53 +01:00
parser: Consistently pass line information as `vlltype` Currently there is a mix of passing line information either as `struct vlltype` or as a separate `const char *file` and `unsigned lineno`. For consistency always use the struct vlltype variant. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2022-01-10 11:21:14 +01:00
extern void pform_make_udp(const struct vlltype&loc, perm_string name,
Verilog2001 new style port declartions for primitives.
2004-03-08 01:10:29 +01:00
bool sync_flag, perm_string out_name,
PExpr*sync_init,
Remove "using namespace std" from compiler header files and fix the fallout.
2021-11-04 17:12:04 +01:00
std::list<perm_string>*parms,
parser: Consistently pass line information as `vlltype` Currently there is a mix of passing line information either as `struct vlltype` or as a separate `const char *file` and `unsigned lineno`. For consistency always use the struct vlltype variant. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2022-01-10 11:21:14 +01:00
std::list<std::string>*table);
Import parameters from packages.
2013-02-15 02:53:47 +01:00
/*
* Package related functions.
*/
extern void pform_start_package_declaration(const struct vlltype&loc,
Added support for default subroutine lifetimes (SystemVerilog).
2016-03-19 18:27:27 +01:00
const char*type,
LexicalScope::lifetime_t lifetime);
Import parameters from packages.
2013-02-15 02:53:47 +01:00
extern void pform_end_package_declaration(const struct vlltype&loc);
extern void pform_package_import(const struct vlltype&loc,
Parse more package items Rework lexical support for PACKAGE_IDENTIFIER so that the lexor can help with package scoped identifiers. Pform package types and package functions up to elaboration.
2013-04-01 00:46:36 +02:00
PPackage*pkg, const char*ident);
Add support for package export By default an identifier that has been imported into a package is not available for imports by other packages. Only imports that have been exported can be imported again. E.g. ``` package P1; int x; endpackage package P2; import P1::x; export P1::x; endpackage module test; import P2::x; // This will only work if x has been exported. endmodule ``` Exports follow the same syntax as imports and allow both export of specific identifiers or wildcard export. Export supports the special `*::*` target, which will export all imported items. Add support for handling package exports. There is one special cases that needs to be considered. Usually when using wildcard imports from multiple packages it is an error if there multiple import candidates for an identifier. With exports it is possible that there are multiple candidates through different packets, but they all refer to the same identifier. In this case it does not create a conflict. E.g. ``` package P1; int x; endpackage package P2; import P1::x; export P1::x; endpackage package P3; import P1::*; import P2::*; int y = x; // No import conflict endpackage ``` Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2022-10-03 19:05:55 +02:00
extern void pform_package_export(const struct vlltype &loc, PPackage *pkg,
const char *ident);
PPackage *pform_package_importable(PPackage *pkg, perm_string name);
PPackage *pform_find_potential_import(const struct vlltype&loc, LexicalScope*scope,
perm_string name, bool tf_call, bool make_explicit);
Verilog2001 new style port declartions for primitives.
2004-03-08 01:10:29 +01:00
Add packages and their own scope. This makes <pkg>::<name> work properly, and also makes the package descriptions available through VPI.
2013-02-17 23:42:07 +01:00
extern PExpr* pform_package_ident(const struct vlltype&loc,
packages can contain variables.
2013-04-08 01:38:48 +02:00
PPackage*pkg, pform_name_t*ident);
Add packages and their own scope. This makes <pkg>::<name> work properly, and also makes the package descriptions available through VPI.
2013-02-17 23:42:07 +01:00
Added parser support for SV modport declarations.
2015-01-10 12:09:42 +01:00
/*
* Interface related functions.
*/
extern void pform_start_modport_item(const struct vlltype&loc, const char*name);
extern void pform_end_modport_item(const struct vlltype&loc);
extern void pform_add_modport_port(const struct vlltype&loc,
NetNet::PortType port_type,
Fix space issues in the code.
2015-01-16 02:46:54 +01:00
perm_string name, PExpr*expr);
Added parser support for SV modport declarations.
2015-01-10 12:09:42 +01:00
Properly implement import <pkg>::<name> This was temporarily implemented to just copy definitions to the local scope, but the better method is to create a PEIdent that has the package attached to it.
2013-02-18 01:22:24 +01:00
/*
* This creates an identifier aware of names that may have been
* imported from other packages.
*/
Correctly handle explicit and wildcard package imports. Explicit imports should always conflict with local declarations using the same name. Wildcard imports only conflict if they are referenced before a local declaration with the same name. This also unifies the detection of identifier conflicts.
2019-09-27 00:35:57 +02:00
extern PEIdent* pform_new_ident(const struct vlltype&loc, const pform_name_t&name);
Properly implement import <pkg>::<name> This was temporarily implemented to just copy definitions to the local scope, but the better method is to create a PEIdent that has the package attached to it.
2013-02-18 01:22:24 +01:00
Add support for package scope resolution for named events.
2019-09-29 22:11:01 +02:00
extern PTrigger* pform_new_trigger(const struct vlltype&loc, PPackage*pkg,
const pform_name_t&name);
Add compiler and the start of vvp support for ->>
2021-02-20 08:21:12 +01:00
extern PNBTrigger* pform_new_nb_trigger(const struct vlltype&loc,
Remove "using namespace std" from compiler header files and fix the fallout.
2021-11-04 17:12:04 +01:00
const std::list<PExpr*>*dly,
Add compiler and the start of vvp support for ->>
2021-02-20 08:21:12 +01:00
const pform_name_t&name);
Add support for named events in packages.
2019-09-28 22:00:17 +02:00
Handle expression widths for EEE and NEE operators, add named blocks and scope handling, add registers declared in named blocks.
1999-06-24 06:24:18 +02:00
/*
Parser and pform use hierarchical names as hname_t objects instead of encoded strings.
2001-12-03 05:47:14 +01:00
* Enter/exit name scopes. The push_scope function pushes the scope
* name string onto the scope hierarchy. The pop pulls it off and
* deletes it. Thus, the string pushed must be allocated.
Handle expression widths for EEE and NEE operators, add named blocks and scope handling, add registers declared in named blocks.
1999-06-24 06:24:18 +02:00
*/
extern void pform_pop_scope();
Import parameters from packages.
2013-02-15 02:53:47 +01:00
/*
* Peek at the current (most recently active) scope.
*/
extern LexicalScope* pform_peek_scope();
Fix variable initialization in class methods Up to 1800-2017 the grammar in the LRM allowed an optional lifetime qualifier for class declarations. Icarus supports this and uses this as the default lifetime for methods of the class. But the LRM never specified what this qualifier should do actually actually. Starting with 1800-2023 the qualifier will be removed from the grammar[1]. Furthermore the LRM states that methods of a class are supposed to have automatic storage and static storage is forbidden. This currently works in Icarus for the most part since the liftime attached to class methods is ignored during elaboration in most places. Where it does not work is for variable initializers where it results in broken code being generated and vvp crashes at runtime. E.g. ``` class C; task t; int x = 10; endtask endclass ``` Keep the optional lifetime qualifier for classes in the grammar for now, to ensure backwards compatibility in case somebody is actually using it. But ignore it and print a warning if it is specified. In addition set the default lifetime for all classes to automatic. This makes sure that variable initialization in classes works as expected. [1] https://accellera.mantishub.io/view.php?id=3561 Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2022-12-19 00:55:09 +01:00
extern PClass* pform_push_class_scope(const struct vlltype&loc, perm_string name);
Added support for default subroutine lifetimes (SystemVerilog).
2016-03-19 18:27:27 +01:00
Generalize user defined function return type handling. I'm gonna need functions to return class objects, so generalize the output types of user defined functions.
2013-04-15 03:03:21 +02:00
extern PFunction*pform_push_constructor_scope(const struct vlltype&loc);
Added support for default subroutine lifetimes (SystemVerilog).
2016-03-19 18:27:27 +01:00
extern PPackage* pform_push_package_scope(const struct vlltype&loc, perm_string name,
LexicalScope::lifetime_t lifetime);
Check for name space collisions. This patch adds code to check for most of the name space collisions. genvars are not checked correctly since they are not completely implemented.
2009-04-25 04:07:48 +02:00
extern PTask*pform_push_task_scope(const struct vlltype&loc, char*name,
Added support for default subroutine lifetimes (SystemVerilog).
2016-03-19 18:27:27 +01:00
LexicalScope::lifetime_t lifetime);
Generalize user defined function return type handling. I'm gonna need functions to return class objects, so generalize the output types of user defined functions.
2013-04-15 03:03:21 +02:00
extern PFunction*pform_push_function_scope(const struct vlltype&loc, const char*name,
Added support for default subroutine lifetimes (SystemVerilog).
2016-03-19 18:27:27 +01:00
LexicalScope::lifetime_t lifetime);
Fix file/line reported for duplicate named blocks.
2019-09-27 01:46:39 +02:00
extern PBlock*pform_push_block_scope(const struct vlltype&loc, char*name,
PBlock::BL_TYPE tt);
Objects of lexical scope use PScope base class. All the pform objects that represent lexical scope now are derived from the PScope class, and are kept in a lexical_scope table so that the scope can be managed.
2008-02-16 06:20:24 +01:00
Infrastructure for parsing analog process statements. Organize the parsing infrastructure for parsing analog processes, including holding them in scopes, and collecting analog statements.
2008-07-27 21:02:09 +02:00
extern void pform_put_behavior_in_scope(AProcess*proc);
Break sized constants into a size token and a based numeric constant.
2003-04-14 05:37:47 +02:00
extern verinum* pform_verinum_with_size(verinum*s, verinum*val,
Add file and line information for parameters, etc. This patch adds file and line information for parameters and local parameters. It also adds file/line stubs for signals in the tgt-* files. It adds the pform code needed to eventually do genvar checks and passing of genvar file/line information. It verifies that a genvar does not have the same name as a parameter/local parameter.
2008-05-06 04:46:30 +02:00
const char*file, unsigned lineno);
Break sized constants into a size token and a based numeric constant.
2003-04-14 05:37:47 +02:00
Add support for generate loops w/ wires and gates.
2006-04-10 02:37:42 +02:00
/*
* This function takes the list of names as new genvars to declare in
Fix for pr2842185 and for genvar scopes. When checking for name collisions, the compiler looks for genvar declarations in the enclosing module rather than in the current scope, which leads to false positives. The compiler also places all genvar declarations in the enclosing module scope, even when the declarations are inside a generate block which has its own scope. This patch fixes both these faults. It also fixes some typos and outdated information in comments.
2009-08-22 14:57:40 +02:00
* the current module or generate scope.
Add support for generate loops w/ wires and gates.
2006-04-10 02:37:42 +02:00
*/
Remove "using namespace std" from compiler header files and fix the fallout.
2021-11-04 17:12:04 +01:00
extern void pform_genvars(const struct vlltype&li, std::list<perm_string>*names);
Add support for generate loops w/ wires and gates.
2006-04-10 02:37:42 +02:00
Fix detection of directly nested generate constructs. If a generate construct is enclosed in a begin-end pair, it can't be directly nested (1364-2005 section 12.4.2).
2021-08-03 22:29:46 +02:00
/*
* This flag is set by the parser to indicate the current generate block
* was not enclosed in a begin-end pair. This is a pre-requisite for
* directly nesting generate constructs.
*/
extern bool pform_generate_single_item;
Add support for generate loops w/ wires and gates.
2006-04-10 02:37:42 +02:00
extern void pform_start_generate_for(const struct vlltype&li,
Add support for local genvar declaration in generate loops. As requested in GitHub issue #304.
2020-01-31 21:29:22 +01:00
bool local_index,
Add support for generate loops w/ wires and gates.
2006-04-10 02:37:42 +02:00
char*ident1,
PExpr*init,
PExpr*test,
char*ident2,
PExpr*next);
Add support for conditional generate. In the process, fix bugs related to generate used multiple times by multiple scopes causing spurious generation results. Signed-off-by: Stephen Williams <steve@icarus.com>
2007-06-22 04:04:48 +02:00
extern void pform_start_generate_if(const struct vlltype&li, PExpr*test);
extern void pform_start_generate_else(const struct vlltype&li);
Add support for generate case Generate case is a complex generate scheme where the items are sub-schemes of the case generate itself. The parser handles them something like nested generate statements, but storing the case guards as the test expression. Then the elaborator notes the case scheme and reaches into the case item schemes inside to make up tests, select the generate item, and elaborate.
2008-02-10 07:19:42 +01:00
extern void pform_start_generate_case(const struct vlltype&lp, PExpr*test);
Add support for the 1364-2001 generate of a named block. This is obsolete in 1364-2005, but is supported 1364-2001. Icarus already supported generate with unnamed block.
2008-11-15 03:35:39 +01:00
extern void pform_start_generate_nblock(const struct vlltype&lp, char*name);
Remove "using namespace std" from compiler header files and fix the fallout.
2021-11-04 17:12:04 +01:00
extern void pform_generate_case_item(const struct vlltype&lp, std::list<PExpr*>*test);
Add support for generate loops w/ wires and gates.
2006-04-10 02:37:42 +02:00
extern void pform_generate_block_name(char*name);
Correctly handle explicit and wildcard package imports. Explicit imports should always conflict with local declarations using the same name. Wildcard imports only conflict if they are referenced before a local declaration with the same name. This also unifies the detection of identifier conflicts.
2019-09-27 00:35:57 +02:00
extern void pform_endgenerate(bool end_conditional);
Add support for generate loops w/ wires and gates.
2006-04-10 02:37:42 +02:00
Detect generate regions within generate schemes. Generate schemes may nest freely, but generate regions (an anachronistic concept from 1364-2001) cannot nest, not within schemes or other regions. Have the parser detect the nesting and print an error message.
2010-03-12 01:06:02 +01:00
/*
* This function returns the lexically containing generate scheme, if
* there is one. The parser may use this to check if we are within a
* generate scheme.
*/
extern PGenerate* pform_parent_generate(void);
Add support for generate loops w/ wires and gates.
2006-04-10 02:37:42 +02:00
Generate error for invalid declarations within generate block Most things that can be declared in a module can also be declared in a generate block. But there are a few exceptions that can not be declared in generate block * module, program or interface declaration * specify block or specparam * timeunit Some of these currently work while some of them trigger an assertion and cause and application crash. Add checks to make sure that all of them these are reported as an error and do not cause a crash. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2022-02-03 10:48:42 +01:00
bool pform_error_in_generate(const vlltype&loc, const char *type);
Some clean up and add initial support for elaboration system tasks
2021-02-01 09:20:09 +01:00
extern void pform_make_elab_task(const struct vlltype&li,
perm_string name,
const std::list<PExpr*>&params);
Allow to attach additional information to typedefs Currently typedefs are just a pointer to a data_type_t. Currently typedefs are implemented by setting the name field of a data_type_t when a typedef of the type is declared. This works mostly, but there are some corner cases that can't be supported. E.g. a typedef of a typedef does not work as it overwrites the name field of the same data_type_t multiple times. Forward typedefs can also not be supported since forward typedefs allow to reference a type before it has been declared. There are also some problems with type identifier references from a higher-level scope if there is a type identifier in the current scope with the same name, but it is declared after the type identifier has been referenced. E.g. in the following x should be a vector fo width 8, but it will be a vector of width 4, because while the right type is used it is elaborated in the wrong scope. ``` localparam A = 8; typedef logic [A-1:0] T; module M; localparam A = 4; T x; typedef int T; endmodule ``` Furthermore typedefs used for the type of ports are elaborated in the wrong scope. To handle these corner case issues introduce a data_type_t for typedefs. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2022-04-23 15:05:53 +02:00
extern void pform_set_typedef(const struct vlltype&loc, perm_string name,
data_type_t*data_type,
Add support for forward type declarations SystemVerilog supports forward type declarations. This allows to declare a type identifier and use it, e.g. in a signal declaration, before declaring what the actual type is. The type still needs to be fully defined eventually in the same scope as its forward type declaration. E.g. ``` typedef T; T x; typedef int T; ``` The forward type definition can also contain the kind of the type it is going to be. E.g struct, union, class, etc. The LRM calls this the basic type. If the actual type is not of the basic type specified in the forward type declaration this is an error. E.g. ``` typedef struct T; typedef int T; // Error, int is not a struct ``` It is legal to have more than one forward type declaration for the same type name, as long as the basic type is the compatible. It is even legal to have a forward type declaration after the actual type has already been declared. E.g. ``` typedef T; typedef int T; typedef T; ``` Implement support for forward type definitions as part of the new typedef_t. The basic type will be attached to the typedef_t. The compatibility of the basic type for multiple forward type declarations will be checked in the parser. The compatibility of the basic type to the actual type will be checked during elaboration, once the actual type is known. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2022-03-31 15:08:51 +02:00
std::list<pform_range_t>*unp_ranges = nullptr);
extern void pform_forward_typedef(const struct vlltype&loc, perm_string name,
enum typedef_t::basic_type basic_type);
Implement simple typedefs, and parse type identifiers. This gets me to the point where the parser stashes a defined type, and the lexical analyzer uses the type names to differentiate IDENTIFIER and TYPE_IDENTIFIER.
2012-01-09 02:51:18 +01:00
Fix handling of wildcard-imported types. Don't add them to the explicit imports until they are referenced legally. Stop searching when a matching name is found, even if it isn't a type name.
2019-09-29 20:16:35 +02:00
extern void pform_set_type_referenced(const struct vlltype&loc, const char*name);
Parse more package items Rework lexical support for PACKAGE_IDENTIFIER so that the lexor can help with package scoped identifiers. Pform package types and package functions up to elaboration.
2013-04-01 00:46:36 +02:00
/*
Remove redundant checks for package imports during parsing. The find_* and symbol_search functions now handle this.
2019-09-22 10:16:10 +02:00
* This function makes a PECallFunction of the named function.
Parse more package items Rework lexical support for PACKAGE_IDENTIFIER so that the lexor can help with package scoped identifiers. Pform package types and package functions up to elaboration.
2013-04-01 00:46:36 +02:00
*/
extern PECallFunction* pform_make_call_function(const struct vlltype&loc,
const pform_name_t&name,
Handle tasks in packages.
2013-04-09 03:12:54 +02:00
const std::list<PExpr*>&parms);
extern PCallTask* pform_make_call_task(const struct vlltype&loc,
const pform_name_t&name,
const std::list<PExpr*>&parms);
Elaborate foreach loops as synthetic for loops. Create an implicit scope to hold the index variable, and generate a for loop to perform the functionality of the foreach.
2014-08-22 00:47:46 +02:00
extern void pform_make_foreach_declarations(const struct vlltype&loc,
std::list<perm_string>*loop_vars);
extern PForeach* pform_make_foreach(const struct vlltype&loc,
char*ident,
std::list<perm_string>*loop_vars,
Statement*stmt);
Parse more package items Rework lexical support for PACKAGE_IDENTIFIER so that the lexor can help with package scoped identifiers. Pform package types and package functions up to elaboration.
2013-04-01 00:46:36 +02:00
Introduce verilog to CVS.
1998-11-04 00:28:49 +01:00
/*
* The makewire functions announce to the pform code new wires. These
* go into a module that is currently opened.
*/
pform_set_data_type(): Avoid signal look-up by name The `pform_set_data_type()` function is used to set the data type as well as attributes on a list of signals. Currently the signals are passed as a list of signal names and then the function looks up the actual signals from the names. Refactor the code to directly pass a list of signals. This will allow to skip the look-up by name. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2022-04-17 20:57:03 +02:00
extern PWire *pform_makewire(const struct vlltype&li, perm_string name,
NetNet::Type type,
std::list<pform_range_t> *indices);
Add ranges and signed to port list declarations.
2002-05-20 04:06:01 +02:00
Generalize signals to carry types.
2005-07-07 18:22:49 +02:00
/* This form handles assignment declarations. */
packages can contain variables.
2013-04-08 01:38:48 +02:00
extern void pform_makewire(const struct vlltype&li,
std::list<PExpr*>*delay,
str_pair_t str,
std::list<decl_assignment_t*>*assign_list,
NetNet::Type type,
pform_makewire(): Allow to specify attributes There are a few places where pform_makewire() is used and attributes can be attached to the created net or variable. At the moment pform_makewire() doesn't allow to specify the attributes, and they either get dropped silently or with a warning. Add support for passing the attributes to pform_makewire() which will then pass it on to pform_set_data_type() to attach it to the declared net or variable. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2022-01-22 09:56:07 +01:00
data_type_t*data_type,
std::list<named_pexpr_t>*attr = 0);
packages can contain variables.
2013-04-08 01:38:48 +02:00
Add helper function for creating variable declarations Variables don't have a delay or strength and the NetNet::Type is known. Add a small wrapper around pform_makewire() that can be used to create variables. This will allow to reduce the boilerplate code for variable declarations. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2022-01-22 17:22:18 +01:00
extern void pform_make_var(const struct vlltype&loc,
std::list<decl_assignment_t*>*assign_list,
data_type_t*data_type,
std::list<named_pexpr_t>*attr = 0);
Handle nets that are packed structures.
2011-12-18 21:00:18 +01:00
Fully support variable initialization in tasks/functions/named blocks.
2016-03-19 14:04:38 +01:00
extern void pform_make_var_init(const struct vlltype&li,
perm_string name, PExpr*expr);
Parse port_declaration_lists from the 2001 Standard.
2002-05-20 01:37:28 +02:00
Fix for br974 - support SV types in non-ansi port declarations.
2016-04-04 21:40:30 +02:00
/* This function is used when we have an incomplete port definition in
a non-ansi style declaration. Look up the names of the wires, and set
the port type, i.e. input, output or inout, and, if specified, the
range and signedness. If the wire does not exist, create it. */
Coerse input to inout when assigned to.
2001-11-10 03:08:49 +01:00
extern void pform_set_port_type(const struct vlltype&li,
Remove "using namespace std" from compiler header files and fix the fallout.
2021-11-04 17:12:04 +01:00
std::list<pform_port_t>*ports,
Fix for br930 - support attributes on old-style port declarations.
2013-05-19 10:16:24 +02:00
NetNet::PortType,
Fix for br974 - support SV types in non-ansi port declarations.
2016-04-04 21:40:30 +02:00
data_type_t*dt,
Remove "using namespace std" from compiler header files and fix the fallout.
2021-11-04 17:12:04 +01:00
std::list<named_pexpr_t>*attr);
Bunches more SystemVerilog syntax.
2012-03-10 03:54:05 +01:00
pform_set_data_type(): Avoid signal look-up by name The `pform_set_data_type()` function is used to set the data type as well as attributes on a list of signals. Currently the signals are passed as a list of signal names and then the function looks up the actual signals from the names. Refactor the code to directly pass a list of signals. This will allow to skip the look-up by name. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2022-04-17 20:57:03 +02:00
extern void pform_set_data_type(const struct vlltype&li,
data_type_t *data_type,
std::vector<PWire*> *wires,
NetNet::Type net_type,
std::list<named_pexpr_t>*attr);
Finish up parser code for enum types This gets the parser syntax actions done, up to the pform code. It is ready for generating pform structures.
2010-10-24 20:21:17 +02:00
Output an error message when a SV variable declaration reuses a name. Assertion failures are not the right way to handle user code errors.
2018-02-18 18:51:56 +01:00
extern void pform_set_string_type(const struct vlltype&li, const string_type_t*string_type, std::list<perm_string>*names, NetNet::Type net_type, std::list<named_pexpr_t>*attr);
Parse support for struct variables.
2011-12-04 02:16:01 +01:00
Output an error message when a SV variable declaration reuses a name. Assertion failures are not the right way to handle user code errors.
2018-02-18 18:51:56 +01:00
extern void pform_set_class_type(const struct vlltype&li, class_type_t*class_type, std::list<perm_string>*names, NetNet::Type net_type, std::list<named_pexpr_t>*addr);
Elaborate class_new and (null) expressions This gets the types right for class_new and null expressions, and elaborate them down to the ivl_target.h API.
2012-11-12 02:42:31 +01:00
Add language support for Verilog-2001 attribute syntax. Hook this support into existing $attribute handling, and add number and void value types. Add to the ivl_target API new functions for access of complex attributes attached to gates.
2002-05-23 05:08:50 +02:00
/* pform_set_attrib and pform_set_type_attrib exist to support the
$attribute syntax, which can only set string values to
attributes. The functions keep the value strings that are
passed in. */
Addtrbute keys are perm_strings.
2004-02-20 19:53:33 +01:00
extern void pform_set_attrib(perm_string name, perm_string key,
Add language support for Verilog-2001 attribute syntax. Hook this support into existing $attribute handling, and add number and void value types. Add to the ivl_target API new functions for access of complex attributes attached to gates.
2002-05-23 05:08:50 +02:00
char*value);
Remove "using namespace std" from compiler header files and fix the fallout.
2021-11-04 17:12:04 +01:00
extern void pform_set_type_attrib(perm_string name, const std::string&key,
Add language support for Verilog-2001 attribute syntax. Hook this support into existing $attribute handling, and add number and void value types. Add to the ivl_target API new functions for access of complex attributes attached to gates.
2002-05-23 05:08:50 +02:00
char*value);
Support parameter, localparam, and event declarations in any scope. Currently, parameters and localparams declared in tasks, functions, generate blocks, and named blocks are placed in the parent module scope. Event declarations in these scopes are not permitted (a syntax error is reported). This patch corrects this behaviour, so that all the above declarations are accepted and are placed in the scope in which they are declared. Note that the IEEE standard does not permit parameter declarations in generate blocks. This patch causes the parser to reject such declarations.
2008-09-17 22:25:59 +02:00
extern LexicalScope::range_t* pform_parameter_value_range(bool exclude_flag,
Parse parameter value ranges into pform. Handle parameter value ranges as far as the pform. The +-inf expressions are not handled yet, nor is the single value exclude, but the other cases are handled.
2008-05-13 06:26:38 +02:00
bool low_open, PExpr*low_expr,
bool hig_open, PExpr*hig_expr);
extern void pform_set_parameter(const struct vlltype&loc,
perm_string name,
Support type parameters SystemVerilog supports type parameters. These are similar to value parameters, but they allow to pass a type to a module or similar when instantiating it. E.g. ``` module A #(parameter type T = int); endmodule module B; A #(.T(real)) i_a; endmodule ``` Add support for handling type parameters. For the vlog95 and vhdl backends type parameters, similar to typedefs, get replaced with their actual value. For modules with non-local type parameters for each module instance a unique module or architecture is generated with the actual type. Querying type parameters through VPI is not yet supported. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2021-12-20 17:00:24 +01:00
bool is_local, bool is_type,
Rework parsing of parameter types Use the common data_type_or_implicit rules to support type definitions for parameters. This eliminates a bunch of special rules in parse.y, and opens the door for parameters having more complex types.
2020-12-25 03:12:06 +01:00
data_type_t*data_type,
Support parameter, localparam, and event declarations in any scope. Currently, parameters and localparams declared in tasks, functions, generate blocks, and named blocks are placed in the parent module scope. Event declarations in these scopes are not permitted (a syntax error is reported). This patch corrects this behaviour, so that all the above declarations are accepted and are placed in the scope in which they are declared. Note that the IEEE standard does not permit parameter declarations in generate blocks. This patch causes the parser to reject such declarations.
2008-09-17 22:25:59 +02:00
PExpr*expr, LexicalScope::range_t*value_range);
Allow specparam declarations outside specify blocks. This patch extends the compiler to support all specparam declarations allowed by the 1364-2005 standard. For compatibility with other simulators, it allows specparam values to be used in any constant expression, but outputs a warning message and disables run-time annotation of a specparam if it is used in an expression that must be evaluated at compile time.
2012-05-07 00:11:26 +02:00
extern void pform_set_specparam(const struct vlltype&loc,
perm_string name,
Remove "using namespace std" from compiler header files and fix the fallout.
2021-11-04 17:12:04 +01:00
std::list<pform_range_t>*range,
Allow specparam declarations outside specify blocks. This patch extends the compiler to support all specparam declarations allowed by the 1364-2005 standard. For compatibility with other simulators, it allows specparam values to be used in any constant expression, but outputs a warning message and disables run-time annotation of a specparam if it is used in an expression that must be evaluated at compile time.
2012-05-07 00:11:26 +02:00
PExpr*expr);
Rework the heirarchical identifier parse syntax and pform to handle more general combinations of heirarch and bit selects.
2007-05-24 06:07:11 +02:00
extern void pform_set_defparam(const pform_name_t&name, PExpr*expr);
Carry Verilog 2001 attributes with processes, all the way through to the ivl_target API. Divide signal reference counts between rval and lval references.
2002-05-26 03:39:02 +02:00
Add initial parsing for let construct
2021-01-18 22:01:23 +01:00
extern void pform_make_let(const struct vlltype&loc,
perm_string name,
Remove "using namespace std" from compiler header files and fix the fallout.
2021-11-04 17:12:04 +01:00
std::list<PLet::let_port_t*>*ports,
Add initial parsing for let construct
2021-01-18 22:01:23 +01:00
PExpr*expr);
extern PLet::let_port_t* pform_make_let_port(data_type_t*data_type,
perm_string name,
Remove "using namespace std" from compiler header files and fix the fallout.
2021-11-04 17:12:04 +01:00
std::list<pform_range_t>*range,
Add initial parsing for let construct
2021-01-18 22:01:23 +01:00
PExpr*def);
specparams as far as pform.
2003-02-27 07:45:11 +01:00
/*
* Functions related to specify blocks.
*/
Basic support for specify timing.
2006-09-23 06:57:19 +02:00
extern PSpecPath*pform_make_specify_path(const struct vlltype&li,
Remove "using namespace std" from compiler header files and fix the fallout.
2021-11-04 17:12:04 +01:00
std::list<perm_string>*src, char pol,
bool full_flag, std::list<perm_string>*dst);
Parse all specify paths to pform.
2007-02-12 02:52:21 +01:00
extern PSpecPath*pform_make_specify_edge_path(const struct vlltype&li,
Parse edge sensitive paths without edge specifier.
2007-04-13 04:34:35 +02:00
int edge_flag, /*posedge==true */
Remove "using namespace std" from compiler header files and fix the fallout.
2021-11-04 17:12:04 +01:00
std::list<perm_string>*src, char pol,
bool full_flag, std::list<perm_string>*dst,
Parse all specify paths to pform.
2007-02-12 02:52:21 +01:00
PExpr*data_source_expression);
Remove "using namespace std" from compiler header files and fix the fallout.
2021-11-04 17:12:04 +01:00
extern PSpecPath*pform_assign_path_delay(PSpecPath*obj, std::list<PExpr*>*delays);
Parse all specify paths to pform.
2007-02-12 02:52:21 +01:00
Basic support for specify timing.
2006-09-23 06:57:19 +02:00
extern void pform_module_specify_path(PSpecPath*obj);
specparams as far as pform.
2003-02-27 07:45:11 +01:00
Handle delayed signals in timing checks as assignments
2023-07-05 16:22:08 +02:00
/*
* Functions related to timing checks.
*/
extern PRecRem* pform_make_rec_rem(const struct vlltype&li,
PTimingCheck::event_t&reference_event,
PTimingCheck::event_t&data_event,
PExpr&setup_limit,
PExpr&hold_limit,
pform_name_t* notifier,
pform_name_t* timestamp_cond,
pform_name_t* timecheck_cond,
pform_name_t* delayed_reference,
pform_name_t* delayed_data
);
extern PSetupHold* pform_make_setup_hold(const struct vlltype&li,
PTimingCheck::event_t&reference_event,
PTimingCheck::event_t&data_event,
PExpr&setup_limit,
PExpr&hold_limit,
pform_name_t* notifier,
pform_name_t* timestamp_cond,
pform_name_t* timecheck_cond,
pform_name_t* delayed_reference,
pform_name_t* delayed_data
);
extern void pform_module_timing_check(PTimingCheck*obj);
Carry Verilog 2001 attributes with processes, all the way through to the ivl_target API. Divide signal reference counts between rval and lval references.
2002-05-26 03:39:02 +02:00
/*
* pform_make_behavior creates processes that are declared with always
* or initial items.
*/
Infrastructure for elaborating analog statements. Put together the infrastructure for elaborating analog statements, including create the NetAnalogTop objects that hold analog statements and are in turn held by the design. While doing this, clean up the various unique initial/always enumerations to use the ivl_process_type_t type.
2008-10-22 07:15:49 +02:00
extern PProcess* pform_make_behavior(ivl_process_type_t, Statement*,
Remove "using namespace std" from compiler header files and fix the fallout.
2021-11-04 17:12:04 +01:00
std::list<named_pexpr_t>*attr);
Add support for synthesis translate meta-comments.
2014-07-16 03:03:40 +02:00
extern void pform_mc_translate_on(bool flag);
Introduce verilog to CVS.
1998-11-04 00:28:49 +01:00
Remove "using namespace std" from compiler header files and fix the fallout.
2021-11-04 17:12:04 +01:00
extern std::vector<PWire*>* pform_make_udp_input_ports(std::list<perm_string>*);
Parse UDP primitives all the way to pform.
1998-11-25 03:35:53 +01:00
parser: Consistently pass line information as `vlltype` Currently there is a mix of passing line information either as `struct vlltype` or as a separate `const char *file` and `unsigned lineno`. For consistency always use the struct vlltype variant. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2022-01-10 11:21:14 +01:00
extern void pform_make_events(const struct vlltype&loc,
std::list<perm_string>*names);
Introduce verilog to CVS.
1998-11-04 00:28:49 +01:00
/*
* The makegate function creates a new gate (which need not have a
* name) and connects it to the specified wires.
*/
Disallow modules/gates in program blocks.
2012-05-15 04:13:57 +02:00
extern void pform_makegates(const struct vlltype&loc,
PGBuiltin::Type type,
Deliver gate output strengths to the netlist.
2000-05-08 07:30:19 +02:00
struct str_pair_t str,
Remove "using namespace std" from compiler header files and fix the fallout.
2021-11-04 17:12:04 +01:00
std::list<PExpr*>*delay,
Replace svector with std::vector The custom `svector` class is essentially a subset of `std::vector`. There is no inherent advantage to using `svector`. Both have the same memory footprint. `svector` was designed to be of static size, but there are a few places in the parser where it has to grow at runtime. Handling this becomes a bit easier by switching to `std::vector` since it is possible to use its methods which take care of resizing the vector. This also allows to remove the unused parameter of the `lgate` struct constructor, which was only needed for compatibility with `svector`. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2022-02-17 10:48:43 +01:00
std::vector<lgate>*gates,
Remove "using namespace std" from compiler header files and fix the fallout.
2021-11-04 17:12:04 +01:00
std::list<named_pexpr_t>*attr);
Introduce verilog to CVS.
1998-11-04 00:28:49 +01:00
Disallow modules/gates in program blocks.
2012-05-15 04:13:57 +02:00
extern void pform_make_modgates(const struct vlltype&loc,
perm_string type,
Support named parameter override lists.
2000-01-09 06:50:48 +01:00
struct parmvalue_t*overrides,
Replace svector with std::vector The custom `svector` class is essentially a subset of `std::vector`. There is no inherent advantage to using `svector`. Both have the same memory footprint. `svector` was designed to be of static size, but there are a few places in the parser where it has to grow at runtime. Handling this becomes a bit easier by switching to `std::vector` since it is possible to use its methods which take care of resizing the vector. This also allows to remove the unused parameter of the `lgate` struct constructor, which was only needed for compatibility with `svector`. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2022-02-17 10:48:43 +01:00
std::vector<lgate>*gates,
Remove "using namespace std" from compiler header files and fix the fallout.
2021-11-04 17:12:04 +01:00
std::list<named_pexpr_t>*attr);
Introduce verilog to CVS.
1998-11-04 00:28:49 +01:00
/* Make a continuous assignment node, with optional bit- or part- select. */
parser: Consistently pass line information as `vlltype` Currently there is a mix of passing line information either as `struct vlltype` or as a separate `const char *file` and `unsigned lineno`. For consistency always use the struct vlltype variant. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2022-01-10 11:21:14 +01:00
extern void pform_make_pgassign_list(const struct vlltype&loc,
std::list<PExpr*>*alist,
Remove "using namespace std" from compiler header files and fix the fallout.
2021-11-04 17:12:04 +01:00
std::list<PExpr*>*del,
parser: Consistently pass line information as `vlltype` Currently there is a mix of passing line information either as `struct vlltype` or as a separate `const char *file` and `unsigned lineno`. For consistency always use the struct vlltype variant. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2022-01-10 11:21:14 +01:00
struct str_pair_t str);
Elaborate task input ports.
1999-07-24 04:11:19 +02:00
Handle task/function default expressions in parsing/pform. This gets it to (but not through) the elaborator.
2013-09-14 02:04:25 +02:00
extern std::vector<pform_tf_port_t>*pform_make_task_ports(const struct vlltype&loc,
More class syntax Part of ongoing parser work to support SystemVerilog classes.
2012-02-19 19:29:50 +01:00
NetNet::PortType pt,
data_type_t*vtype,
Support unpacked array dimensions on non-ansi style task ports SystemVerilog allows unpacked array dimensions on non-ANSI style task and function ports. To support this refactor pform_make_task_ports() to accept a of pform_port_t, which in addition to the identifier name also allows to specify per port unpacked dimensions. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2022-02-19 22:44:02 +01:00
std::list<pform_port_t>*ports,
Support SystemVerilog types for non-ansi task port declarations Tasks and functions support two types of port declarations. Either ANSI style, in parenthesis after the task name, or non-ANSI style, as declaration statements in the task body. In the current implementation SystemVerilog types are only accept for ANSI style port declarations, while non-ANSI style only accept Verilog types (reg, integer, time, real). Add support for SystemVerilog data types for non-ansi style ports. This also makes the parsing rules simpler since we can use `data_type` to match all data types and don't need a explicit rule for each supported data type. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2022-01-04 16:16:08 +01:00
bool allow_implicit = false);
More class syntax Part of ongoing parser work to support SystemVerilog classes.
2012-02-19 19:29:50 +01:00
Implement increment/decrement statements. During parse/pform processing, convert increment statements to the equivalent compressed assignment statement. This is less weird for elaboration processing and better expresses what is going on.
2012-02-20 03:54:58 +01:00
/*
* The parser uses this function to convert a unary
Spelling refresh
2012-04-07 01:38:38 +02:00
* increment/decrement expression to the equivalent compressed
Implement increment/decrement statements. During parse/pform processing, convert increment statements to the equivalent compressed assignment statement. This is less weird for elaboration processing and better expresses what is going on.
2012-02-20 03:54:58 +01:00
* assignment statement.
*/
extern PAssign* pform_compressed_assign_from_inc_dec(const struct vlltype&loc,
PExpr*exp);
Elaborate task input ports.
1999-07-24 04:11:19 +02:00
Add support for increment/decrement operators in generate loop iteration. As requested in GitHub issue #303.
2020-01-30 22:45:04 +01:00
/*
* The parser uses this function to convert a genvar increment/decrement
* expression to the equivalent binary add/subtract expression.
*/
extern PExpr* pform_genvar_inc_dec(const struct vlltype&loc, const char*name,
bool inc_flag);
Support compressed assignment statements for genvar loops SystemVerilog supports using compressed assignment operators for the genvar for loop variable update. Add support for this in a similar way as increment/decrement operators by transforming the statement to its uncompressed equivalent. E.g. `x += y` gets transformed to `x = x + y`. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2022-10-04 00:09:25 +02:00
extern PExpr* pform_genvar_compressed(const struct vlltype &loc,
const char *name, char op, PExpr *rval);
Introduce verilog to CVS.
1998-11-04 00:28:49 +01:00
/*
* These are functions that the outside-the-parser code uses the do
Spelling fixes only comments and documentation some punctuation and capitalization for good measure Changelogs are purposefully untouched
2008-01-29 21:19:59 +01:00
* interesting things to the Verilog. The parse function reads and
Introduce verilog to CVS.
1998-11-04 00:28:49 +01:00
* parses the source file and places all the modules it finds into the
* mod list. The dump function dumps a module to the output stream.
*/
Remove "using namespace std" from compiler header files and fix the fallout.
2021-11-04 17:12:04 +01:00
extern void pform_dump(std::ostream&out, Module*mod);
Introduce verilog to CVS.
1998-11-04 00:28:49 +01:00
Parse disciplines and contribution statements Parse discipline declarations, net discipline declarations, and analog contribution statements. Don't yet do anything useful with these, just give a sorry message where they are encountered.
2008-05-11 21:00:11 +02:00
/* ** pform_discipline.cc
* Functions for handling the parse of natures and disciplines. These
* functions are in pform_disciplines.cc
*/
Attach natures to disciplines Pform parse enough of the natures that they can be mapped and the disciplines can bind to them. Since Verilog-AMS expects natures to be declared before use, we can do the binding early.
2008-05-12 03:52:27 +02:00
extern void pform_start_nature(const char*name);
extern void pform_end_nature(const struct vlltype&loc);
extern void pform_nature_access(const struct vlltype&loc, const char*name);
Parse disciplines and contribution statements Parse discipline declarations, net discipline declarations, and analog contribution statements. Don't yet do anything useful with these, just give a sorry message where they are encountered.
2008-05-11 21:00:11 +02:00
extern void pform_start_discipline(const char*name);
extern void pform_end_discipline(const struct vlltype&loc);
Bring signal discipline all the way to the ivl_target API. Signals may have VMA disciplines attached. Make the attached discipline visible through the ivl_target.h API. Also, re-arrange the internal handling of the discipline structure so that we can expose disciplines through the ivl_target C API without creating new structures. The t-dll-api implementations of the discipline access functions can look at the elaborated discipline structure directly. This is possible since the discipline parse and elaboration are very simple.
2008-11-02 17:10:41 +01:00
extern void pform_discipline_domain(const struct vlltype&loc, ivl_dis_domain_t use_domain);
Attach natures to disciplines Pform parse enough of the natures that they can be mapped and the disciplines can bind to them. Since Verilog-AMS expects natures to be declared before use, we can do the binding early.
2008-05-12 03:52:27 +02:00
extern void pform_discipline_potential(const struct vlltype&loc, const char*name);
extern void pform_discipline_flow(const struct vlltype&loc, const char*name);
Parse disciplines and contribution statements Parse discipline declarations, net discipline declarations, and analog contribution statements. Don't yet do anything useful with these, just give a sorry message where they are encountered.
2008-05-11 21:00:11 +02:00
extern void pform_attach_discipline(const struct vlltype&loc,
Remove "using namespace std" from compiler header files and fix the fallout.
2021-11-04 17:12:04 +01:00
ivl_discipline_t discipline, std::list<perm_string>*names);
Parse disciplines and contribution statements Parse discipline declarations, net discipline declarations, and analog contribution statements. Don't yet do anything useful with these, just give a sorry message where they are encountered.
2008-05-11 21:00:11 +02:00
Remove "using namespace std" from compiler header files and fix the fallout.
2021-11-04 17:12:04 +01:00
extern void pform_dump(std::ostream&out, const ivl_nature_s*);
extern void pform_dump(std::ostream&out, const ivl_discipline_s*);
Parse disciplines and contribution statements Parse discipline declarations, net discipline declarations, and analog contribution statements. Don't yet do anything useful with these, just give a sorry message where they are encountered.
2008-05-11 21:00:11 +02:00
Infrastructure for parsing analog process statements. Organize the parsing infrastructure for parsing analog processes, including holding them in scopes, and collecting analog statements.
2008-07-27 21:02:09 +02:00
/* ** pform_analog.cc
*/
extern void pform_make_analog_behavior(const struct vlltype&loc,
Basic elaboration of analog contribution statements. Get at least basic elaboration of analog processes and contribution statements. Bring the statements and analog statements together and net future elaboration work sort out which statements are valid in a given context. This makes sense because there really is a lot of syntactic overlap, and analog behavioral code is processed somewhat sequentially.
2008-10-23 06:56:00 +02:00
ivl_process_type_t type, Statement*st);
Infrastructure for parsing analog process statements. Organize the parsing infrastructure for parsing analog processes, including holding them in scopes, and collecting analog statements.
2008-07-27 21:02:09 +02:00
Basic elaboration of analog contribution statements. Get at least basic elaboration of analog processes and contribution statements. Bring the statements and analog statements together and net future elaboration work sort out which statements are valid in a given context. This makes sense because there really is a lot of syntactic overlap, and analog behavioral code is processed somewhat sequentially.
2008-10-23 06:56:00 +02:00
extern AContrib*pform_contribution_statement(const struct vlltype&loc,
PExpr*lval, PExpr*rval);
Infrastructure for parsing analog process statements. Organize the parsing infrastructure for parsing analog processes, including holding them in scopes, and collecting analog statements.
2008-07-27 21:02:09 +02:00
Parse contribution statements as far as pform. Contribution statements have an l-value and r-value. Parse those expressions into pform so that elaboration has something to work with. In this process, this patch also changes the PECallFunction class to use the vector template instead of the svector template. The latter doesn't add anything over the STL vector template, so this is a start of working the svector out.
2008-07-27 23:22:19 +02:00
extern PExpr* pform_make_branch_probe_expression(const struct vlltype&loc,
char*name, char*n1, char*n2);
extern PExpr* pform_make_branch_probe_expression(const struct vlltype&loc,
char*name, char*branch);
Add function to define parameter from command line This patch is based on one from "bruce <bruce1914@gmail.com>". I've applied all but the elaboration code, which I rewrote to properly work with the elaboration work queue. I also constrained the implementation so that the parameter name must have exactly two components: the root scope name and the parameter name. This is necessary to keep the defparm processing sane. The comments from bruce's original patch are as follows: -- This patch would provide function to define parameter from command line. This serves the same functionality as 'defparam' in Verilog source code, but provide much more ease for using. Parameter definition can be write in command file, with following syntax: +parameter+<scope>.<parameter>=<val> *Do not apply any space between them* The scope name should be full hierachical name with root name at the begining. The following example would override test.T1 with new value 2'b01: +parameter+test.T1=2'b01 'test' here is the root module name. The parameter value here should be constant. Parameter definition can also be write in the command line: iverilog -Ptest.T1=2'b01 This serves the same functionality with the previous example. If we define the same parameter in command file and command line, the one in command line would over-write all others.
2009-08-06 23:42:13 +02:00
Revert bad merge from vhdl branch
2010-10-02 20:02:27 +02:00
/*
Add function to define parameter from command line This patch is based on one from "bruce <bruce1914@gmail.com>". I've applied all but the elaboration code, which I rewrote to properly work with the elaboration work queue. I also constrained the implementation so that the parameter name must have exactly two components: the root scope name and the parameter name. This is necessary to keep the defparm processing sane. The comments from bruce's original patch are as follows: -- This patch would provide function to define parameter from command line. This serves the same functionality as 'defparam' in Verilog source code, but provide much more ease for using. Parameter definition can be write in command file, with following syntax: +parameter+<scope>.<parameter>=<val> *Do not apply any space between them* The scope name should be full hierachical name with root name at the begining. The following example would override test.T1 with new value 2'b01: +parameter+test.T1=2'b01 'test' here is the root module name. The parameter value here should be constant. Parameter definition can also be write in the command line: iverilog -Ptest.T1=2'b01 This serves the same functionality with the previous example. If we define the same parameter in command file and command line, the one in command line would over-write all others.
2009-08-06 23:42:13 +02:00
* Parse configuration file with format <key>=<value>, where key
* is the hierarchical name of a valid parameter name and value
* is the value user wants to assign to. The value should be constant.
*/
Remove "using namespace std" from compiler header files and fix the fallout.
2021-11-04 17:12:04 +01:00
extern void parm_to_defparam_list(const std::string&param);
Add function to define parameter from command line This patch is based on one from "bruce <bruce1914@gmail.com>". I've applied all but the elaboration code, which I rewrote to properly work with the elaboration work queue. I also constrained the implementation so that the parameter name must have exactly two components: the root scope name and the parameter name. This is necessary to keep the defparm processing sane. The comments from bruce's original patch are as follows: -- This patch would provide function to define parameter from command line. This serves the same functionality as 'defparam' in Verilog source code, but provide much more ease for using. Parameter definition can be write in command file, with following syntax: +parameter+<scope>.<parameter>=<val> *Do not apply any space between them* The scope name should be full hierachical name with root name at the begining. The following example would override test.T1 with new value 2'b01: +parameter+test.T1=2'b01 'test' here is the root module name. The parameter value here should be constant. Parameter definition can also be write in the command line: iverilog -Ptest.T1=2'b01 This serves the same functionality with the previous example. If we define the same parameter in command file and command line, the one in command line would over-write all others.
2009-08-06 23:42:13 +02:00
System Verilog timeunit and timeprecision addition This patch adds timeunit and timeprecision keywords.Use -gsystem-verilog generation flag to use this feature
2009-06-20 05:58:46 +02:00
/*
Fix up original SV timeunit/timeprecision patch. This patch modifies the original SystemVerilog timeunit/timeprecision patch in the following way: Removed trailing space. Reworked some code to use standard spacing rules. Added some comments. Combined some code. Major rework of local/global timeunit/timeprecision logic. Major rework of timeunit/timeprecision declaration/check code. This was needed to remove the shift/reduce warnings. Add a number of checks for invalid combinations.
2009-07-11 03:19:59 +02:00
* Tasks to set the timeunit or timeprecision for SystemVerilog.
System Verilog timeunit and timeprecision addition This patch adds timeunit and timeprecision keywords.Use -gsystem-verilog generation flag to use this feature
2009-06-20 05:58:46 +02:00
*/
Add support for SystemVerilog style time literals SystemVerilog has support for time literals. The time literal for example #10ns, adds a delay of 10ns no matter the time unit currently in effect. For more details please refer to http://iverilog.wikia.com/wiki/Projects#SystemVerilog_Style_Time_Literals Tested-by: Oswaldo Cadenas <oswaldo.cadenas@gmail.com> Signed-off-by: Prasad Joshi <prasadjoshi124@gmail.com>
2011-07-05 19:11:56 +02:00
extern bool get_time_unit(const char*cp, int &unit);
extern int pform_get_timeunit();
Time literals need to be rounded using the time precision
2021-02-13 10:10:38 +01:00
extern int pform_get_timeprec();
Fix a couple of minor bugs in the timescale parsing rework.
2017-11-06 01:37:56 +01:00
extern void pform_set_timeunit(const char*txt, bool initial_decl);
extern void pform_set_timeprec(const char*txt, bool initial_decl);
/*
* Flags to determine whether this is an initial declaration.
*/
extern bool allow_timeunit_decl;
extern bool allow_timeprec_decl;
System Verilog timeunit and timeprecision addition This patch adds timeunit and timeprecision keywords.Use -gsystem-verilog generation flag to use this feature
2009-06-20 05:58:46 +02:00
Put enum type into scope when declaring it When creating an enum type it must be added to the scope where it is declared so it can later be elaborated and the enum and its names can be referenced in expressions. In addition the names of the enum must be added to the lexor scope so that name collisions are detected and can be reported as errors. This is done with pform_put_enum_type_in_scope() function. At the moment the function is called from two different places * When adding a typedef of a enum type * When creating a signal of a enum type In addition the enum_type_t is added to a class scope `enum_sets` when declaring a enum property in a class. But this only makes sure that the enum gets elaborated, its names are not added to the lexor scope. This works fine for the most part, but breaks for a few corner cases. E.g. it is possible to declare a enum type as part of the subtype of another packed type such as structs or packed arrays. E.g. ``` struct packed { enum { A } e; } s; ``` This is not covered by either of the cases above and neither do the names of the enum get added to the lexor scope, nor is the enum type elaborated. Another corner case that is currently not working is declaring a class property where the type is a typedef of a enum that is declared outside of the class. In this case the enum is elaborated again inside the class scope. E.g. the below is supposed to work, but fails with an already declared symbol error. ``` typedef enum { A } e_t; class C; typedef enum { A } e1; e_t e2; endclass ``` In addition since for enums declared in classes they are only added to `enum_sets`, but names are not added to the lexor scope, it is possible to declare a different symbol in the class scope with the same name. E.g. the following elaborates fine ``` class C; enum { A } e; typedef int A; endclass ``` To fix this call pform_put_enum_type_in_scope() when the enum_type_t is created in the parser. This makes sure that it is handled the same regardless where the type is declared or used. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2022-01-15 13:08:32 +01:00
void pform_put_enum_type_in_scope(enum_type_t*enum_set);
Add helper function to emit error when SystemVerilog is requried When encountering a construct that requires SystemVerilog in most cases an error message is generated when SystemVerilog is not enabled and parsing simply continues. Factor the checking and generating of the error message into a helper function. This slightly reduces boiler plate code and gives consistent error messages. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2022-02-05 10:49:34 +01:00
bool pform_requires_sv(const struct vlltype&loc, const char *feature);
Support parameters without default value SystemVerilog allows to omit the default value of a parameter declared in a parameter port list. In this case the parameter must be overridden for every module instance. This is defined in section 6.20.1 ("Parameter declaration syntax") of the LRM (1800-2017). In addition a module that has a parameter without a default value does not qualify for automatic toplevel module selection. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2022-02-10 14:03:46 +01:00
void pform_start_parameter_port_list();
void pform_end_parameter_port_list();
Report errors for nets with invalid data type While a variable can have any data type the data type for nets is quite restricted. The SystemVerilog LRM section 6.7.1 ("Net declarations with built-in net types") requires that the data type of a wire is either a 4-state packed or a unpacked struct or unpacked array of 4-state packed types. As an extension to this iverilog allows real data type for wires as well as 2-state packed types. Add a check that reports an error if a net with any other type is declared. In addition in Verilog a net can not have an explicit data type at all. It can only have a packed dimension and a signed flag. As an extension to this Icarus also allows wires to be of `real` data type. Note that in Verilog mode the data type is checked in the parser since only the parser knows whether the data type is an implicit type (`input reg [7:0]` and `input [7:0] x` elaborate the same). But for SystemVerilog the type is checked during elaboration since due to forward typedefs and type parameters the type is not necessarily known in the parser. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2022-01-20 15:59:28 +01:00
void pform_check_net_data_type(const struct vlltype&loc, NetNet::Type net_type,
const data_type_t *data_type);
Update header files to use a more standard name to prevent rereading This is from github report #16. There are likely a few more issues that need to be addressed though this takes care of the major ones.
2014-07-23 22:39:29 +02:00
#endif /* IVL_pform_H */