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Introduce shell of vhdlpp program. Create the makefiles and configuration scripts to hold together the vhdlpp front-end program. Create a shell main.
2010-12-13 05:02:18 +01:00
%{
/*
* Copyright (c) 2011 Stephen Williams (steve@icarus.com)
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
# include "vhdlpp_config.h"
Added full number, based number (both int and float), string and character literals handling
2011-02-04 17:51:51 +01:00
# include "vhdlint.h"
Introductory changes for numbers handling
2011-01-31 18:25:29 +01:00
# include "vhdlreal.h"
Parse create entities with ports Create entity objects from entity declarations in the source, and populate them with ports.
2011-01-03 07:30:09 +01:00
# include "compiler.h"
Introduce shell of vhdlpp program. Create the makefiles and configuration scripts to hold together the vhdlpp front-end program. Create a shell main.
2010-12-13 05:02:18 +01:00
# include "parse_api.h"
Create an Architecture class and bind them to their entities.
2011-01-24 05:26:27 +01:00
# include "parse_misc.h"
# include "architec.h"
Add parse decorations for expressions. Elaboration will need a parse tree for expressions. Create one for the expression types that are currently supported. Also add rules and the keywords for all the remaining binary logical operators.
2011-01-30 02:27:30 +01:00
# include "expression.h"
Parse component declarations / parse signal declarations. These go into the architecture/block of their scope and will be used by component instantiations to make sure the bindings are correct and complete. Also handle signal declarations. The elaborator will use these to generate module local variables that are used by the architecture.
2011-03-22 17:16:20 +01:00
# include "vsignal.h"
Do type mapping in the parser. In VHDL, types are declared before they are used, so it is possible to do type binding during parse. This makes the parser a little bit cleaner.
2011-02-14 01:37:10 +01:00
# include "vtype.h"
Flesh out VHDL parser engine. Add enough rules to parse a simple VHDL program: Parse library and use clauses, Parse entity declarations, and Parse architecture bodies. Add some parser infrastructure: Handle syntax errors with useful error messages, Include file name and line numbers in parse errors, Add some parser debug aids.
2010-12-15 06:36:47 +01:00
# include <cstdarg>
Add use clause parsing Up till now only "global" use clauses were parsed and as a result libraries were loaded. Since use clauses can appear not only in global context, parsing of non-global clauses has been introduced and selected names are now handled (like name1.name2.name3).
2011-03-29 10:33:09 +02:00
# include <cstring>
Parse create entities with ports Create entity objects from entity declarations in the source, and populate them with ports.
2011-01-03 07:30:09 +01:00
# include <list>
Parse component declarations / parse signal declarations. These go into the architecture/block of their scope and will be used by component instantiations to make sure the bindings are correct and complete. Also handle signal declarations. The elaborator will use these to generate module local variables that are used by the architecture.
2011-03-22 17:16:20 +01:00
# include <map>
Add use clause parsing Up till now only "global" use clauses were parsed and as a result libraries were loaded. Since use clauses can appear not only in global context, parsing of non-global clauses has been introduced and selected names are now handled (like name1.name2.name3).
2011-03-29 10:33:09 +02:00
# include <vector>
Basic elaboration of vhdl component instantiations. This gets us as far as emiting a component instantiation. Very little error checking/elaboration is done, so there is room for improvement, but this is a working stub.
2011-04-01 03:50:48 +02:00
# include "parse_types.h"
Add more complete support for vhdl local signals. These signals are declared in the architecture and are local to the module. The Architecture already parsed and stored these signal declarations, but this patch adds the ability to actually emit these signals in the generated code. In the process of doing this, I had to regularize the elaboration and emit of VTypes, so that it can be used in multiple places, not just in entity headers (for ports). I also added support for bit selects of signals. This effected a couple places in the parser, and expressions in general.
2011-03-27 21:01:58 +02:00
# include <assert.h>
Introduce shell of vhdlpp program. Create the makefiles and configuration scripts to hold together the vhdlpp front-end program. Create a shell main.
2010-12-13 05:02:18 +01:00
Add file/line information to entities and ports Include the compiler infrastructure to vhdlpp for collecting the file and line information and attaching it to entities and ports. Make the parser store the file name during parse. Create a libmisc library where I can put source files that are used by multiple programs within the source tree.
2011-01-06 18:27:30 +01:00
inline void FILE_NAME(LineInfo*tmp, const struct yyltype&where)
{
tmp->set_lineno(where.first_line);
tmp->set_file(filename_strings.make(where.text));
}
Support vhdl identifier lists in interface elements. syntax like this is ok: name1, name1, name3 : in bit; name4 : out bit; and so on.
2011-03-19 19:15:47 +01:00
/* Recent version of bison expect that the user supply a
YYLLOC_DEFAULT macro that makes up a yylloc value from existing
values. I need to supply an explicit version to account for the
text field, that otherwise won't be copied. */
# define YYLLOC_DEFAULT(Current, Rhs, N) do { \
(Current).first_line = (Rhs)[1].first_line; \
(Current).first_column = (Rhs)[1].first_column; \
(Current).last_line = (Rhs)[N].last_line; \
(Current).last_column = (Rhs)[N].last_column; \
(Current).text = (Rhs)[1].text; } while (0)
Introduce shell of vhdlpp program. Create the makefiles and configuration scripts to hold together the vhdlpp front-end program. Create a shell main.
2010-12-13 05:02:18 +01:00
static void yyerror(const char*msg);
Flesh out VHDL parser engine. Add enough rules to parse a simple VHDL program: Parse library and use clauses, Parse entity declarations, and Parse architecture bodies. Add some parser infrastructure: Handle syntax errors with useful error messages, Include file name and line numbers in parse errors, Add some parser debug aids.
2010-12-15 06:36:47 +01:00
int parse_errors = 0;
Add parser support for architecture declaratives and component instantiations Also include support for "sorry" messages so that we have a place to hang unsupported but properly parsed constructs. In the process of doing this, I also encountered and add parser support for indexed names. And matching "sorry" messages.
2011-03-20 02:26:43 +01:00
int parse_sorrys = 0;
Parse component declarations / parse signal declarations. These go into the architecture/block of their scope and will be used by component instantiations to make sure the bindings are correct and complete. Also handle signal declarations. The elaborator will use these to generate module local variables that are used by the architecture.
2011-03-22 17:16:20 +01:00
/*
* This map accumulates signals that are matched in the declarations
* section of a block. When the declarations are over, these are
* transferred to a map for the block proper.
*/
static map<perm_string, Signal*> block_signals;
/*
* This map accumulates component declarations.
*/
static map<perm_string, ComponentBase*> block_components;
Introduce shell of vhdlpp program. Create the makefiles and configuration scripts to hold together the vhdlpp front-end program. Create a shell main.
2010-12-13 05:02:18 +01:00
%}
Introductory changes for numbers handling
2011-01-31 18:25:29 +01:00
Parse create entities with ports Create entity objects from entity declarations in the source, and populate them with ports.
2011-01-03 07:30:09 +01:00
%union {
port_mode_t port_mode;
Stub support for library import. This provides a stub implementation for library import. Use this stub to make up a slightly more functional ieee library implementation.
2011-02-19 20:39:00 +01:00
Parse create entities with ports Create entity objects from entity declarations in the source, and populate them with ports.
2011-01-03 07:30:09 +01:00
char*text;
Merge branch 'master' into work4 Conflicts: vhdlpp/lexor.lex vhdlpp/parse.y vhdlpp/vhdlint.cc
2011-03-15 01:34:57 +01:00
Stub support for library import. This provides a stub implementation for library import. Use this stub to make up a slightly more functional ieee library implementation.
2011-02-19 20:39:00 +01:00
std::list<perm_string>* name_list;
Add use clause parsing Up till now only "global" use clauses were parsed and as a result libraries were loaded. Since use clauses can appear not only in global context, parsing of non-global clauses has been introduced and selected names are now handled (like name1.name2.name3).
2011-03-29 10:33:09 +02:00
std::vector<perm_string>* compound_name;
std::list<std::vector<perm_string>* >* compound_name_list;
Add parse decorations for expressions. Elaboration will need a parse tree for expressions. Create one for the expression types that are currently supported. Also add rules and the keywords for all the remaining binary logical operators.
2011-01-30 02:27:30 +01:00
Elaborate array subtypes of ports. There are internal types that are unbounded arrays. Allow subtype syntax that creates bounded versions of these arrays, and elaborate them as vectors at port boundaries. This makes some interesting types work out. Also start replacing vhdlint and vhdlreal with int64_t and double, which are reasonable values for universal_integer and universal_real from the VHDL standard. I need these cleaned up because the ints in particular are used for the literal expressions in array index constraints.
2011-02-14 04:01:21 +01:00
bool flag;
int64_t uni_integer;
double uni_real;
Add use clause parsing Up till now only "global" use clauses were parsed and as a result libraries were loaded. Since use clauses can appear not only in global context, parsing of non-global clauses has been introduced and selected names are now handled (like name1.name2.name3).
2011-03-29 10:33:09 +02:00
Add parse decorations for expressions. Elaboration will need a parse tree for expressions. Create one for the expression types that are currently supported. Also add rules and the keywords for all the remaining binary logical operators.
2011-01-30 02:27:30 +01:00
Expression*expr;
std::list<Expression*>* expr_list;
Basic elaboration of vhdl component instantiations. This gets us as far as emiting a component instantiation. Very little error checking/elaboration is done, so there is room for improvement, but this is a working stub.
2011-04-01 03:50:48 +02:00
named_expr_t*named_expr;
std::list<named_expr_t*>*named_expr_list;
Add entity aspects to VHDL parsing Entity aspects are now recognized and parsed into corresponding objects. A new class (entity_aspect) has been added.
2011-03-31 15:19:42 +02:00
entity_aspect_t* entity_aspect;
Add basic instantiation list handling in VHDL A class for representing instantiation list has been added.
2011-03-31 17:02:44 +02:00
instant_list_t* instantiation_list;
Add component specification parsing A class for component specification has been added
2011-04-01 09:50:04 +02:00
std::pair<instant_list_t*, ExpName*>* component_specification;
Basic elaboration of vhdl component instantiations. This gets us as far as emiting a component instantiation. Very little error checking/elaboration is done, so there is room for improvement, but this is a working stub.
2011-04-01 03:50:48 +02:00
Do type mapping in the parser. In VHDL, types are declared before they are used, so it is possible to do type binding during parse. This makes the parser a little bit cleaner.
2011-02-14 01:37:10 +01:00
const VType* vtype;
Parse create entities with ports Create entity objects from entity declarations in the source, and populate them with ports.
2011-01-03 07:30:09 +01:00
std::list<InterfacePort*>* interface_list;
Annotate the parse of simple concurrent statements.
2011-01-27 05:38:20 +01:00
Architecture::Statement* arch_statement;
std::list<Architecture::Statement*>* arch_statement_list;
Parse create entities with ports Create entity objects from entity declarations in the source, and populate them with ports.
2011-01-03 07:30:09 +01:00
};
Introduce shell of vhdlpp program. Create the makefiles and configuration scripts to hold together the vhdlpp front-end program. Create a shell main.
2010-12-13 05:02:18 +01:00
/* The keywords are all tokens. */
%token K_abs K_access K_after K_alias K_all K_and K_architecture
%token K_array K_assert K_assume K_assume_guarantee K_attribute
%token K_begin K_block K_body K_buffer K_bus
%token K_case K_component K_configuration K_constant K_context K_cover
New keywords to lexer added and typos corrected
2011-01-27 15:13:38 +01:00
%token K_default K_disconnect K_downto
Introduce shell of vhdlpp program. Create the makefiles and configuration scripts to hold together the vhdlpp front-end program. Create a shell main.
2010-12-13 05:02:18 +01:00
%token K_else K_elsif K_end K_entity K_exit
%token K_fairness K_file K_for K_force K_function
%token K_generate K_generic K_group K_guarded
New keywords to lexer added and typos corrected
2011-01-27 15:13:38 +01:00
%token K_if K_impure K_in K_inertial K_inout K_is
Introduce shell of vhdlpp program. Create the makefiles and configuration scripts to hold together the vhdlpp front-end program. Create a shell main.
2010-12-13 05:02:18 +01:00
%token K_label K_library K_linkage K_literal K_loop
%token K_map K_mod
%token K_nand K_new K_next K_nor K_not K_null
%token K_of K_on K_open K_or K_others K_out
%token K_package K_parameter K_port K_postponed K_procedure K_process
%token K_property K_protected K_pure
%token K_range K_record K_register K_reject K_release K_rem K_report
%token K_restrict K_restrict_guarantee K_return K_rol K_ror
New keywords to lexer added and typos corrected
2011-01-27 15:13:38 +01:00
%token K_select K_sequence K_severity K_signal K_shared
Minor changes to VHDL lexor
2011-01-28 10:40:38 +01:00
%token K_sla K_sll K_sra K_srl K_strong K_subtype
Introduce shell of vhdlpp program. Create the makefiles and configuration scripts to hold together the vhdlpp front-end program. Create a shell main.
2010-12-13 05:02:18 +01:00
%token K_then K_to K_transport K_type
%token K_unaffected K_units K_until K_use
%token K_variable K_vmode K_vprop K_vunit
%token K_wait K_when K_while K_with
%token K_xnor K_xor
/* Identifiers that are not keywords are identifiers. */
Parse create entities with ports Create entity objects from entity declarations in the source, and populate them with ports.
2011-01-03 07:30:09 +01:00
%token <text> IDENTIFIER
Elaborate array subtypes of ports. There are internal types that are unbounded arrays. Allow subtype syntax that creates bounded versions of these arrays, and elaborate them as vectors at port boundaries. This makes some interesting types work out. Also start replacing vhdlint and vhdlreal with int64_t and double, which are reasonable values for universal_integer and universal_real from the VHDL standard. I need these cleaned up because the ints in particular are used for the literal expressions in array index constraints.
2011-02-14 04:01:21 +01:00
%token <uni_integer> INT_LITERAL
%token <uni_real> REAL_LITERAL
Introductory changes for numbers handling
2011-01-31 18:25:29 +01:00
%token <text> STRING_LITERAL CHARACTER_LITERAL
Flesh out VHDL parser engine. Add enough rules to parse a simple VHDL program: Parse library and use clauses, Parse entity declarations, and Parse architecture bodies. Add some parser infrastructure: Handle syntax errors with useful error messages, Include file name and line numbers in parse errors, Add some parser debug aids.
2010-12-15 06:36:47 +01:00
/* compound symbols */
Introductory changes for numbers handling
2011-01-31 18:25:29 +01:00
%token LEQ GEQ VASSIGN NE BOX EXP ARROW DLT DGT
Flesh out VHDL parser engine. Add enough rules to parse a simple VHDL program: Parse library and use clauses, Parse entity declarations, and Parse architecture bodies. Add some parser infrastructure: Handle syntax errors with useful error messages, Include file name and line numbers in parse errors, Add some parser debug aids.
2010-12-15 06:36:47 +01:00
Parse create entities with ports Create entity objects from entity declarations in the source, and populate them with ports.
2011-01-03 07:30:09 +01:00
/* The rules may have types. */
Annotate the parse of simple concurrent statements.
2011-01-27 05:38:20 +01:00
Elaborate array subtypes of ports. There are internal types that are unbounded arrays. Allow subtype syntax that creates bounded versions of these arrays, and elaborate them as vectors at port boundaries. This makes some interesting types work out. Also start replacing vhdlint and vhdlreal with int64_t and double, which are reasonable values for universal_integer and universal_real from the VHDL standard. I need these cleaned up because the ints in particular are used for the literal expressions in array index constraints.
2011-02-14 04:01:21 +01:00
%type <flag> direction
Add parser support for architecture declaratives and component instantiations Also include support for "sorry" messages so that we have a place to hang unsupported but properly parsed constructs. In the process of doing this, I also encountered and add parser support for indexed names. And matching "sorry" messages.
2011-03-20 02:26:43 +01:00
%type <interface_list> interface_element interface_list entity_header
%type <interface_list> port_clause port_clause_opt
Parse create entities with ports Create entity objects from entity declarations in the source, and populate them with ports.
2011-01-03 07:30:09 +01:00
%type <port_mode> mode
Add basic instantiation list handling in VHDL A class for representing instantiation list has been added.
2011-03-31 17:02:44 +02:00
%type <entity_aspect> entity_aspect entity_aspect_opt binding_indication binding_indication_semicolon_opt
%type <instantiation_list> instantiation_list
Add component specification parsing A class for component specification has been added
2011-04-01 09:50:04 +02:00
%type <component_specification> component_specification
Add entity aspects to VHDL parsing Entity aspects are now recognized and parsed into corresponding objects. A new class (entity_aspect) has been added.
2011-03-31 15:19:42 +02:00
Add parser support for architecture declaratives and component instantiations Also include support for "sorry" messages so that we have a place to hang unsupported but properly parsed constructs. In the process of doing this, I also encountered and add parser support for indexed names. And matching "sorry" messages.
2011-03-20 02:26:43 +01:00
%type <arch_statement> concurrent_statement component_instantiation_statement concurrent_signal_assignment_statement
Annotate the parse of simple concurrent statements.
2011-01-27 05:38:20 +01:00
%type <arch_statement_list> architecture_statement_part
Add parser support for architecture declaratives and component instantiations Also include support for "sorry" messages so that we have a place to hang unsupported but properly parsed constructs. In the process of doing this, I also encountered and add parser support for indexed names. And matching "sorry" messages.
2011-03-20 02:26:43 +01:00
%type <expr> expression factor primary relation
%type <expr> expression_logical expression_logical_and expression_logical_or
%type <expr> expression_logical_xnor expression_logical_xor
Add more complete support for vhdl local signals. These signals are declared in the architecture and are local to the module. The Architecture already parsed and stored these signal declarations, but this patch adds the ability to actually emit these signals in the generated code. In the process of doing this, I had to regularize the elaboration and emit of VTypes, so that it can be used in multiple places, not just in entity headers (for ports). I also added support for bit selects of signals. This effected a couple places in the parser, and expressions in general.
2011-03-27 21:01:58 +02:00
%type <expr> name
Add parse decorations for expressions. Elaboration will need a parse tree for expressions. Create one for the expression types that are currently supported. Also add rules and the keywords for all the remaining binary logical operators.
2011-01-30 02:27:30 +01:00
%type <expr> shift_expression simple_expression term waveform_element
%type <expr_list> waveform waveform_elements
Architecture syntax allows for closing name.
2011-02-03 05:14:27 +01:00
Basic elaboration of vhdl component instantiations. This gets us as far as emiting a component instantiation. Very little error checking/elaboration is done, so there is room for improvement, but this is a working stub.
2011-04-01 03:50:48 +02:00
%type <named_expr> association_element
%type <named_expr_list> association_list port_map_aspect port_map_aspect_opt
Do type mapping in the parser. In VHDL, types are declared before they are used, so it is possible to do type binding during parse. This makes the parser a little bit cleaner.
2011-02-14 01:37:10 +01:00
%type <vtype> subtype_indication
Add use clause parsing Up till now only "global" use clauses were parsed and as a result libraries were loaded. Since use clauses can appear not only in global context, parsing of non-global clauses has been introduced and selected names are now handled (like name1.name2.name3).
2011-03-29 10:33:09 +02:00
%type <text> identifier_opt logical_name suffix
Support vhdl identifier lists in interface elements. syntax like this is ok: name1, name1, name3 : in bit; name4 : out bit; and so on.
2011-03-19 19:15:47 +01:00
%type <name_list> logical_name_list identifier_list
Add use clause parsing Up till now only "global" use clauses were parsed and as a result libraries were loaded. Since use clauses can appear not only in global context, parsing of non-global clauses has been introduced and selected names are now handled (like name1.name2.name3).
2011-03-29 10:33:09 +02:00
%type <compound_name> prefix selected_name
%type <compound_name_list> selected_names use_clause
Architecture syntax allows for closing name.
2011-02-03 05:14:27 +01:00
Introduce shell of vhdlpp program. Create the makefiles and configuration scripts to hold together the vhdlpp front-end program. Create a shell main.
2010-12-13 05:02:18 +01:00
%%
Flesh out VHDL parser engine. Add enough rules to parse a simple VHDL program: Parse library and use clauses, Parse entity declarations, and Parse architecture bodies. Add some parser infrastructure: Handle syntax errors with useful error messages, Include file name and line numbers in parse errors, Add some parser debug aids.
2010-12-15 06:36:47 +01:00
/* The design_file is the root for the VHDL parse. */
design_file : design_units ;
architecture_body
: K_architecture IDENTIFIER
K_of IDENTIFIER
Add parser support for architecture declaratives and component instantiations Also include support for "sorry" messages so that we have a place to hang unsupported but properly parsed constructs. In the process of doing this, I also encountered and add parser support for indexed names. And matching "sorry" messages.
2011-03-20 02:26:43 +01:00
K_is block_declarative_items_opt
Architecture syntax allows for closing name.
2011-02-03 05:14:27 +01:00
K_begin architecture_statement_part K_end K_architecture_opt identifier_opt ';'
Parse component declarations / parse signal declarations. These go into the architecture/block of their scope and will be used by component instantiations to make sure the bindings are correct and complete. Also handle signal declarations. The elaborator will use these to generate module local variables that are used by the architecture.
2011-03-22 17:16:20 +01:00
{ Architecture*tmp = new Architecture(lex_strings.make($2),
block_signals,
block_components, *$8);
Create an Architecture class and bind them to their entities.
2011-01-24 05:26:27 +01:00
FILE_NAME(tmp, @1);
bind_architecture_to_entity($4, tmp);
Add parser support for architecture declaratives and component instantiations Also include support for "sorry" messages so that we have a place to hang unsupported but properly parsed constructs. In the process of doing this, I also encountered and add parser support for indexed names. And matching "sorry" messages.
2011-03-20 02:26:43 +01:00
if ($11 && tmp->get_name() != $11)
Basic VHDL configuration parsing The bison grammar has been extended in order to parse configuration statements. Parsing remains very primitive but principal constructs can be now recognized.
2011-03-28 18:59:04 +02:00
errormsg(@2, "Architecture name doesn't match closing name.\n");
Create an Architecture class and bind them to their entities.
2011-01-24 05:26:27 +01:00
delete[]$2;
delete[]$4;
Add parser support for architecture declaratives and component instantiations Also include support for "sorry" messages so that we have a place to hang unsupported but properly parsed constructs. In the process of doing this, I also encountered and add parser support for indexed names. And matching "sorry" messages.
2011-03-20 02:26:43 +01:00
delete $8;
Parse component declarations / parse signal declarations. These go into the architecture/block of their scope and will be used by component instantiations to make sure the bindings are correct and complete. Also handle signal declarations. The elaborator will use these to generate module local variables that are used by the architecture.
2011-03-22 17:16:20 +01:00
block_signals.clear();
block_components.clear();
Add parser support for architecture declaratives and component instantiations Also include support for "sorry" messages so that we have a place to hang unsupported but properly parsed constructs. In the process of doing this, I also encountered and add parser support for indexed names. And matching "sorry" messages.
2011-03-20 02:26:43 +01:00
if ($11) delete[]$11;
Create an Architecture class and bind them to their entities.
2011-01-24 05:26:27 +01:00
}
Flesh out VHDL parser engine. Add enough rules to parse a simple VHDL program: Parse library and use clauses, Parse entity declarations, and Parse architecture bodies. Add some parser infrastructure: Handle syntax errors with useful error messages, Include file name and line numbers in parse errors, Add some parser debug aids.
2010-12-15 06:36:47 +01:00
| K_architecture IDENTIFIER
K_of IDENTIFIER
Add parser support for architecture declaratives and component instantiations Also include support for "sorry" messages so that we have a place to hang unsupported but properly parsed constructs. In the process of doing this, I also encountered and add parser support for indexed names. And matching "sorry" messages.
2011-03-20 02:26:43 +01:00
K_is block_declarative_items_opt
Support vhdl identifier lists in interface elements. syntax like this is ok: name1, name1, name3 : in bit; name4 : out bit; and so on.
2011-03-19 19:15:47 +01:00
K_begin error K_end K_architecture_opt identifier_opt ';'
Add parser support for architecture declaratives and component instantiations Also include support for "sorry" messages so that we have a place to hang unsupported but properly parsed constructs. In the process of doing this, I also encountered and add parser support for indexed names. And matching "sorry" messages.
2011-03-20 02:26:43 +01:00
{ errormsg(@8, "Errors in architecture statements.\n"); yyerrok; }
Flesh out VHDL parser engine. Add enough rules to parse a simple VHDL program: Parse library and use clauses, Parse entity declarations, and Parse architecture bodies. Add some parser infrastructure: Handle syntax errors with useful error messages, Include file name and line numbers in parse errors, Add some parser debug aids.
2010-12-15 06:36:47 +01:00
| K_architecture error ';'
Add parser support for architecture declaratives and component instantiations Also include support for "sorry" messages so that we have a place to hang unsupported but properly parsed constructs. In the process of doing this, I also encountered and add parser support for indexed names. And matching "sorry" messages.
2011-03-20 02:26:43 +01:00
{ errormsg(@2, "Errors in architecture body.\n"); yyerrok; }
Flesh out VHDL parser engine. Add enough rules to parse a simple VHDL program: Parse library and use clauses, Parse entity declarations, and Parse architecture bodies. Add some parser infrastructure: Handle syntax errors with useful error messages, Include file name and line numbers in parse errors, Add some parser debug aids.
2010-12-15 06:36:47 +01:00
;
Add parser support for architecture declaratives and component instantiations Also include support for "sorry" messages so that we have a place to hang unsupported but properly parsed constructs. In the process of doing this, I also encountered and add parser support for indexed names. And matching "sorry" messages.
2011-03-20 02:26:43 +01:00
/*
* The architecture_statement_part is a list of concurrent
* statements.
*/
Flesh out VHDL parser engine. Add enough rules to parse a simple VHDL program: Parse library and use clauses, Parse entity declarations, and Parse architecture bodies. Add some parser infrastructure: Handle syntax errors with useful error messages, Include file name and line numbers in parse errors, Add some parser debug aids.
2010-12-15 06:36:47 +01:00
architecture_statement_part
: architecture_statement_part concurrent_statement
Annotate the parse of simple concurrent statements.
2011-01-27 05:38:20 +01:00
{ std::list<Architecture::Statement*>*tmp = $1;
Support vhdl identifier lists in interface elements. syntax like this is ok: name1, name1, name3 : in bit; name4 : out bit; and so on.
2011-03-19 19:15:47 +01:00
if ($2) tmp->push_back($2);
Annotate the parse of simple concurrent statements.
2011-01-27 05:38:20 +01:00
$$ = tmp;
}
Flesh out VHDL parser engine. Add enough rules to parse a simple VHDL program: Parse library and use clauses, Parse entity declarations, and Parse architecture bodies. Add some parser infrastructure: Handle syntax errors with useful error messages, Include file name and line numbers in parse errors, Add some parser debug aids.
2010-12-15 06:36:47 +01:00
| concurrent_statement
Annotate the parse of simple concurrent statements.
2011-01-27 05:38:20 +01:00
{ std::list<Architecture::Statement*>*tmp = new std::list<Architecture::Statement*>;
Support vhdl identifier lists in interface elements. syntax like this is ok: name1, name1, name3 : in bit; name4 : out bit; and so on.
2011-03-19 19:15:47 +01:00
if ($1) tmp->push_back($1);
Annotate the parse of simple concurrent statements.
2011-01-27 05:38:20 +01:00
$$ = tmp;
}
Add parser support for architecture declaratives and component instantiations Also include support for "sorry" messages so that we have a place to hang unsupported but properly parsed constructs. In the process of doing this, I also encountered and add parser support for indexed names. And matching "sorry" messages.
2011-03-20 02:26:43 +01:00
| error ';'
{ $$ = 0;
errormsg(@1, "Syntax error in architecture statement.\n");
yyerrok;
}
;
association_element
Basic elaboration of vhdl component instantiations. This gets us as far as emiting a component instantiation. Very little error checking/elaboration is done, so there is room for improvement, but this is a working stub.
2011-04-01 03:50:48 +02:00
: IDENTIFIER ARROW name
{ named_expr_t*tmp = new named_expr_t(lex_strings.make($1), $3);
delete[]$1;
$$ = tmp;
}
Add parser support for architecture declaratives and component instantiations Also include support for "sorry" messages so that we have a place to hang unsupported but properly parsed constructs. In the process of doing this, I also encountered and add parser support for indexed names. And matching "sorry" messages.
2011-03-20 02:26:43 +01:00
;
association_list
: association_list ',' association_element
Basic elaboration of vhdl component instantiations. This gets us as far as emiting a component instantiation. Very little error checking/elaboration is done, so there is room for improvement, but this is a working stub.
2011-04-01 03:50:48 +02:00
{ std::list<named_expr_t*>*tmp = $1;
tmp->push_back($3);
$$ = tmp;
}
Add parser support for architecture declaratives and component instantiations Also include support for "sorry" messages so that we have a place to hang unsupported but properly parsed constructs. In the process of doing this, I also encountered and add parser support for indexed names. And matching "sorry" messages.
2011-03-20 02:26:43 +01:00
| association_element
Basic elaboration of vhdl component instantiations. This gets us as far as emiting a component instantiation. Very little error checking/elaboration is done, so there is room for improvement, but this is a working stub.
2011-04-01 03:50:48 +02:00
{ std::list<named_expr_t*>*tmp = new std::list<named_expr_t*>;
tmp->push_back($1);
$$ = tmp;
}
Add parser support for architecture declaratives and component instantiations Also include support for "sorry" messages so that we have a place to hang unsupported but properly parsed constructs. In the process of doing this, I also encountered and add parser support for indexed names. And matching "sorry" messages.
2011-03-20 02:26:43 +01:00
;
Basic VHDL configuration parsing The bison grammar has been extended in order to parse configuration statements. Parsing remains very primitive but principal constructs can be now recognized.
2011-03-28 18:59:04 +02:00
binding_indication
: K_use entity_aspect_opt
port_map_aspect_opt
generic_map_aspect_opt
Add basic instantiation list handling in VHDL A class for representing instantiation list has been added.
2011-03-31 17:02:44 +02:00
{ //TODO: do sth with generic map aspect
$$ = $2;
}
Basic VHDL configuration parsing The bison grammar has been extended in order to parse configuration statements. Parsing remains very primitive but principal constructs can be now recognized.
2011-03-28 18:59:04 +02:00
;
binding_indication_semicolon_opt
Add basic instantiation list handling in VHDL A class for representing instantiation list has been added.
2011-03-31 17:02:44 +02:00
: binding_indication ';' { $$ = $1; }
| { $$ = 0; }
Basic VHDL configuration parsing The bison grammar has been extended in order to parse configuration statements. Parsing remains very primitive but principal constructs can be now recognized.
2011-03-28 18:59:04 +02:00
;
block_configuration
: K_for IDENTIFIER
use_clauses_opt
configuration_items_opt
K_end K_for ';'
{ delete[] $2; }
;
block_configuration_opt
: block_configuration
|
;
Add parser support for architecture declaratives and component instantiations Also include support for "sorry" messages so that we have a place to hang unsupported but properly parsed constructs. In the process of doing this, I also encountered and add parser support for indexed names. And matching "sorry" messages.
2011-03-20 02:26:43 +01:00
block_declarative_item
: K_signal identifier_list ':' subtype_indication ';'
Parse component declarations / parse signal declarations. These go into the architecture/block of their scope and will be used by component instantiations to make sure the bindings are correct and complete. Also handle signal declarations. The elaborator will use these to generate module local variables that are used by the architecture.
2011-03-22 17:16:20 +01:00
{ /* Save the signal declaration in the block_signals map. */
for (std::list<perm_string>::iterator cur = $2->begin()
; cur != $2->end() ; ++cur) {
Signal*sig = new Signal(*cur, $4);
FILE_NAME(sig, @1);
block_signals[*cur] = sig;
}
delete $2;
}
Add parser support for architecture declaratives and component instantiations Also include support for "sorry" messages so that we have a place to hang unsupported but properly parsed constructs. In the process of doing this, I also encountered and add parser support for indexed names. And matching "sorry" messages.
2011-03-20 02:26:43 +01:00
| K_component IDENTIFIER K_is_opt
port_clause_opt
K_end K_component identifier_opt ';'
{ perm_string name = lex_strings.make($2);
Basic VHDL configuration parsing The bison grammar has been extended in order to parse configuration statements. Parsing remains very primitive but principal constructs can be now recognized.
2011-03-28 18:59:04 +02:00
if($7) {
if (name != $7)
errormsg(@7, "Identifier %s doesn't match component name %s.\n",
Add parser support for architecture declaratives and component instantiations Also include support for "sorry" messages so that we have a place to hang unsupported but properly parsed constructs. In the process of doing this, I also encountered and add parser support for indexed names. And matching "sorry" messages.
2011-03-20 02:26:43 +01:00
$7, name.str());
Basic VHDL configuration parsing The bison grammar has been extended in order to parse configuration statements. Parsing remains very primitive but principal constructs can be now recognized.
2011-03-28 18:59:04 +02:00
delete[] $7;
}
Add parser support for architecture declaratives and component instantiations Also include support for "sorry" messages so that we have a place to hang unsupported but properly parsed constructs. In the process of doing this, I also encountered and add parser support for indexed names. And matching "sorry" messages.
2011-03-20 02:26:43 +01:00
Parse component declarations / parse signal declarations. These go into the architecture/block of their scope and will be used by component instantiations to make sure the bindings are correct and complete. Also handle signal declarations. The elaborator will use these to generate module local variables that are used by the architecture.
2011-03-22 17:16:20 +01:00
ComponentBase*comp = new ComponentBase(name);
if ($4) comp->set_interface($4);
block_components[name] = comp;
Add parser support for architecture declaratives and component instantiations Also include support for "sorry" messages so that we have a place to hang unsupported but properly parsed constructs. In the process of doing this, I also encountered and add parser support for indexed names. And matching "sorry" messages.
2011-03-20 02:26:43 +01:00
delete[]$2;
}
/* Various error handling rules for block_declarative_item... */
| K_signal error ';'
{ errormsg(@2, "Syntax error declaring signals.\n"); yyerrok; }
| error ';'
{ errormsg(@1, "Syntax error in block declarations.\n"); yyerrok; }
| K_component IDENTIFIER K_is_opt error K_end K_component identifier_opt ';'
Basic VHDL configuration parsing The bison grammar has been extended in order to parse configuration statements. Parsing remains very primitive but principal constructs can be now recognized.
2011-03-28 18:59:04 +02:00
{ errormsg(@4, "Syntax error in component declaration.\n");
delete[] $2;
if($7) {
delete[] $7;
}
yyerrok; }
Add parser support for architecture declaratives and component instantiations Also include support for "sorry" messages so that we have a place to hang unsupported but properly parsed constructs. In the process of doing this, I also encountered and add parser support for indexed names. And matching "sorry" messages.
2011-03-20 02:26:43 +01:00
;
/*
* The block_declarative_items rule matches "{ block_declarative_item }"
* which is a synonym for "architecture_declarative_part" and
* "block_declarative_part".
*/
block_declarative_items
: block_declarative_items block_declarative_item
| block_declarative_item
;
block_declarative_items_opt
: block_declarative_items
|
;
Basic VHDL configuration parsing The bison grammar has been extended in order to parse configuration statements. Parsing remains very primitive but principal constructs can be now recognized.
2011-03-28 18:59:04 +02:00
component_configuration
: K_for component_specification
binding_indication_semicolon_opt
block_configuration_opt
K_end K_for ';'
Add component specification parsing A class for component specification has been added
2011-04-01 09:50:04 +02:00
| K_for component_specification error K_end K_for
{
errormsg(@1, "Error in component configuration statement.\n");
}
Basic VHDL configuration parsing The bison grammar has been extended in order to parse configuration statements. Parsing remains very primitive but principal constructs can be now recognized.
2011-03-28 18:59:04 +02:00
;
Add parser support for architecture declaratives and component instantiations Also include support for "sorry" messages so that we have a place to hang unsupported but properly parsed constructs. In the process of doing this, I also encountered and add parser support for indexed names. And matching "sorry" messages.
2011-03-20 02:26:43 +01:00
component_instantiation_statement
Basic elaboration of vhdl component instantiations. This gets us as far as emiting a component instantiation. Very little error checking/elaboration is done, so there is room for improvement, but this is a working stub.
2011-04-01 03:50:48 +02:00
: IDENTIFIER ':' K_component_opt IDENTIFIER port_map_aspect_opt ';'
{ perm_string iname = lex_strings.make($1);
perm_string cname = lex_strings.make($4);
ComponentInstantiation*tmp = new ComponentInstantiation(iname, cname, $5);
FILE_NAME(tmp, @1);
Add parser support for architecture declaratives and component instantiations Also include support for "sorry" messages so that we have a place to hang unsupported but properly parsed constructs. In the process of doing this, I also encountered and add parser support for indexed names. And matching "sorry" messages.
2011-03-20 02:26:43 +01:00
delete[]$1;
Basic elaboration of vhdl component instantiations. This gets us as far as emiting a component instantiation. Very little error checking/elaboration is done, so there is room for improvement, but this is a working stub.
2011-04-01 03:50:48 +02:00
delete[]$4;
$$ = tmp;
Add parser support for architecture declaratives and component instantiations Also include support for "sorry" messages so that we have a place to hang unsupported but properly parsed constructs. In the process of doing this, I also encountered and add parser support for indexed names. And matching "sorry" messages.
2011-03-20 02:26:43 +01:00
}
Basic elaboration of vhdl component instantiations. This gets us as far as emiting a component instantiation. Very little error checking/elaboration is done, so there is room for improvement, but this is a working stub.
2011-04-01 03:50:48 +02:00
| IDENTIFIER ':' K_component_opt IDENTIFIER error ';'
Add parser support for architecture declaratives and component instantiations Also include support for "sorry" messages so that we have a place to hang unsupported but properly parsed constructs. In the process of doing this, I also encountered and add parser support for indexed names. And matching "sorry" messages.
2011-03-20 02:26:43 +01:00
{ errormsg(@4, "Errors in component instantiation.\n");
delete[]$1;
Basic elaboration of vhdl component instantiations. This gets us as far as emiting a component instantiation. Very little error checking/elaboration is done, so there is room for improvement, but this is a working stub.
2011-04-01 03:50:48 +02:00
delete[]$4;
Add parser support for architecture declaratives and component instantiations Also include support for "sorry" messages so that we have a place to hang unsupported but properly parsed constructs. In the process of doing this, I also encountered and add parser support for indexed names. And matching "sorry" messages.
2011-03-20 02:26:43 +01:00
$$ = 0;
}
Flesh out VHDL parser engine. Add enough rules to parse a simple VHDL program: Parse library and use clauses, Parse entity declarations, and Parse architecture bodies. Add some parser infrastructure: Handle syntax errors with useful error messages, Include file name and line numbers in parse errors, Add some parser debug aids.
2010-12-15 06:36:47 +01:00
;
Basic VHDL configuration parsing The bison grammar has been extended in order to parse configuration statements. Parsing remains very primitive but principal constructs can be now recognized.
2011-03-28 18:59:04 +02:00
component_specification
Add component specification parsing A class for component specification has been added
2011-04-01 09:50:04 +02:00
: instantiation_list ':' name
{
ExpName* name = dynamic_cast<ExpName*>($3);
std::pair<instant_list_t*, ExpName*>* tmp = new std::pair<instant_list_t*, ExpName*>($1, name);
$$ = tmp;
Basic VHDL configuration parsing The bison grammar has been extended in order to parse configuration statements. Parsing remains very primitive but principal constructs can be now recognized.
2011-03-28 18:59:04 +02:00
}
;
Flesh out VHDL parser engine. Add enough rules to parse a simple VHDL program: Parse library and use clauses, Parse entity declarations, and Parse architecture bodies. Add some parser infrastructure: Handle syntax errors with useful error messages, Include file name and line numbers in parse errors, Add some parser debug aids.
2010-12-15 06:36:47 +01:00
concurrent_signal_assignment_statement
Add parser support for architecture declaratives and component instantiations Also include support for "sorry" messages so that we have a place to hang unsupported but properly parsed constructs. In the process of doing this, I also encountered and add parser support for indexed names. And matching "sorry" messages.
2011-03-20 02:26:43 +01:00
: name LEQ waveform ';'
Add more complete support for vhdl local signals. These signals are declared in the architecture and are local to the module. The Architecture already parsed and stored these signal declarations, but this patch adds the ability to actually emit these signals in the generated code. In the process of doing this, I had to regularize the elaboration and emit of VTypes, so that it can be used in multiple places, not just in entity headers (for ports). I also added support for bit selects of signals. This effected a couple places in the parser, and expressions in general.
2011-03-27 21:01:58 +02:00
{ ExpName*name = dynamic_cast<ExpName*> ($1);
assert(name);
SignalAssignment*tmp = new SignalAssignment(name, *$3);
Annotate the parse of simple concurrent statements.
2011-01-27 05:38:20 +01:00
FILE_NAME(tmp, @1);
$$ = tmp;
Add parse decorations for expressions. Elaboration will need a parse tree for expressions. Create one for the expression types that are currently supported. Also add rules and the keywords for all the remaining binary logical operators.
2011-01-30 02:27:30 +01:00
delete $3;
Annotate the parse of simple concurrent statements.
2011-01-27 05:38:20 +01:00
}
Add parser support for architecture declaratives and component instantiations Also include support for "sorry" messages so that we have a place to hang unsupported but properly parsed constructs. In the process of doing this, I also encountered and add parser support for indexed names. And matching "sorry" messages.
2011-03-20 02:26:43 +01:00
| name LEQ error ';'
Support vhdl identifier lists in interface elements. syntax like this is ok: name1, name1, name3 : in bit; name4 : out bit; and so on.
2011-03-19 19:15:47 +01:00
{ errormsg(@2, "Syntax error in signal assignment waveform.\n");
Add more complete support for vhdl local signals. These signals are declared in the architecture and are local to the module. The Architecture already parsed and stored these signal declarations, but this patch adds the ability to actually emit these signals in the generated code. In the process of doing this, I had to regularize the elaboration and emit of VTypes, so that it can be used in multiple places, not just in entity headers (for ports). I also added support for bit selects of signals. This effected a couple places in the parser, and expressions in general.
2011-03-27 21:01:58 +02:00
delete $1;
Support vhdl identifier lists in interface elements. syntax like this is ok: name1, name1, name3 : in bit; name4 : out bit; and so on.
2011-03-19 19:15:47 +01:00
$$ = 0;
yyerrok;
}
Flesh out VHDL parser engine. Add enough rules to parse a simple VHDL program: Parse library and use clauses, Parse entity declarations, and Parse architecture bodies. Add some parser infrastructure: Handle syntax errors with useful error messages, Include file name and line numbers in parse errors, Add some parser debug aids.
2010-12-15 06:36:47 +01:00
;
concurrent_statement
Add parser support for architecture declaratives and component instantiations Also include support for "sorry" messages so that we have a place to hang unsupported but properly parsed constructs. In the process of doing this, I also encountered and add parser support for indexed names. And matching "sorry" messages.
2011-03-20 02:26:43 +01:00
: component_instantiation_statement
| concurrent_signal_assignment_statement
Flesh out VHDL parser engine. Add enough rules to parse a simple VHDL program: Parse library and use clauses, Parse entity declarations, and Parse architecture bodies. Add some parser infrastructure: Handle syntax errors with useful error messages, Include file name and line numbers in parse errors, Add some parser debug aids.
2010-12-15 06:36:47 +01:00
;
Fix constructs sequence in bison file for VHDL
2011-03-31 15:22:55 +02:00
configuration_declaration
: K_configuration IDENTIFIER K_of IDENTIFIER K_is
configuration_declarative_part
block_configuration
K_end K_configuration_opt identifier_opt ';'
{
if(design_entities.find(lex_strings.make($4)) == design_entities.end())
errormsg(@4, "Couldn't find entity %s used in configuration declaration", $4);
//choose_architecture_for_entity();
sorrymsg(@1, "Configuration declaration is not yet supported.\n");
}
| K_configuration error K_end K_configuration_opt identifier_opt ';'
{ errormsg(@2, "Too many errors, giving up on configuration declaration.\n");
if($5) delete $5;
yyerrok;
}
;
Basic VHDL configuration parsing The bison grammar has been extended in order to parse configuration statements. Parsing remains very primitive but principal constructs can be now recognized.
2011-03-28 18:59:04 +02:00
//TODO: this list is only a sketch. It must be filled out later
configuration_declarative_item
: use_clause
;
configuration_declarative_items
: configuration_declarative_items configuration_declarative_item
| configuration_declarative_item
;
configuration_declarative_part
: configuration_declarative_items
|
;
configuration_item
: block_configuration
| component_configuration
;
configuration_items
: configuration_items configuration_item
| configuration_item
;
configuration_items_opt
: configuration_items
|
;
Flesh out VHDL parser engine. Add enough rules to parse a simple VHDL program: Parse library and use clauses, Parse entity declarations, and Parse architecture bodies. Add some parser infrastructure: Handle syntax errors with useful error messages, Include file name and line numbers in parse errors, Add some parser debug aids.
2010-12-15 06:36:47 +01:00
context_clause : context_items | ;
context_item
: library_clause
Add use clause parsing Up till now only "global" use clauses were parsed and as a result libraries were loaded. Since use clauses can appear not only in global context, parsing of non-global clauses has been introduced and selected names are now handled (like name1.name2.name3).
2011-03-29 10:33:09 +02:00
| use_clause_lib
Flesh out VHDL parser engine. Add enough rules to parse a simple VHDL program: Parse library and use clauses, Parse entity declarations, and Parse architecture bodies. Add some parser infrastructure: Handle syntax errors with useful error messages, Include file name and line numbers in parse errors, Add some parser debug aids.
2010-12-15 06:36:47 +01:00
;
context_items
: context_items context_item
| context_item
;
design_unit
: context_clause library_unit
| error { errormsg(@1, "Invalid design_unit\n"); }
;
design_units
Fix spacing problems. This patch fixes spacing problems in the source code, space/tab at the end of line and space before tab.
2011-03-03 05:23:02 +01:00
: design_units design_unit
Flesh out VHDL parser engine. Add enough rules to parse a simple VHDL program: Parse library and use clauses, Parse entity declarations, and Parse architecture bodies. Add some parser infrastructure: Handle syntax errors with useful error messages, Include file name and line numbers in parse errors, Add some parser debug aids.
2010-12-15 06:36:47 +01:00
| design_unit
;
Elaborate array subtypes of ports. There are internal types that are unbounded arrays. Allow subtype syntax that creates bounded versions of these arrays, and elaborate them as vectors at port boundaries. This makes some interesting types work out. Also start replacing vhdlint and vhdlreal with int64_t and double, which are reasonable values for universal_integer and universal_real from the VHDL standard. I need these cleaned up because the ints in particular are used for the literal expressions in array index constraints.
2011-02-14 04:01:21 +01:00
/* Indicate the direction as a flag, with "downto" being TRUE. */
direction : K_to { $$ = false; } | K_downto { $$ = true; } ;
Do type mapping in the parser. In VHDL, types are declared before they are used, so it is possible to do type binding during parse. This makes the parser a little bit cleaner.
2011-02-14 01:37:10 +01:00
Parse create entities with ports Create entity objects from entity declarations in the source, and populate them with ports.
2011-01-03 07:30:09 +01:00
/* As an entity is declared, add it to the map of design entities. */
Basic VHDL configuration parsing The bison grammar has been extended in order to parse configuration statements. Parsing remains very primitive but principal constructs can be now recognized.
2011-03-28 18:59:04 +02:00
entity_aspect
Add entity aspects to VHDL parsing Entity aspects are now recognized and parsed into corresponding objects. A new class (entity_aspect) has been added.
2011-03-31 15:19:42 +02:00
: K_entity name
{
ExpName* name = dynamic_cast<ExpName*>($2);
entity_aspect_t* tmp = new entity_aspect_t(entity_aspect_t::ENTITY, name);
$$ = tmp;
}
| K_configuration name
{
ExpName* name = dynamic_cast<ExpName*>($2);
entity_aspect_t* tmp = new entity_aspect_t(entity_aspect_t::CONFIGURATION, name);
$$ = tmp;
}
Basic VHDL configuration parsing The bison grammar has been extended in order to parse configuration statements. Parsing remains very primitive but principal constructs can be now recognized.
2011-03-28 18:59:04 +02:00
| K_open
Add entity aspects to VHDL parsing Entity aspects are now recognized and parsed into corresponding objects. A new class (entity_aspect) has been added.
2011-03-31 15:19:42 +02:00
{
entity_aspect_t* tmp = new entity_aspect_t(entity_aspect_t::OPEN, 0);
$$ = tmp;
}
Basic VHDL configuration parsing The bison grammar has been extended in order to parse configuration statements. Parsing remains very primitive but principal constructs can be now recognized.
2011-03-28 18:59:04 +02:00
;
entity_aspect_opt
Add entity aspects to VHDL parsing Entity aspects are now recognized and parsed into corresponding objects. A new class (entity_aspect) has been added.
2011-03-31 15:19:42 +02:00
: entity_aspect { $$ = $1; }
| { $$ = 0; }
Basic VHDL configuration parsing The bison grammar has been extended in order to parse configuration statements. Parsing remains very primitive but principal constructs can be now recognized.
2011-03-28 18:59:04 +02:00
;
Flesh out VHDL parser engine. Add enough rules to parse a simple VHDL program: Parse library and use clauses, Parse entity declarations, and Parse architecture bodies. Add some parser infrastructure: Handle syntax errors with useful error messages, Include file name and line numbers in parse errors, Add some parser debug aids.
2010-12-15 06:36:47 +01:00
entity_declaration
Simplify entity parsing (removed the duplicate code)
2011-03-23 16:17:18 +01:00
: K_entity IDENTIFIER K_is entity_header K_end K_entity_opt identifier_opt';'
Create an Architecture class and bind them to their entities.
2011-01-24 05:26:27 +01:00
{ Entity*tmp = new Entity(lex_strings.make($2));
Add file/line information to entities and ports Include the compiler infrastructure to vhdlpp for collecting the file and line information and attaching it to entities and ports. Make the parser store the file name during parse. Create a libmisc library where I can put source files that are used by multiple programs within the source tree.
2011-01-06 18:27:30 +01:00
FILE_NAME(tmp, @1);
Parse create entities with ports Create entity objects from entity declarations in the source, and populate them with ports.
2011-01-03 07:30:09 +01:00
// Transfer the ports
std::list<InterfacePort*>*ports = $4;
Clean up entity interface.
2011-02-03 04:59:20 +01:00
tmp->set_interface(ports);
Parse create entities with ports Create entity objects from entity declarations in the source, and populate them with ports.
2011-01-03 07:30:09 +01:00
delete ports;
// Save the entity in the entity map.
Create an Architecture class and bind them to their entities.
2011-01-24 05:26:27 +01:00
design_entities[tmp->get_name()] = tmp;
delete[]$2;
Simplify entity parsing (removed the duplicate code)
2011-03-23 16:17:18 +01:00
if($7) {
if(tmp->get_name() != $7) {
errormsg(@1, "Syntax error in entity clause. Closing name doesn't match.\n");
Basic VHDL configuration parsing The bison grammar has been extended in order to parse configuration statements. Parsing remains very primitive but principal constructs can be now recognized.
2011-03-28 18:59:04 +02:00
yyerrok;
Simplify entity parsing (removed the duplicate code)
2011-03-23 16:17:18 +01:00
}
delete $7;
}
Fix identation style.
2011-01-27 02:44:58 +01:00
}
Do type mapping in the parser. In VHDL, types are declared before they are used, so it is possible to do type binding during parse. This makes the parser a little bit cleaner.
2011-02-14 01:37:10 +01:00
| K_entity error K_end K_entity_opt identifier_opt ';'
{ errormsg(@1, "Too many errors, giving up on entity declaration.\n");
yyerrok;
if ($5) delete[]$5;
}
Flesh out VHDL parser engine. Add enough rules to parse a simple VHDL program: Parse library and use clauses, Parse entity declarations, and Parse architecture bodies. Add some parser infrastructure: Handle syntax errors with useful error messages, Include file name and line numbers in parse errors, Add some parser debug aids.
2010-12-15 06:36:47 +01:00
;
entity_header
: port_clause
Parse create entities with ports Create entity objects from entity declarations in the source, and populate them with ports.
2011-01-03 07:30:09 +01:00
{ $$ = $1; }
Flesh out VHDL parser engine. Add enough rules to parse a simple VHDL program: Parse library and use clauses, Parse entity declarations, and Parse architecture bodies. Add some parser infrastructure: Handle syntax errors with useful error messages, Include file name and line numbers in parse errors, Add some parser debug aids.
2010-12-15 06:36:47 +01:00
;
expression
: expression_logical
Add parse decorations for expressions. Elaboration will need a parse tree for expressions. Create one for the expression types that are currently supported. Also add rules and the keywords for all the remaining binary logical operators.
2011-01-30 02:27:30 +01:00
{ $$ = $1; }
Flesh out VHDL parser engine. Add enough rules to parse a simple VHDL program: Parse library and use clauses, Parse entity declarations, and Parse architecture bodies. Add some parser infrastructure: Handle syntax errors with useful error messages, Include file name and line numbers in parse errors, Add some parser debug aids.
2010-12-15 06:36:47 +01:00
;
Add parser support for architecture declaratives and component instantiations Also include support for "sorry" messages so that we have a place to hang unsupported but properly parsed constructs. In the process of doing this, I also encountered and add parser support for indexed names. And matching "sorry" messages.
2011-03-20 02:26:43 +01:00
/*
* The expression_logical matches the logical_expression from the
* standard. Note that this is a little more tricky then usual because
* of the strange VHDL rules for logical expressions. We have to
* account for things like this:
*
* <exp> and <exp> and <exp>...
*
* which is matched by the standard rule:
*
* logical_expression ::=
* ...
* relation { and relation }
*
* The {} is important, and implies that "and" can be strung together
* with other "and" operators without parentheses. This is true for
* "and", "or", "xor", and "xnor". The tricky part is that these
* cannot be mixed. For example, this is not OK:
*
* <exp> and <exp> or <exp>
*
* Also note that "nand" and "nor" can not be chained in this manner.
*/
Flesh out VHDL parser engine. Add enough rules to parse a simple VHDL program: Parse library and use clauses, Parse entity declarations, and Parse architecture bodies. Add some parser infrastructure: Handle syntax errors with useful error messages, Include file name and line numbers in parse errors, Add some parser debug aids.
2010-12-15 06:36:47 +01:00
expression_logical
Support for some arithmetic operators.
2011-02-20 02:47:30 +01:00
: relation { $$ = $1; }
Add parser support for architecture declaratives and component instantiations Also include support for "sorry" messages so that we have a place to hang unsupported but properly parsed constructs. In the process of doing this, I also encountered and add parser support for indexed names. And matching "sorry" messages.
2011-03-20 02:26:43 +01:00
| relation K_and expression_logical_and
Add parse decorations for expressions. Elaboration will need a parse tree for expressions. Create one for the expression types that are currently supported. Also add rules and the keywords for all the remaining binary logical operators.
2011-01-30 02:27:30 +01:00
{ ExpLogical*tmp = new ExpLogical(ExpLogical::AND, $1, $3);
FILE_NAME(tmp, @2);
$$ = tmp;
}
Add parser support for architecture declaratives and component instantiations Also include support for "sorry" messages so that we have a place to hang unsupported but properly parsed constructs. In the process of doing this, I also encountered and add parser support for indexed names. And matching "sorry" messages.
2011-03-20 02:26:43 +01:00
| relation K_or expression_logical_or
Add parse decorations for expressions. Elaboration will need a parse tree for expressions. Create one for the expression types that are currently supported. Also add rules and the keywords for all the remaining binary logical operators.
2011-01-30 02:27:30 +01:00
{ ExpLogical*tmp = new ExpLogical(ExpLogical::OR, $1, $3);
FILE_NAME(tmp, @2);
$$ = tmp;
}
Add parser support for architecture declaratives and component instantiations Also include support for "sorry" messages so that we have a place to hang unsupported but properly parsed constructs. In the process of doing this, I also encountered and add parser support for indexed names. And matching "sorry" messages.
2011-03-20 02:26:43 +01:00
| relation K_xor expression_logical_xor
Add parse decorations for expressions. Elaboration will need a parse tree for expressions. Create one for the expression types that are currently supported. Also add rules and the keywords for all the remaining binary logical operators.
2011-01-30 02:27:30 +01:00
{ ExpLogical*tmp = new ExpLogical(ExpLogical::XOR, $1, $3);
FILE_NAME(tmp, @2);
$$ = tmp;
}
| relation K_nand relation
{ ExpLogical*tmp = new ExpLogical(ExpLogical::NAND, $1, $3);
FILE_NAME(tmp, @2);
$$ = tmp;
}
| relation K_nor relation
{ ExpLogical*tmp = new ExpLogical(ExpLogical::NOR, $1, $3);
FILE_NAME(tmp, @2);
$$ = tmp;
}
Add parser support for architecture declaratives and component instantiations Also include support for "sorry" messages so that we have a place to hang unsupported but properly parsed constructs. In the process of doing this, I also encountered and add parser support for indexed names. And matching "sorry" messages.
2011-03-20 02:26:43 +01:00
| relation K_xnor expression_logical_xnor
{ ExpLogical*tmp = new ExpLogical(ExpLogical::XNOR, $1, $3);
FILE_NAME(tmp, @2);
$$ = tmp;
}
;
expression_logical_and
: relation
{ $$ = $1; }
| expression_logical_and K_and relation
{ ExpLogical*tmp = new ExpLogical(ExpLogical::AND, $1, $3);
FILE_NAME(tmp, @2);
$$ = tmp;
}
;
expression_logical_or
: relation
{ $$ = $1; }
| expression_logical_or K_or relation
{ ExpLogical*tmp = new ExpLogical(ExpLogical::OR, $1, $3);
FILE_NAME(tmp, @2);
$$ = tmp;
}
;
expression_logical_xnor
: relation
{ $$ = $1; }
| expression_logical_xnor K_xnor relation
Add parse decorations for expressions. Elaboration will need a parse tree for expressions. Create one for the expression types that are currently supported. Also add rules and the keywords for all the remaining binary logical operators.
2011-01-30 02:27:30 +01:00
{ ExpLogical*tmp = new ExpLogical(ExpLogical::XNOR, $1, $3);
FILE_NAME(tmp, @2);
$$ = tmp;
}
Flesh out VHDL parser engine. Add enough rules to parse a simple VHDL program: Parse library and use clauses, Parse entity declarations, and Parse architecture bodies. Add some parser infrastructure: Handle syntax errors with useful error messages, Include file name and line numbers in parse errors, Add some parser debug aids.
2010-12-15 06:36:47 +01:00
;
Add parser support for architecture declaratives and component instantiations Also include support for "sorry" messages so that we have a place to hang unsupported but properly parsed constructs. In the process of doing this, I also encountered and add parser support for indexed names. And matching "sorry" messages.
2011-03-20 02:26:43 +01:00
expression_logical_xor
: relation
{ $$ = $1; }
| expression_logical_xor K_xor relation
{ ExpLogical*tmp = new ExpLogical(ExpLogical::XOR, $1, $3);
FILE_NAME(tmp, @2);
$$ = tmp;
}
;
Support for some arithmetic operators.
2011-02-20 02:47:30 +01:00
factor
: primary
{ $$ = $1; }
| primary EXP primary
{ ExpArithmetic*tmp = new ExpArithmetic(ExpArithmetic::POW, $1, $3);
FILE_NAME(tmp, @2);
$$ = tmp;
}
Add support for unary abs and not operators. While I'm at it, do a little refactoring of the handling of binary expressions to reduce code duplication.
2011-02-21 02:03:46 +01:00
| K_abs primary
{ ExpUAbs*tmp = new ExpUAbs($2);
FILE_NAME(tmp, @1);
$$ = tmp;
}
| K_not primary
{ ExpUNot*tmp = new ExpUNot($2);
FILE_NAME(tmp, @1);
$$ = tmp;
}
Support for some arithmetic operators.
2011-02-20 02:47:30 +01:00
;
Basic VHDL configuration parsing The bison grammar has been extended in order to parse configuration statements. Parsing remains very primitive but principal constructs can be now recognized.
2011-03-28 18:59:04 +02:00
generic_map_aspect_opt
: generic_map_aspect
|
;
generic_map_aspect
: K_generic K_map '(' association_list ')'
;
Flesh out VHDL parser engine. Add enough rules to parse a simple VHDL program: Parse library and use clauses, Parse entity declarations, and Parse architecture bodies. Add some parser infrastructure: Handle syntax errors with useful error messages, Include file name and line numbers in parse errors, Add some parser debug aids.
2010-12-15 06:36:47 +01:00
Support vhdl identifier lists in interface elements. syntax like this is ok: name1, name1, name3 : in bit; name4 : out bit; and so on.
2011-03-19 19:15:47 +01:00
identifier_list
: identifier_list ',' IDENTIFIER
{ std::list<perm_string>* tmp = $1;
tmp->push_back(lex_strings.make($3));
delete[]$3;
$$ = tmp;
}
| IDENTIFIER
{ std::list<perm_string>*tmp = new std::list<perm_string>;
tmp->push_back(lex_strings.make($1));
delete[]$1;
$$ = tmp;
}
;
Architecture syntax allows for closing name.
2011-02-03 05:14:27 +01:00
identifier_opt : IDENTIFIER { $$ = $1; } | { $$ = 0; } ;
Basic VHDL configuration parsing The bison grammar has been extended in order to parse configuration statements. Parsing remains very primitive but principal constructs can be now recognized.
2011-03-28 18:59:04 +02:00
instantiation_list
: identifier_list
Add basic instantiation list handling in VHDL A class for representing instantiation list has been added.
2011-03-31 17:02:44 +02:00
{
instant_list_t* tmp = new instant_list_t(instant_list_t::NONE, $1);
$$ = tmp;
}
Basic VHDL configuration parsing The bison grammar has been extended in order to parse configuration statements. Parsing remains very primitive but principal constructs can be now recognized.
2011-03-28 18:59:04 +02:00
| K_others
Add basic instantiation list handling in VHDL A class for representing instantiation list has been added.
2011-03-31 17:02:44 +02:00
{
instant_list_t* tmp = new instant_list_t(instant_list_t::OTHERS, 0);
$$ = tmp;
}
Basic VHDL configuration parsing The bison grammar has been extended in order to parse configuration statements. Parsing remains very primitive but principal constructs can be now recognized.
2011-03-28 18:59:04 +02:00
| K_all
{
Add basic instantiation list handling in VHDL A class for representing instantiation list has been added.
2011-03-31 17:02:44 +02:00
instant_list_t* tmp = new instant_list_t(instant_list_t::ALL, 0);
$$ = tmp;
Basic VHDL configuration parsing The bison grammar has been extended in order to parse configuration statements. Parsing remains very primitive but principal constructs can be now recognized.
2011-03-28 18:59:04 +02:00
}
;
Flesh out VHDL parser engine. Add enough rules to parse a simple VHDL program: Parse library and use clauses, Parse entity declarations, and Parse architecture bodies. Add some parser infrastructure: Handle syntax errors with useful error messages, Include file name and line numbers in parse errors, Add some parser debug aids.
2010-12-15 06:36:47 +01:00
/* The interface_element is also an interface_declaration */
interface_element
Support vhdl identifier lists in interface elements. syntax like this is ok: name1, name1, name3 : in bit; name4 : out bit; and so on.
2011-03-19 19:15:47 +01:00
: identifier_list ':' mode subtype_indication
{ std::list<InterfacePort*>*tmp = new std::list<InterfacePort*>;
for (std::list<perm_string>::iterator cur = $1->begin()
; cur != $1->end() ; ++cur) {
InterfacePort*port = new InterfacePort;
FILE_NAME(port, @1);
port->mode = $3;
port->name = *(cur);
port->type = $4;
tmp->push_back(port);
}
delete $1;
Parse create entities with ports Create entity objects from entity declarations in the source, and populate them with ports.
2011-01-03 07:30:09 +01:00
$$ = tmp;
}
Flesh out VHDL parser engine. Add enough rules to parse a simple VHDL program: Parse library and use clauses, Parse entity declarations, and Parse architecture bodies. Add some parser infrastructure: Handle syntax errors with useful error messages, Include file name and line numbers in parse errors, Add some parser debug aids.
2010-12-15 06:36:47 +01:00
;
interface_list
: interface_list ';' interface_element
Save the type name if an InterfacePort object.
2011-01-06 17:12:55 +01:00
{ std::list<InterfacePort*>*tmp = $1;
Support vhdl identifier lists in interface elements. syntax like this is ok: name1, name1, name3 : in bit; name4 : out bit; and so on.
2011-03-19 19:15:47 +01:00
tmp->splice(tmp->end(), *$3);
delete $3;
Parse create entities with ports Create entity objects from entity declarations in the source, and populate them with ports.
2011-01-03 07:30:09 +01:00
$$ = tmp;
}
Flesh out VHDL parser engine. Add enough rules to parse a simple VHDL program: Parse library and use clauses, Parse entity declarations, and Parse architecture bodies. Add some parser infrastructure: Handle syntax errors with useful error messages, Include file name and line numbers in parse errors, Add some parser debug aids.
2010-12-15 06:36:47 +01:00
| interface_element
Support vhdl identifier lists in interface elements. syntax like this is ok: name1, name1, name3 : in bit; name4 : out bit; and so on.
2011-03-19 19:15:47 +01:00
{ std::list<InterfacePort*>*tmp = $1;
Parse create entities with ports Create entity objects from entity declarations in the source, and populate them with ports.
2011-01-03 07:30:09 +01:00
$$ = tmp;
}
Flesh out VHDL parser engine. Add enough rules to parse a simple VHDL program: Parse library and use clauses, Parse entity declarations, and Parse architecture bodies. Add some parser infrastructure: Handle syntax errors with useful error messages, Include file name and line numbers in parse errors, Add some parser debug aids.
2010-12-15 06:36:47 +01:00
;
library_clause
: K_library logical_name_list ';'
Stub support for library import. This provides a stub implementation for library import. Use this stub to make up a slightly more functional ieee library implementation.
2011-02-19 20:39:00 +01:00
{ library_import(@1, $2);
delete $2;
}
Flesh out VHDL parser engine. Add enough rules to parse a simple VHDL program: Parse library and use clauses, Parse entity declarations, and Parse architecture bodies. Add some parser infrastructure: Handle syntax errors with useful error messages, Include file name and line numbers in parse errors, Add some parser debug aids.
2010-12-15 06:36:47 +01:00
| K_library error ';'
{ errormsg(@1, "Syntax error in library clause.\n"); yyerrok; }
;
/* Collapse the primary_unit and secondary_unit of the library_unit
into this single set of rules. */
library_unit
Basic VHDL configuration parsing The bison grammar has been extended in order to parse configuration statements. Parsing remains very primitive but principal constructs can be now recognized.
2011-03-28 18:59:04 +02:00
: primary_unit
| secondary_unit
Flesh out VHDL parser engine. Add enough rules to parse a simple VHDL program: Parse library and use clauses, Parse entity declarations, and Parse architecture bodies. Add some parser infrastructure: Handle syntax errors with useful error messages, Include file name and line numbers in parse errors, Add some parser debug aids.
2010-12-15 06:36:47 +01:00
;
Stub support for library import. This provides a stub implementation for library import. Use this stub to make up a slightly more functional ieee library implementation.
2011-02-19 20:39:00 +01:00
logical_name : IDENTIFIER { $$ = $1; } ;
Flesh out VHDL parser engine. Add enough rules to parse a simple VHDL program: Parse library and use clauses, Parse entity declarations, and Parse architecture bodies. Add some parser infrastructure: Handle syntax errors with useful error messages, Include file name and line numbers in parse errors, Add some parser debug aids.
2010-12-15 06:36:47 +01:00
logical_name_list
: logical_name_list ',' logical_name
Stub support for library import. This provides a stub implementation for library import. Use this stub to make up a slightly more functional ieee library implementation.
2011-02-19 20:39:00 +01:00
{ std::list<perm_string>*tmp = $1;
tmp->push_back(lex_strings.make($3));
delete[]$3;
$$ = tmp;
}
Flesh out VHDL parser engine. Add enough rules to parse a simple VHDL program: Parse library and use clauses, Parse entity declarations, and Parse architecture bodies. Add some parser infrastructure: Handle syntax errors with useful error messages, Include file name and line numbers in parse errors, Add some parser debug aids.
2010-12-15 06:36:47 +01:00
| logical_name
Stub support for library import. This provides a stub implementation for library import. Use this stub to make up a slightly more functional ieee library implementation.
2011-02-19 20:39:00 +01:00
{ std::list<perm_string>*tmp = new std::list<perm_string>;
tmp->push_back(lex_strings.make($1));
delete[]$1;
$$ = tmp;
}
Flesh out VHDL parser engine. Add enough rules to parse a simple VHDL program: Parse library and use clauses, Parse entity declarations, and Parse architecture bodies. Add some parser infrastructure: Handle syntax errors with useful error messages, Include file name and line numbers in parse errors, Add some parser debug aids.
2010-12-15 06:36:47 +01:00
;
Parse create entities with ports Create entity objects from entity declarations in the source, and populate them with ports.
2011-01-03 07:30:09 +01:00
mode
: K_in { $$ = PORT_IN; }
| K_out { $$ = PORT_OUT; }
;
Flesh out VHDL parser engine. Add enough rules to parse a simple VHDL program: Parse library and use clauses, Parse entity declarations, and Parse architecture bodies. Add some parser infrastructure: Handle syntax errors with useful error messages, Include file name and line numbers in parse errors, Add some parser debug aids.
2010-12-15 06:36:47 +01:00
Add parser support for architecture declaratives and component instantiations Also include support for "sorry" messages so that we have a place to hang unsupported but properly parsed constructs. In the process of doing this, I also encountered and add parser support for indexed names. And matching "sorry" messages.
2011-03-20 02:26:43 +01:00
name
: IDENTIFIER
Add more complete support for vhdl local signals. These signals are declared in the architecture and are local to the module. The Architecture already parsed and stored these signal declarations, but this patch adds the ability to actually emit these signals in the generated code. In the process of doing this, I had to regularize the elaboration and emit of VTypes, so that it can be used in multiple places, not just in entity headers (for ports). I also added support for bit selects of signals. This effected a couple places in the parser, and expressions in general.
2011-03-27 21:01:58 +02:00
{ ExpName*tmp = new ExpName(lex_strings.make($1));
FILE_NAME(tmp, @1);
delete[]$1;
$$ = tmp;
}
Add parser support for architecture declaratives and component instantiations Also include support for "sorry" messages so that we have a place to hang unsupported but properly parsed constructs. In the process of doing this, I also encountered and add parser support for indexed names. And matching "sorry" messages.
2011-03-20 02:26:43 +01:00
| IDENTIFIER '(' expression ')'
Add more complete support for vhdl local signals. These signals are declared in the architecture and are local to the module. The Architecture already parsed and stored these signal declarations, but this patch adds the ability to actually emit these signals in the generated code. In the process of doing this, I had to regularize the elaboration and emit of VTypes, so that it can be used in multiple places, not just in entity headers (for ports). I also added support for bit selects of signals. This effected a couple places in the parser, and expressions in general.
2011-03-27 21:01:58 +02:00
{ ExpName*tmp = new ExpName(lex_strings.make($1), $3);
FILE_NAME(tmp, @1);
delete[]$1;
$$ = tmp;
Add parser support for architecture declaratives and component instantiations Also include support for "sorry" messages so that we have a place to hang unsupported but properly parsed constructs. In the process of doing this, I also encountered and add parser support for indexed names. And matching "sorry" messages.
2011-03-20 02:26:43 +01:00
}
;
Basic VHDL configuration parsing The bison grammar has been extended in order to parse configuration statements. Parsing remains very primitive but principal constructs can be now recognized.
2011-03-28 18:59:04 +02:00
package_declaration
: K_package IDENTIFIER K_is
package_declarative_part_opt
K_end K_package_opt identifier_opt ';'
{ sorrymsg(@4, "Package declaration not supported yet.\n");
if($7) {
if($2 != $7) {
errormsg(@1, "Syntax error in package clause. Closing name doesn't match.\n");
yyerrok;
}
delete $7;
}
delete $2;
}
| K_package error K_end K_package_opt identifier_opt ';'
{ errormsg(@2, "Syntax error in package clause.\n");
yyerrok;
}
;
/* TODO: this list must be extended in the future
presently it is only a sketch */
package_body_declarative_item
: use_clause
;
package_body_declarative_items
: package_body_declarative_items package_body_declarative_item
| package_body_declarative_item
;
package_body_declarative_part_opt
: package_body_declarative_items
|
;
/* TODO: this list is only a sketch
it must be extended in the future */
package_declarative_item
: use_clause
;
package_declarative_items
: package_declarative_items package_declarative_item
| package_declarative_item
;
package_declarative_part_opt
: package_declarative_items
|
;
package_body
: K_package K_body IDENTIFIER K_is
package_body_declarative_part_opt
K_end K_package_opt identifier_opt ';'
{
delete[] $3;
if($8) delete[] $8;
}
;
Parse create entities with ports Create entity objects from entity declarations in the source, and populate them with ports.
2011-01-03 07:30:09 +01:00
port_clause
: K_port '(' interface_list ')' ';'
{ $$ = $3; }
Do type mapping in the parser. In VHDL, types are declared before they are used, so it is possible to do type binding during parse. This makes the parser a little bit cleaner.
2011-02-14 01:37:10 +01:00
| K_port '(' error ')' ';'
Basic VHDL configuration parsing The bison grammar has been extended in order to parse configuration statements. Parsing remains very primitive but principal constructs can be now recognized.
2011-03-28 18:59:04 +02:00
{ errormsg(@1, "Syntax error in port list.\n");
Do type mapping in the parser. In VHDL, types are declared before they are used, so it is possible to do type binding during parse. This makes the parser a little bit cleaner.
2011-02-14 01:37:10 +01:00
yyerrok;
$$ = 0;
}
Parse create entities with ports Create entity objects from entity declarations in the source, and populate them with ports.
2011-01-03 07:30:09 +01:00
;
Flesh out VHDL parser engine. Add enough rules to parse a simple VHDL program: Parse library and use clauses, Parse entity declarations, and Parse architecture bodies. Add some parser infrastructure: Handle syntax errors with useful error messages, Include file name and line numbers in parse errors, Add some parser debug aids.
2010-12-15 06:36:47 +01:00
Add parser support for architecture declaratives and component instantiations Also include support for "sorry" messages so that we have a place to hang unsupported but properly parsed constructs. In the process of doing this, I also encountered and add parser support for indexed names. And matching "sorry" messages.
2011-03-20 02:26:43 +01:00
port_clause_opt : port_clause {$$ = $1;} | {$$ = 0;} ;
port_map_aspect
: K_port K_map '(' association_list ')'
Basic elaboration of vhdl component instantiations. This gets us as far as emiting a component instantiation. Very little error checking/elaboration is done, so there is room for improvement, but this is a working stub.
2011-04-01 03:50:48 +02:00
{ $$ = $4; }
Add parser support for architecture declaratives and component instantiations Also include support for "sorry" messages so that we have a place to hang unsupported but properly parsed constructs. In the process of doing this, I also encountered and add parser support for indexed names. And matching "sorry" messages.
2011-03-20 02:26:43 +01:00
;
port_map_aspect_opt
Basic elaboration of vhdl component instantiations. This gets us as far as emiting a component instantiation. Very little error checking/elaboration is done, so there is room for improvement, but this is a working stub.
2011-04-01 03:50:48 +02:00
: port_map_aspect { $$ = $1; }
| { $$ = 0; }
Add parser support for architecture declaratives and component instantiations Also include support for "sorry" messages so that we have a place to hang unsupported but properly parsed constructs. In the process of doing this, I also encountered and add parser support for indexed names. And matching "sorry" messages.
2011-03-20 02:26:43 +01:00
;
Add use clause parsing Up till now only "global" use clauses were parsed and as a result libraries were loaded. Since use clauses can appear not only in global context, parsing of non-global clauses has been introduced and selected names are now handled (like name1.name2.name3).
2011-03-29 10:33:09 +02:00
prefix
: IDENTIFIER
{
std::vector<perm_string>* tmp = new std::vector<perm_string>();
tmp->push_back(lex_strings.make($1));
delete[] $1;
$$ = tmp;
}
| STRING_LITERAL
{
std::vector<perm_string>* tmp = new std::vector<perm_string>();
tmp->push_back(lex_strings.make($1));
delete[] $1;
$$ = tmp;
}
| selected_name
{
$$ = $1;
}
;
Flesh out VHDL parser engine. Add enough rules to parse a simple VHDL program: Parse library and use clauses, Parse entity declarations, and Parse architecture bodies. Add some parser infrastructure: Handle syntax errors with useful error messages, Include file name and line numbers in parse errors, Add some parser debug aids.
2010-12-15 06:36:47 +01:00
primary
Add parser support for architecture declaratives and component instantiations Also include support for "sorry" messages so that we have a place to hang unsupported but properly parsed constructs. In the process of doing this, I also encountered and add parser support for indexed names. And matching "sorry" messages.
2011-03-20 02:26:43 +01:00
: name
Add more complete support for vhdl local signals. These signals are declared in the architecture and are local to the module. The Architecture already parsed and stored these signal declarations, but this patch adds the ability to actually emit these signals in the generated code. In the process of doing this, I had to regularize the elaboration and emit of VTypes, so that it can be used in multiple places, not just in entity headers (for ports). I also added support for bit selects of signals. This effected a couple places in the parser, and expressions in general.
2011-03-27 21:01:58 +02:00
{ $$ = $1; }
Elaborate array subtypes of ports. There are internal types that are unbounded arrays. Allow subtype syntax that creates bounded versions of these arrays, and elaborate them as vectors at port boundaries. This makes some interesting types work out. Also start replacing vhdlint and vhdlreal with int64_t and double, which are reasonable values for universal_integer and universal_real from the VHDL standard. I need these cleaned up because the ints in particular are used for the literal expressions in array index constraints.
2011-02-14 04:01:21 +01:00
| INT_LITERAL
{ ExpInteger*tmp = new ExpInteger($1);
FILE_NAME(tmp, @1);
$$ = tmp;
}
Add support for unary abs and not operators. While I'm at it, do a little refactoring of the handling of binary expressions to reduce code duplication.
2011-02-21 02:03:46 +01:00
| '(' expression ')'
{ $$ = $2; }
Flesh out VHDL parser engine. Add enough rules to parse a simple VHDL program: Parse library and use clauses, Parse entity declarations, and Parse architecture bodies. Add some parser infrastructure: Handle syntax errors with useful error messages, Include file name and line numbers in parse errors, Add some parser debug aids.
2010-12-15 06:36:47 +01:00
;
Basic VHDL configuration parsing The bison grammar has been extended in order to parse configuration statements. Parsing remains very primitive but principal constructs can be now recognized.
2011-03-28 18:59:04 +02:00
primary_unit
: entity_declaration
| configuration_declaration
| package_declaration
;
Add parse decorations for expressions. Elaboration will need a parse tree for expressions. Create one for the expression types that are currently supported. Also add rules and the keywords for all the remaining binary logical operators.
2011-01-30 02:27:30 +01:00
relation : shift_expression { $$ = $1; } ;
Flesh out VHDL parser engine. Add enough rules to parse a simple VHDL program: Parse library and use clauses, Parse entity declarations, and Parse architecture bodies. Add some parser infrastructure: Handle syntax errors with useful error messages, Include file name and line numbers in parse errors, Add some parser debug aids.
2010-12-15 06:36:47 +01:00
Basic VHDL configuration parsing The bison grammar has been extended in order to parse configuration statements. Parsing remains very primitive but principal constructs can be now recognized.
2011-03-28 18:59:04 +02:00
secondary_unit
: architecture_body
| package_body
;
Add use clause parsing Up till now only "global" use clauses were parsed and as a result libraries were loaded. Since use clauses can appear not only in global context, parsing of non-global clauses has been introduced and selected names are now handled (like name1.name2.name3).
2011-03-29 10:33:09 +02:00
selected_name
: prefix '.' suffix
{
std::vector<perm_string>* tmp = $1;
tmp->push_back(lex_strings.make($3));
delete[] $3;
$$ = tmp;
}
;
selected_names
: selected_names ',' selected_name
{
std::list<std::vector<perm_string>* >* tmp = $1;
tmp->push_back($3);
$$ = tmp;
}
| selected_name
{
std::list<std::vector<perm_string>* >* tmp = new std::list<std::vector<perm_string>* >();
tmp->push_back($1);
$$ = tmp;
}
;
Stub support for "use" directives. Implement the parser infrastructure for handling library use clauses, and use that to handle specific packages of the ieee library. Make the numeric types come from the numeric_* packages instead of being built in.
2011-02-19 22:08:26 +01:00
/* The *_use variant of selected_name is used by the "use"
clause. It is syntactically identical to other selected_name
rules, but is a convenient place to attach use_clause actions. */
selected_name_use
Flesh out VHDL parser engine. Add enough rules to parse a simple VHDL program: Parse library and use clauses, Parse entity declarations, and Parse architecture bodies. Add some parser infrastructure: Handle syntax errors with useful error messages, Include file name and line numbers in parse errors, Add some parser debug aids.
2010-12-15 06:36:47 +01:00
: IDENTIFIER '.' K_all
Stub support for "use" directives. Implement the parser infrastructure for handling library use clauses, and use that to handle specific packages of the ieee library. Make the numeric types come from the numeric_* packages instead of being built in.
2011-02-19 22:08:26 +01:00
{ library_use(@1, 0, $1, 0);
delete[]$1;
}
Flesh out VHDL parser engine. Add enough rules to parse a simple VHDL program: Parse library and use clauses, Parse entity declarations, and Parse architecture bodies. Add some parser infrastructure: Handle syntax errors with useful error messages, Include file name and line numbers in parse errors, Add some parser debug aids.
2010-12-15 06:36:47 +01:00
| IDENTIFIER '.' IDENTIFIER '.' K_all
Stub support for "use" directives. Implement the parser infrastructure for handling library use clauses, and use that to handle specific packages of the ieee library. Make the numeric types come from the numeric_* packages instead of being built in.
2011-02-19 22:08:26 +01:00
{ library_use(@1, $1, $3, 0);
delete[]$1;
delete[]$3;
}
Flesh out VHDL parser engine. Add enough rules to parse a simple VHDL program: Parse library and use clauses, Parse entity declarations, and Parse architecture bodies. Add some parser infrastructure: Handle syntax errors with useful error messages, Include file name and line numbers in parse errors, Add some parser debug aids.
2010-12-15 06:36:47 +01:00
;
Stub support for "use" directives. Implement the parser infrastructure for handling library use clauses, and use that to handle specific packages of the ieee library. Make the numeric types come from the numeric_* packages instead of being built in.
2011-02-19 22:08:26 +01:00
selected_names_use
: selected_names_use ',' selected_name_use
| selected_name_use
Flesh out VHDL parser engine. Add enough rules to parse a simple VHDL program: Parse library and use clauses, Parse entity declarations, and Parse architecture bodies. Add some parser infrastructure: Handle syntax errors with useful error messages, Include file name and line numbers in parse errors, Add some parser debug aids.
2010-12-15 06:36:47 +01:00
;
Add parse decorations for expressions. Elaboration will need a parse tree for expressions. Create one for the expression types that are currently supported. Also add rules and the keywords for all the remaining binary logical operators.
2011-01-30 02:27:30 +01:00
shift_expression : simple_expression { $$ = $1; } ;
Flesh out VHDL parser engine. Add enough rules to parse a simple VHDL program: Parse library and use clauses, Parse entity declarations, and Parse architecture bodies. Add some parser infrastructure: Handle syntax errors with useful error messages, Include file name and line numbers in parse errors, Add some parser debug aids.
2010-12-15 06:36:47 +01:00
Support for some arithmetic operators.
2011-02-20 02:47:30 +01:00
simple_expression
: term
{ $$ = $1; }
| term '+' term
{ ExpArithmetic*tmp = new ExpArithmetic(ExpArithmetic::PLUS, $1, $3);
FILE_NAME(tmp, @2);
$$ = tmp;
}
| term '-' term
{ ExpArithmetic*tmp = new ExpArithmetic(ExpArithmetic::MINUS, $1, $3);
FILE_NAME(tmp, @2);
$$ = tmp;
}
;
Flesh out VHDL parser engine. Add enough rules to parse a simple VHDL program: Parse library and use clauses, Parse entity declarations, and Parse architecture bodies. Add some parser infrastructure: Handle syntax errors with useful error messages, Include file name and line numbers in parse errors, Add some parser debug aids.
2010-12-15 06:36:47 +01:00
Do type mapping in the parser. In VHDL, types are declared before they are used, so it is possible to do type binding during parse. This makes the parser a little bit cleaner.
2011-02-14 01:37:10 +01:00
subtype_indication
: IDENTIFIER
{ const VType*tmp = global_types[lex_strings.make($1)];
delete[]$1;
$$ = tmp;
}
Elaborate array subtypes of ports. There are internal types that are unbounded arrays. Allow subtype syntax that creates bounded versions of these arrays, and elaborate them as vectors at port boundaries. This makes some interesting types work out. Also start replacing vhdlint and vhdlreal with int64_t and double, which are reasonable values for universal_integer and universal_real from the VHDL standard. I need these cleaned up because the ints in particular are used for the literal expressions in array index constraints.
2011-02-14 04:01:21 +01:00
| IDENTIFIER '(' simple_expression direction simple_expression ')'
{ const VType*tmp = calculate_subtype($1, $3, $4, $5);
Do type mapping in the parser. In VHDL, types are declared before they are used, so it is possible to do type binding during parse. This makes the parser a little bit cleaner.
2011-02-14 01:37:10 +01:00
delete[]$1;
$$ = tmp;
}
;
Add use clause parsing Up till now only "global" use clauses were parsed and as a result libraries were loaded. Since use clauses can appear not only in global context, parsing of non-global clauses has been introduced and selected names are now handled (like name1.name2.name3).
2011-03-29 10:33:09 +02:00
suffix
: IDENTIFIER
{
$$ = $1;
}
| CHARACTER_LITERAL
{
$$ = $1;
}
| K_all
{
//do not have now better idea than using char constant
$$ = strcpy(new char[strlen("all"+1)], "all");
}
;
Support for some arithmetic operators.
2011-02-20 02:47:30 +01:00
term
: factor
{ $$ = $1; }
| factor '*' factor
{ ExpArithmetic*tmp = new ExpArithmetic(ExpArithmetic::MULT, $1, $3);
FILE_NAME(tmp, @2);
$$ = tmp;
}
| factor '/' factor
{ ExpArithmetic*tmp = new ExpArithmetic(ExpArithmetic::DIV, $1, $3);
FILE_NAME(tmp, @2);
$$ = tmp;
}
| factor K_mod factor
{ ExpArithmetic*tmp = new ExpArithmetic(ExpArithmetic::MOD, $1, $3);
FILE_NAME(tmp, @2);
$$ = tmp;
}
| factor K_rem factor
{ ExpArithmetic*tmp = new ExpArithmetic(ExpArithmetic::REM, $1, $3);
FILE_NAME(tmp, @2);
$$ = tmp;
}
;
Flesh out VHDL parser engine. Add enough rules to parse a simple VHDL program: Parse library and use clauses, Parse entity declarations, and Parse architecture bodies. Add some parser infrastructure: Handle syntax errors with useful error messages, Include file name and line numbers in parse errors, Add some parser debug aids.
2010-12-15 06:36:47 +01:00
use_clause
Add use clause parsing Up till now only "global" use clauses were parsed and as a result libraries were loaded. Since use clauses can appear not only in global context, parsing of non-global clauses has been introduced and selected names are now handled (like name1.name2.name3).
2011-03-29 10:33:09 +02:00
: K_use selected_names ';'
{
$$ = $2;
}
| K_use error ';'
{ errormsg(@1, "Syntax error in use clause.\n"); yyerrok; }
;
use_clause_lib
Stub support for "use" directives. Implement the parser infrastructure for handling library use clauses, and use that to handle specific packages of the ieee library. Make the numeric types come from the numeric_* packages instead of being built in.
2011-02-19 22:08:26 +01:00
: K_use selected_names_use ';'
Flesh out VHDL parser engine. Add enough rules to parse a simple VHDL program: Parse library and use clauses, Parse entity declarations, and Parse architecture bodies. Add some parser infrastructure: Handle syntax errors with useful error messages, Include file name and line numbers in parse errors, Add some parser debug aids.
2010-12-15 06:36:47 +01:00
| K_use error ';'
{ errormsg(@1, "Syntax error in use clause.\n"); yyerrok; }
;
Basic VHDL configuration parsing The bison grammar has been extended in order to parse configuration statements. Parsing remains very primitive but principal constructs can be now recognized.
2011-03-28 18:59:04 +02:00
use_clauses
: use_clauses use_clause
| use_clause
;
use_clauses_opt
: use_clauses
|
;
Flesh out VHDL parser engine. Add enough rules to parse a simple VHDL program: Parse library and use clauses, Parse entity declarations, and Parse architecture bodies. Add some parser infrastructure: Handle syntax errors with useful error messages, Include file name and line numbers in parse errors, Add some parser debug aids.
2010-12-15 06:36:47 +01:00
waveform
: waveform_elements
Add parse decorations for expressions. Elaboration will need a parse tree for expressions. Create one for the expression types that are currently supported. Also add rules and the keywords for all the remaining binary logical operators.
2011-01-30 02:27:30 +01:00
{ $$ = $1; }
Flesh out VHDL parser engine. Add enough rules to parse a simple VHDL program: Parse library and use clauses, Parse entity declarations, and Parse architecture bodies. Add some parser infrastructure: Handle syntax errors with useful error messages, Include file name and line numbers in parse errors, Add some parser debug aids.
2010-12-15 06:36:47 +01:00
| K_unaffected
Add parse decorations for expressions. Elaboration will need a parse tree for expressions. Create one for the expression types that are currently supported. Also add rules and the keywords for all the remaining binary logical operators.
2011-01-30 02:27:30 +01:00
{ $$ = 0; }
Flesh out VHDL parser engine. Add enough rules to parse a simple VHDL program: Parse library and use clauses, Parse entity declarations, and Parse architecture bodies. Add some parser infrastructure: Handle syntax errors with useful error messages, Include file name and line numbers in parse errors, Add some parser debug aids.
2010-12-15 06:36:47 +01:00
;
waveform_elements
: waveform_elements ',' waveform_element
Add parse decorations for expressions. Elaboration will need a parse tree for expressions. Create one for the expression types that are currently supported. Also add rules and the keywords for all the remaining binary logical operators.
2011-01-30 02:27:30 +01:00
{ std::list<Expression*>*tmp = $1;
tmp->push_back($3);
$$ = tmp;
}
Flesh out VHDL parser engine. Add enough rules to parse a simple VHDL program: Parse library and use clauses, Parse entity declarations, and Parse architecture bodies. Add some parser infrastructure: Handle syntax errors with useful error messages, Include file name and line numbers in parse errors, Add some parser debug aids.
2010-12-15 06:36:47 +01:00
| waveform_element
Add parse decorations for expressions. Elaboration will need a parse tree for expressions. Create one for the expression types that are currently supported. Also add rules and the keywords for all the remaining binary logical operators.
2011-01-30 02:27:30 +01:00
{ std::list<Expression*>*tmp = new std::list<Expression*>;
tmp->push_back($1);
$$ = tmp;
}
Flesh out VHDL parser engine. Add enough rules to parse a simple VHDL program: Parse library and use clauses, Parse entity declarations, and Parse architecture bodies. Add some parser infrastructure: Handle syntax errors with useful error messages, Include file name and line numbers in parse errors, Add some parser debug aids.
2010-12-15 06:36:47 +01:00
;
waveform_element
: expression
Add parse decorations for expressions. Elaboration will need a parse tree for expressions. Create one for the expression types that are currently supported. Also add rules and the keywords for all the remaining binary logical operators.
2011-01-30 02:27:30 +01:00
{ $$ = $1; }
Flesh out VHDL parser engine. Add enough rules to parse a simple VHDL program: Parse library and use clauses, Parse entity declarations, and Parse architecture bodies. Add some parser infrastructure: Handle syntax errors with useful error messages, Include file name and line numbers in parse errors, Add some parser debug aids.
2010-12-15 06:36:47 +01:00
| K_null
Add parse decorations for expressions. Elaboration will need a parse tree for expressions. Create one for the expression types that are currently supported. Also add rules and the keywords for all the remaining binary logical operators.
2011-01-30 02:27:30 +01:00
{ $$ = 0; }
Flesh out VHDL parser engine. Add enough rules to parse a simple VHDL program: Parse library and use clauses, Parse entity declarations, and Parse architecture bodies. Add some parser infrastructure: Handle syntax errors with useful error messages, Include file name and line numbers in parse errors, Add some parser debug aids.
2010-12-15 06:36:47 +01:00
;
/* Some keywords are optional in some contexts. In all such cases, a
similar rule is used, as described here. */
K_architecture_opt : K_architecture | ;
Basic elaboration of vhdl component instantiations. This gets us as far as emiting a component instantiation. Very little error checking/elaboration is done, so there is room for improvement, but this is a working stub.
2011-04-01 03:50:48 +02:00
K_component_opt : K_component | ;
Basic VHDL configuration parsing The bison grammar has been extended in order to parse configuration statements. Parsing remains very primitive but principal constructs can be now recognized.
2011-03-28 18:59:04 +02:00
K_configuration_opt: K_configuration| ;
Add parser support for architecture declaratives and component instantiations Also include support for "sorry" messages so that we have a place to hang unsupported but properly parsed constructs. In the process of doing this, I also encountered and add parser support for indexed names. And matching "sorry" messages.
2011-03-20 02:26:43 +01:00
K_entity_opt : K_entity | ;
Basic VHDL configuration parsing The bison grammar has been extended in order to parse configuration statements. Parsing remains very primitive but principal constructs can be now recognized.
2011-03-28 18:59:04 +02:00
K_package_opt : K_package | ;
Add parser support for architecture declaratives and component instantiations Also include support for "sorry" messages so that we have a place to hang unsupported but properly parsed constructs. In the process of doing this, I also encountered and add parser support for indexed names. And matching "sorry" messages.
2011-03-20 02:26:43 +01:00
K_is_opt : K_is | ;
Introduce shell of vhdlpp program. Create the makefiles and configuration scripts to hold together the vhdlpp front-end program. Create a shell main.
2010-12-13 05:02:18 +01:00
%%
Add parser support for architecture declaratives and component instantiations Also include support for "sorry" messages so that we have a place to hang unsupported but properly parsed constructs. In the process of doing this, I also encountered and add parser support for indexed names. And matching "sorry" messages.
2011-03-20 02:26:43 +01:00
static void yyerror(const char* /*msg*/)
Introduce shell of vhdlpp program. Create the makefiles and configuration scripts to hold together the vhdlpp front-end program. Create a shell main.
2010-12-13 05:02:18 +01:00
{
Add parser support for architecture declaratives and component instantiations Also include support for "sorry" messages so that we have a place to hang unsupported but properly parsed constructs. In the process of doing this, I also encountered and add parser support for indexed names. And matching "sorry" messages.
2011-03-20 02:26:43 +01:00
//fprintf(stderr, "%s\n", msg);
Flesh out VHDL parser engine. Add enough rules to parse a simple VHDL program: Parse library and use clauses, Parse entity declarations, and Parse architecture bodies. Add some parser infrastructure: Handle syntax errors with useful error messages, Include file name and line numbers in parse errors, Add some parser debug aids.
2010-12-15 06:36:47 +01:00
parse_errors += 1;
}
static const char*file_path = "";
Stub support for library import. This provides a stub implementation for library import. Use this stub to make up a slightly more functional ieee library implementation.
2011-02-19 20:39:00 +01:00
void errormsg(const YYLTYPE&loc, const char*fmt, ...)
Flesh out VHDL parser engine. Add enough rules to parse a simple VHDL program: Parse library and use clauses, Parse entity declarations, and Parse architecture bodies. Add some parser infrastructure: Handle syntax errors with useful error messages, Include file name and line numbers in parse errors, Add some parser debug aids.
2010-12-15 06:36:47 +01:00
{
va_list ap;
va_start(ap, fmt);
Add parser support for architecture declaratives and component instantiations Also include support for "sorry" messages so that we have a place to hang unsupported but properly parsed constructs. In the process of doing this, I also encountered and add parser support for indexed names. And matching "sorry" messages.
2011-03-20 02:26:43 +01:00
fprintf(stderr, "%s:%d: error: ", file_path, loc.first_line);
Flesh out VHDL parser engine. Add enough rules to parse a simple VHDL program: Parse library and use clauses, Parse entity declarations, and Parse architecture bodies. Add some parser infrastructure: Handle syntax errors with useful error messages, Include file name and line numbers in parse errors, Add some parser debug aids.
2010-12-15 06:36:47 +01:00
vfprintf(stderr, fmt, ap);
va_end(ap);
parse_errors += 1;
}
Add parser support for architecture declaratives and component instantiations Also include support for "sorry" messages so that we have a place to hang unsupported but properly parsed constructs. In the process of doing this, I also encountered and add parser support for indexed names. And matching "sorry" messages.
2011-03-20 02:26:43 +01:00
void sorrymsg(const YYLTYPE&loc, const char*fmt, ...)
{
va_list ap;
va_start(ap, fmt);
fprintf(stderr, "%s:%d: sorry: ", file_path, loc.first_line);
vfprintf(stderr, fmt, ap);
va_end(ap);
parse_sorrys += 1;
}
Flesh out VHDL parser engine. Add enough rules to parse a simple VHDL program: Parse library and use clauses, Parse entity declarations, and Parse architecture bodies. Add some parser infrastructure: Handle syntax errors with useful error messages, Include file name and line numbers in parse errors, Add some parser debug aids.
2010-12-15 06:36:47 +01:00
/*
* This is used only by the lexor, to set the file path used in error
* messages.
*/
void yyparse_set_filepath(const char*path)
{
file_path = path;
Introduce shell of vhdlpp program. Create the makefiles and configuration scripts to hold together the vhdlpp front-end program. Create a shell main.
2010-12-13 05:02:18 +01:00
}