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Introduce shell of vhdlpp program. Create the makefiles and configuration scripts to hold together the vhdlpp front-end program. Create a shell main.
2010-12-13 05:02:18 +01:00
%{
/*
* Copyright (c) 2011 Stephen Williams (steve@icarus.com)
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
# include "vhdlpp_config.h"
Added full number, based number (both int and float), string and character literals handling
2011-02-04 17:51:51 +01:00
# include "vhdlint.h"
Introductory changes for numbers handling
2011-01-31 18:25:29 +01:00
# include "vhdlreal.h"
Parse create entities with ports Create entity objects from entity declarations in the source, and populate them with ports.
2011-01-03 07:30:09 +01:00
# include "compiler.h"
Introduce shell of vhdlpp program. Create the makefiles and configuration scripts to hold together the vhdlpp front-end program. Create a shell main.
2010-12-13 05:02:18 +01:00
# include "parse_api.h"
Create an Architecture class and bind them to their entities.
2011-01-24 05:26:27 +01:00
# include "parse_misc.h"
# include "architec.h"
Add parse decorations for expressions. Elaboration will need a parse tree for expressions. Create one for the expression types that are currently supported. Also add rules and the keywords for all the remaining binary logical operators.
2011-01-30 02:27:30 +01:00
# include "expression.h"
Flesh out VHDL parser engine. Add enough rules to parse a simple VHDL program: Parse library and use clauses, Parse entity declarations, and Parse architecture bodies. Add some parser infrastructure: Handle syntax errors with useful error messages, Include file name and line numbers in parse errors, Add some parser debug aids.
2010-12-15 06:36:47 +01:00
# include <cstdarg>
Parse create entities with ports Create entity objects from entity declarations in the source, and populate them with ports.
2011-01-03 07:30:09 +01:00
# include <list>
Introduce shell of vhdlpp program. Create the makefiles and configuration scripts to hold together the vhdlpp front-end program. Create a shell main.
2010-12-13 05:02:18 +01:00
Add file/line information to entities and ports Include the compiler infrastructure to vhdlpp for collecting the file and line information and attaching it to entities and ports. Make the parser store the file name during parse. Create a libmisc library where I can put source files that are used by multiple programs within the source tree.
2011-01-06 18:27:30 +01:00
inline void FILE_NAME(LineInfo*tmp, const struct yyltype&where)
{
tmp->set_lineno(where.first_line);
tmp->set_file(filename_strings.make(where.text));
}
Introduce shell of vhdlpp program. Create the makefiles and configuration scripts to hold together the vhdlpp front-end program. Create a shell main.
2010-12-13 05:02:18 +01:00
static void yyerror(const char*msg);
Flesh out VHDL parser engine. Add enough rules to parse a simple VHDL program: Parse library and use clauses, Parse entity declarations, and Parse architecture bodies. Add some parser infrastructure: Handle syntax errors with useful error messages, Include file name and line numbers in parse errors, Add some parser debug aids.
2010-12-15 06:36:47 +01:00
static void errormsg(const YYLTYPE&loc, const char*msg, ...);
int parse_errors = 0;
Introduce shell of vhdlpp program. Create the makefiles and configuration scripts to hold together the vhdlpp front-end program. Create a shell main.
2010-12-13 05:02:18 +01:00
%}
Introductory changes for numbers handling
2011-01-31 18:25:29 +01:00
Parse create entities with ports Create entity objects from entity declarations in the source, and populate them with ports.
2011-01-03 07:30:09 +01:00
%union {
port_mode_t port_mode;
char*text;
Add parse decorations for expressions. Elaboration will need a parse tree for expressions. Create one for the expression types that are currently supported. Also add rules and the keywords for all the remaining binary logical operators.
2011-01-30 02:27:30 +01:00
Added full number, based number (both int and float), string and character literals handling
2011-02-04 17:51:51 +01:00
vhdlint* integer;
Introductory changes for numbers handling
2011-01-31 18:25:29 +01:00
vhdlreal* real;
Add parse decorations for expressions. Elaboration will need a parse tree for expressions. Create one for the expression types that are currently supported. Also add rules and the keywords for all the remaining binary logical operators.
2011-01-30 02:27:30 +01:00
Expression*expr;
std::list<Expression*>* expr_list;
Parse create entities with ports Create entity objects from entity declarations in the source, and populate them with ports.
2011-01-03 07:30:09 +01:00
InterfacePort*interface_element;
std::list<InterfacePort*>* interface_list;
Annotate the parse of simple concurrent statements.
2011-01-27 05:38:20 +01:00
Architecture::Statement* arch_statement;
std::list<Architecture::Statement*>* arch_statement_list;
Parse create entities with ports Create entity objects from entity declarations in the source, and populate them with ports.
2011-01-03 07:30:09 +01:00
};
Introduce shell of vhdlpp program. Create the makefiles and configuration scripts to hold together the vhdlpp front-end program. Create a shell main.
2010-12-13 05:02:18 +01:00
/* The keywords are all tokens. */
%token K_abs K_access K_after K_alias K_all K_and K_architecture
%token K_array K_assert K_assume K_assume_guarantee K_attribute
%token K_begin K_block K_body K_buffer K_bus
%token K_case K_component K_configuration K_constant K_context K_cover
New keywords to lexer added and typos corrected
2011-01-27 15:13:38 +01:00
%token K_default K_disconnect K_downto
Introduce shell of vhdlpp program. Create the makefiles and configuration scripts to hold together the vhdlpp front-end program. Create a shell main.
2010-12-13 05:02:18 +01:00
%token K_else K_elsif K_end K_entity K_exit
%token K_fairness K_file K_for K_force K_function
%token K_generate K_generic K_group K_guarded
New keywords to lexer added and typos corrected
2011-01-27 15:13:38 +01:00
%token K_if K_impure K_in K_inertial K_inout K_is
Introduce shell of vhdlpp program. Create the makefiles and configuration scripts to hold together the vhdlpp front-end program. Create a shell main.
2010-12-13 05:02:18 +01:00
%token K_label K_library K_linkage K_literal K_loop
%token K_map K_mod
%token K_nand K_new K_next K_nor K_not K_null
%token K_of K_on K_open K_or K_others K_out
%token K_package K_parameter K_port K_postponed K_procedure K_process
%token K_property K_protected K_pure
%token K_range K_record K_register K_reject K_release K_rem K_report
%token K_restrict K_restrict_guarantee K_return K_rol K_ror
New keywords to lexer added and typos corrected
2011-01-27 15:13:38 +01:00
%token K_select K_sequence K_severity K_signal K_shared
Minor changes to VHDL lexor
2011-01-28 10:40:38 +01:00
%token K_sla K_sll K_sra K_srl K_strong K_subtype
Introduce shell of vhdlpp program. Create the makefiles and configuration scripts to hold together the vhdlpp front-end program. Create a shell main.
2010-12-13 05:02:18 +01:00
%token K_then K_to K_transport K_type
%token K_unaffected K_units K_until K_use
%token K_variable K_vmode K_vprop K_vunit
%token K_wait K_when K_while K_with
%token K_xnor K_xor
/* Identifiers that are not keywords are identifiers. */
Parse create entities with ports Create entity objects from entity declarations in the source, and populate them with ports.
2011-01-03 07:30:09 +01:00
%token <text> IDENTIFIER
Introductory changes for numbers handling
2011-01-31 18:25:29 +01:00
%token <integer> INT_LITERAL
%token <real> REAL_LITERAL
%token <text> STRING_LITERAL CHARACTER_LITERAL
Flesh out VHDL parser engine. Add enough rules to parse a simple VHDL program: Parse library and use clauses, Parse entity declarations, and Parse architecture bodies. Add some parser infrastructure: Handle syntax errors with useful error messages, Include file name and line numbers in parse errors, Add some parser debug aids.
2010-12-15 06:36:47 +01:00
/* compound symbols */
Introductory changes for numbers handling
2011-01-31 18:25:29 +01:00
%token LEQ GEQ VASSIGN NE BOX EXP ARROW DLT DGT
Flesh out VHDL parser engine. Add enough rules to parse a simple VHDL program: Parse library and use clauses, Parse entity declarations, and Parse architecture bodies. Add some parser infrastructure: Handle syntax errors with useful error messages, Include file name and line numbers in parse errors, Add some parser debug aids.
2010-12-15 06:36:47 +01:00
Parse create entities with ports Create entity objects from entity declarations in the source, and populate them with ports.
2011-01-03 07:30:09 +01:00
/* The rules may have types. */
Annotate the parse of simple concurrent statements.
2011-01-27 05:38:20 +01:00
Parse create entities with ports Create entity objects from entity declarations in the source, and populate them with ports.
2011-01-03 07:30:09 +01:00
%type <interface_element> interface_element
%type <interface_list> interface_list entity_header port_clause
%type <port_mode> mode
Annotate the parse of simple concurrent statements.
2011-01-27 05:38:20 +01:00
%type <arch_statement> concurrent_statement concurrent_signal_assignment_statement
%type <arch_statement_list> architecture_statement_part
Add parse decorations for expressions. Elaboration will need a parse tree for expressions. Create one for the expression types that are currently supported. Also add rules and the keywords for all the remaining binary logical operators.
2011-01-30 02:27:30 +01:00
%type <expr> expression expression_logical factor primary relation
%type <expr> shift_expression simple_expression term waveform_element
%type <expr_list> waveform waveform_elements
Introduce shell of vhdlpp program. Create the makefiles and configuration scripts to hold together the vhdlpp front-end program. Create a shell main.
2010-12-13 05:02:18 +01:00
%%
Flesh out VHDL parser engine. Add enough rules to parse a simple VHDL program: Parse library and use clauses, Parse entity declarations, and Parse architecture bodies. Add some parser infrastructure: Handle syntax errors with useful error messages, Include file name and line numbers in parse errors, Add some parser debug aids.
2010-12-15 06:36:47 +01:00
/* The design_file is the root for the VHDL parse. */
design_file : design_units ;
architecture_body
: K_architecture IDENTIFIER
K_of IDENTIFIER
K_is
K_begin architecture_statement_part K_end K_architecture_opt ';'
Annotate the parse of simple concurrent statements.
2011-01-27 05:38:20 +01:00
{ Architecture*tmp = new Architecture(lex_strings.make($2), *$7);
Create an Architecture class and bind them to their entities.
2011-01-24 05:26:27 +01:00
FILE_NAME(tmp, @1);
bind_architecture_to_entity($4, tmp);
delete[]$2;
delete[]$4;
Annotate the parse of simple concurrent statements.
2011-01-27 05:38:20 +01:00
delete $7;
Create an Architecture class and bind them to their entities.
2011-01-24 05:26:27 +01:00
}
Flesh out VHDL parser engine. Add enough rules to parse a simple VHDL program: Parse library and use clauses, Parse entity declarations, and Parse architecture bodies. Add some parser infrastructure: Handle syntax errors with useful error messages, Include file name and line numbers in parse errors, Add some parser debug aids.
2010-12-15 06:36:47 +01:00
| K_architecture IDENTIFIER
K_of IDENTIFIER
K_is
K_begin error K_end K_architecture_opt ';'
{ errormsg(@1, "Syntax error in architecture statement.\n"); yyerrok; }
| K_architecture error ';'
{ errormsg(@1, "Syntax error in architecture body.\n"); yyerrok; }
;
/* The architecture_statement_part is a list of concurrent
statements. */
architecture_statement_part
: architecture_statement_part concurrent_statement
Annotate the parse of simple concurrent statements.
2011-01-27 05:38:20 +01:00
{ std::list<Architecture::Statement*>*tmp = $1;
tmp->push_back($2);
$$ = tmp;
}
Flesh out VHDL parser engine. Add enough rules to parse a simple VHDL program: Parse library and use clauses, Parse entity declarations, and Parse architecture bodies. Add some parser infrastructure: Handle syntax errors with useful error messages, Include file name and line numbers in parse errors, Add some parser debug aids.
2010-12-15 06:36:47 +01:00
| concurrent_statement
Annotate the parse of simple concurrent statements.
2011-01-27 05:38:20 +01:00
{ std::list<Architecture::Statement*>*tmp = new std::list<Architecture::Statement*>;
tmp->push_back($1);
$$ = tmp;
}
Flesh out VHDL parser engine. Add enough rules to parse a simple VHDL program: Parse library and use clauses, Parse entity declarations, and Parse architecture bodies. Add some parser infrastructure: Handle syntax errors with useful error messages, Include file name and line numbers in parse errors, Add some parser debug aids.
2010-12-15 06:36:47 +01:00
;
concurrent_signal_assignment_statement
: IDENTIFIER LEQ waveform ';'
Annotate the parse of simple concurrent statements.
2011-01-27 05:38:20 +01:00
{ perm_string targ_name = lex_strings.make($1);
Add parse decorations for expressions. Elaboration will need a parse tree for expressions. Create one for the expression types that are currently supported. Also add rules and the keywords for all the remaining binary logical operators.
2011-01-30 02:27:30 +01:00
SignalAssignment*tmp = new SignalAssignment(targ_name, *$3);
Annotate the parse of simple concurrent statements.
2011-01-27 05:38:20 +01:00
FILE_NAME(tmp, @1);
$$ = tmp;
delete[]$1;
Add parse decorations for expressions. Elaboration will need a parse tree for expressions. Create one for the expression types that are currently supported. Also add rules and the keywords for all the remaining binary logical operators.
2011-01-30 02:27:30 +01:00
delete $3;
Annotate the parse of simple concurrent statements.
2011-01-27 05:38:20 +01:00
}
Flesh out VHDL parser engine. Add enough rules to parse a simple VHDL program: Parse library and use clauses, Parse entity declarations, and Parse architecture bodies. Add some parser infrastructure: Handle syntax errors with useful error messages, Include file name and line numbers in parse errors, Add some parser debug aids.
2010-12-15 06:36:47 +01:00
;
concurrent_statement
: concurrent_signal_assignment_statement
;
context_clause : context_items | ;
context_item
: library_clause
| use_clause
;
context_items
: context_items context_item
| context_item
;
design_unit
: context_clause library_unit
| error { errormsg(@1, "Invalid design_unit\n"); }
;
design_units
: design_units design_unit
| design_unit
;
Parse create entities with ports Create entity objects from entity declarations in the source, and populate them with ports.
2011-01-03 07:30:09 +01:00
/* As an entity is declared, add it to the map of design entities. */
Flesh out VHDL parser engine. Add enough rules to parse a simple VHDL program: Parse library and use clauses, Parse entity declarations, and Parse architecture bodies. Add some parser infrastructure: Handle syntax errors with useful error messages, Include file name and line numbers in parse errors, Add some parser debug aids.
2010-12-15 06:36:47 +01:00
entity_declaration
Entity parsing changed
2011-01-26 19:11:29 +01:00
: K_entity IDENTIFIER K_is entity_header K_end K_entity_opt ';'
Create an Architecture class and bind them to their entities.
2011-01-24 05:26:27 +01:00
{ Entity*tmp = new Entity(lex_strings.make($2));
Add file/line information to entities and ports Include the compiler infrastructure to vhdlpp for collecting the file and line information and attaching it to entities and ports. Make the parser store the file name during parse. Create a libmisc library where I can put source files that are used by multiple programs within the source tree.
2011-01-06 18:27:30 +01:00
FILE_NAME(tmp, @1);
Parse create entities with ports Create entity objects from entity declarations in the source, and populate them with ports.
2011-01-03 07:30:09 +01:00
// Transfer the ports
std::list<InterfacePort*>*ports = $4;
Clean up entity interface.
2011-02-03 04:59:20 +01:00
tmp->set_interface(ports);
Parse create entities with ports Create entity objects from entity declarations in the source, and populate them with ports.
2011-01-03 07:30:09 +01:00
delete ports;
// Save the entity in the entity map.
Create an Architecture class and bind them to their entities.
2011-01-24 05:26:27 +01:00
design_entities[tmp->get_name()] = tmp;
delete[]$2;
Fix identation style.
2011-01-27 02:44:58 +01:00
}
Entity parsing changed
2011-01-26 19:11:29 +01:00
| K_entity IDENTIFIER K_is entity_header K_end K_entity_opt IDENTIFIER ';'
Create an Architecture class and bind them to their entities.
2011-01-24 05:26:27 +01:00
{ Entity*tmp = new Entity(lex_strings.make($2));
Entity parsing changed
2011-01-26 19:11:29 +01:00
FILE_NAME(tmp, @1);
Create an Architecture class and bind them to their entities.
2011-01-24 05:26:27 +01:00
if(tmp->get_name() != $7) {
errormsg(@1, "Syntax error in entity clause. \n");
Entity parsing changed
2011-01-26 19:11:29 +01:00
}
delete[]$2;
delete[]$7;
// Transfer the ports
std::list<InterfacePort*>*ports = $4;
Clean up entity interface.
2011-02-03 04:59:20 +01:00
tmp->set_interface(ports);
Entity parsing changed
2011-01-26 19:11:29 +01:00
delete ports;
// Save the entity in the entity map.
Create an Architecture class and bind them to their entities.
2011-01-24 05:26:27 +01:00
design_entities[tmp->get_name()] = tmp;
Fix identation style.
2011-01-27 02:44:58 +01:00
}
Flesh out VHDL parser engine. Add enough rules to parse a simple VHDL program: Parse library and use clauses, Parse entity declarations, and Parse architecture bodies. Add some parser infrastructure: Handle syntax errors with useful error messages, Include file name and line numbers in parse errors, Add some parser debug aids.
2010-12-15 06:36:47 +01:00
;
entity_header
: port_clause
Parse create entities with ports Create entity objects from entity declarations in the source, and populate them with ports.
2011-01-03 07:30:09 +01:00
{ $$ = $1; }
Flesh out VHDL parser engine. Add enough rules to parse a simple VHDL program: Parse library and use clauses, Parse entity declarations, and Parse architecture bodies. Add some parser infrastructure: Handle syntax errors with useful error messages, Include file name and line numbers in parse errors, Add some parser debug aids.
2010-12-15 06:36:47 +01:00
;
expression
: expression_logical
Add parse decorations for expressions. Elaboration will need a parse tree for expressions. Create one for the expression types that are currently supported. Also add rules and the keywords for all the remaining binary logical operators.
2011-01-30 02:27:30 +01:00
{ $$ = $1; }
Flesh out VHDL parser engine. Add enough rules to parse a simple VHDL program: Parse library and use clauses, Parse entity declarations, and Parse architecture bodies. Add some parser infrastructure: Handle syntax errors with useful error messages, Include file name and line numbers in parse errors, Add some parser debug aids.
2010-12-15 06:36:47 +01:00
;
expression_logical
: relation K_and relation
Add parse decorations for expressions. Elaboration will need a parse tree for expressions. Create one for the expression types that are currently supported. Also add rules and the keywords for all the remaining binary logical operators.
2011-01-30 02:27:30 +01:00
{ ExpLogical*tmp = new ExpLogical(ExpLogical::AND, $1, $3);
FILE_NAME(tmp, @2);
$$ = tmp;
}
Flesh out VHDL parser engine. Add enough rules to parse a simple VHDL program: Parse library and use clauses, Parse entity declarations, and Parse architecture bodies. Add some parser infrastructure: Handle syntax errors with useful error messages, Include file name and line numbers in parse errors, Add some parser debug aids.
2010-12-15 06:36:47 +01:00
| relation K_or relation
Add parse decorations for expressions. Elaboration will need a parse tree for expressions. Create one for the expression types that are currently supported. Also add rules and the keywords for all the remaining binary logical operators.
2011-01-30 02:27:30 +01:00
{ ExpLogical*tmp = new ExpLogical(ExpLogical::OR, $1, $3);
FILE_NAME(tmp, @2);
$$ = tmp;
}
| relation K_xor relation
{ ExpLogical*tmp = new ExpLogical(ExpLogical::XOR, $1, $3);
FILE_NAME(tmp, @2);
$$ = tmp;
}
| relation K_nand relation
{ ExpLogical*tmp = new ExpLogical(ExpLogical::NAND, $1, $3);
FILE_NAME(tmp, @2);
$$ = tmp;
}
| relation K_nor relation
{ ExpLogical*tmp = new ExpLogical(ExpLogical::NOR, $1, $3);
FILE_NAME(tmp, @2);
$$ = tmp;
}
| relation K_xnor relation
{ ExpLogical*tmp = new ExpLogical(ExpLogical::XNOR, $1, $3);
FILE_NAME(tmp, @2);
$$ = tmp;
}
Flesh out VHDL parser engine. Add enough rules to parse a simple VHDL program: Parse library and use clauses, Parse entity declarations, and Parse architecture bodies. Add some parser infrastructure: Handle syntax errors with useful error messages, Include file name and line numbers in parse errors, Add some parser debug aids.
2010-12-15 06:36:47 +01:00
;
Add parse decorations for expressions. Elaboration will need a parse tree for expressions. Create one for the expression types that are currently supported. Also add rules and the keywords for all the remaining binary logical operators.
2011-01-30 02:27:30 +01:00
factor : primary { $$ = $1; } ;
Flesh out VHDL parser engine. Add enough rules to parse a simple VHDL program: Parse library and use clauses, Parse entity declarations, and Parse architecture bodies. Add some parser infrastructure: Handle syntax errors with useful error messages, Include file name and line numbers in parse errors, Add some parser debug aids.
2010-12-15 06:36:47 +01:00
/* The interface_element is also an interface_declaration */
interface_element
: IDENTIFIER ':' mode IDENTIFIER
Parse create entities with ports Create entity objects from entity declarations in the source, and populate them with ports.
2011-01-03 07:30:09 +01:00
{ InterfacePort*tmp = new InterfacePort;
Add file/line information to entities and ports Include the compiler infrastructure to vhdlpp for collecting the file and line information and attaching it to entities and ports. Make the parser store the file name during parse. Create a libmisc library where I can put source files that are used by multiple programs within the source tree.
2011-01-06 18:27:30 +01:00
FILE_NAME(tmp, @1);
Parse create entities with ports Create entity objects from entity declarations in the source, and populate them with ports.
2011-01-03 07:30:09 +01:00
tmp->mode = $3;
tmp->name = lex_strings.make($1);
Save the type name if an InterfacePort object.
2011-01-06 17:12:55 +01:00
tmp->type_name = lex_strings.make($4);
Parse create entities with ports Create entity objects from entity declarations in the source, and populate them with ports.
2011-01-03 07:30:09 +01:00
delete[]$1;
delete[]$4;
$$ = tmp;
}
Flesh out VHDL parser engine. Add enough rules to parse a simple VHDL program: Parse library and use clauses, Parse entity declarations, and Parse architecture bodies. Add some parser infrastructure: Handle syntax errors with useful error messages, Include file name and line numbers in parse errors, Add some parser debug aids.
2010-12-15 06:36:47 +01:00
;
interface_list
: interface_list ';' interface_element
Save the type name if an InterfacePort object.
2011-01-06 17:12:55 +01:00
{ std::list<InterfacePort*>*tmp = $1;
Parse create entities with ports Create entity objects from entity declarations in the source, and populate them with ports.
2011-01-03 07:30:09 +01:00
tmp->push_back($3);
$$ = tmp;
}
Flesh out VHDL parser engine. Add enough rules to parse a simple VHDL program: Parse library and use clauses, Parse entity declarations, and Parse architecture bodies. Add some parser infrastructure: Handle syntax errors with useful error messages, Include file name and line numbers in parse errors, Add some parser debug aids.
2010-12-15 06:36:47 +01:00
| interface_element
Parse create entities with ports Create entity objects from entity declarations in the source, and populate them with ports.
2011-01-03 07:30:09 +01:00
{ std::list<InterfacePort*>*tmp = new std::list<InterfacePort*>;
tmp->push_back($1);
$$ = tmp;
}
Flesh out VHDL parser engine. Add enough rules to parse a simple VHDL program: Parse library and use clauses, Parse entity declarations, and Parse architecture bodies. Add some parser infrastructure: Handle syntax errors with useful error messages, Include file name and line numbers in parse errors, Add some parser debug aids.
2010-12-15 06:36:47 +01:00
;
library_clause
: K_library logical_name_list ';'
| K_library error ';'
{ errormsg(@1, "Syntax error in library clause.\n"); yyerrok; }
;
/* Collapse the primary_unit and secondary_unit of the library_unit
into this single set of rules. */
library_unit
: entity_declaration
| architecture_body
;
logical_name : IDENTIFIER ;
logical_name_list
: logical_name_list ',' logical_name
| logical_name
;
Parse create entities with ports Create entity objects from entity declarations in the source, and populate them with ports.
2011-01-03 07:30:09 +01:00
mode
: K_in { $$ = PORT_IN; }
| K_out { $$ = PORT_OUT; }
;
Flesh out VHDL parser engine. Add enough rules to parse a simple VHDL program: Parse library and use clauses, Parse entity declarations, and Parse architecture bodies. Add some parser infrastructure: Handle syntax errors with useful error messages, Include file name and line numbers in parse errors, Add some parser debug aids.
2010-12-15 06:36:47 +01:00
Parse create entities with ports Create entity objects from entity declarations in the source, and populate them with ports.
2011-01-03 07:30:09 +01:00
port_clause
: K_port '(' interface_list ')' ';'
{ $$ = $3; }
;
Flesh out VHDL parser engine. Add enough rules to parse a simple VHDL program: Parse library and use clauses, Parse entity declarations, and Parse architecture bodies. Add some parser infrastructure: Handle syntax errors with useful error messages, Include file name and line numbers in parse errors, Add some parser debug aids.
2010-12-15 06:36:47 +01:00
primary
: IDENTIFIER
Add parse decorations for expressions. Elaboration will need a parse tree for expressions. Create one for the expression types that are currently supported. Also add rules and the keywords for all the remaining binary logical operators.
2011-01-30 02:27:30 +01:00
{ ExpName*tmp = new ExpName(lex_strings.make($1));
FILE_NAME(tmp, @1);
delete[]$1;
$$ = tmp;
}
Flesh out VHDL parser engine. Add enough rules to parse a simple VHDL program: Parse library and use clauses, Parse entity declarations, and Parse architecture bodies. Add some parser infrastructure: Handle syntax errors with useful error messages, Include file name and line numbers in parse errors, Add some parser debug aids.
2010-12-15 06:36:47 +01:00
;
Add parse decorations for expressions. Elaboration will need a parse tree for expressions. Create one for the expression types that are currently supported. Also add rules and the keywords for all the remaining binary logical operators.
2011-01-30 02:27:30 +01:00
relation : shift_expression { $$ = $1; } ;
Flesh out VHDL parser engine. Add enough rules to parse a simple VHDL program: Parse library and use clauses, Parse entity declarations, and Parse architecture bodies. Add some parser infrastructure: Handle syntax errors with useful error messages, Include file name and line numbers in parse errors, Add some parser debug aids.
2010-12-15 06:36:47 +01:00
selected_name
: IDENTIFIER '.' K_all
| IDENTIFIER '.' IDENTIFIER '.' K_all
;
selected_names
: selected_names ',' selected_name
| selected_name
;
Add parse decorations for expressions. Elaboration will need a parse tree for expressions. Create one for the expression types that are currently supported. Also add rules and the keywords for all the remaining binary logical operators.
2011-01-30 02:27:30 +01:00
shift_expression : simple_expression { $$ = $1; } ;
Flesh out VHDL parser engine. Add enough rules to parse a simple VHDL program: Parse library and use clauses, Parse entity declarations, and Parse architecture bodies. Add some parser infrastructure: Handle syntax errors with useful error messages, Include file name and line numbers in parse errors, Add some parser debug aids.
2010-12-15 06:36:47 +01:00
Add parse decorations for expressions. Elaboration will need a parse tree for expressions. Create one for the expression types that are currently supported. Also add rules and the keywords for all the remaining binary logical operators.
2011-01-30 02:27:30 +01:00
simple_expression : term { $$ = $1; } ;
Flesh out VHDL parser engine. Add enough rules to parse a simple VHDL program: Parse library and use clauses, Parse entity declarations, and Parse architecture bodies. Add some parser infrastructure: Handle syntax errors with useful error messages, Include file name and line numbers in parse errors, Add some parser debug aids.
2010-12-15 06:36:47 +01:00
Add parse decorations for expressions. Elaboration will need a parse tree for expressions. Create one for the expression types that are currently supported. Also add rules and the keywords for all the remaining binary logical operators.
2011-01-30 02:27:30 +01:00
term : factor { $$ = $1; } ;
Flesh out VHDL parser engine. Add enough rules to parse a simple VHDL program: Parse library and use clauses, Parse entity declarations, and Parse architecture bodies. Add some parser infrastructure: Handle syntax errors with useful error messages, Include file name and line numbers in parse errors, Add some parser debug aids.
2010-12-15 06:36:47 +01:00
use_clause
: K_use selected_names ';'
| K_use error ';'
{ errormsg(@1, "Syntax error in use clause.\n"); yyerrok; }
;
waveform
: waveform_elements
Add parse decorations for expressions. Elaboration will need a parse tree for expressions. Create one for the expression types that are currently supported. Also add rules and the keywords for all the remaining binary logical operators.
2011-01-30 02:27:30 +01:00
{ $$ = $1; }
Flesh out VHDL parser engine. Add enough rules to parse a simple VHDL program: Parse library and use clauses, Parse entity declarations, and Parse architecture bodies. Add some parser infrastructure: Handle syntax errors with useful error messages, Include file name and line numbers in parse errors, Add some parser debug aids.
2010-12-15 06:36:47 +01:00
| K_unaffected
Add parse decorations for expressions. Elaboration will need a parse tree for expressions. Create one for the expression types that are currently supported. Also add rules and the keywords for all the remaining binary logical operators.
2011-01-30 02:27:30 +01:00
{ $$ = 0; }
Flesh out VHDL parser engine. Add enough rules to parse a simple VHDL program: Parse library and use clauses, Parse entity declarations, and Parse architecture bodies. Add some parser infrastructure: Handle syntax errors with useful error messages, Include file name and line numbers in parse errors, Add some parser debug aids.
2010-12-15 06:36:47 +01:00
;
waveform_elements
: waveform_elements ',' waveform_element
Add parse decorations for expressions. Elaboration will need a parse tree for expressions. Create one for the expression types that are currently supported. Also add rules and the keywords for all the remaining binary logical operators.
2011-01-30 02:27:30 +01:00
{ std::list<Expression*>*tmp = $1;
tmp->push_back($3);
$$ = tmp;
}
Flesh out VHDL parser engine. Add enough rules to parse a simple VHDL program: Parse library and use clauses, Parse entity declarations, and Parse architecture bodies. Add some parser infrastructure: Handle syntax errors with useful error messages, Include file name and line numbers in parse errors, Add some parser debug aids.
2010-12-15 06:36:47 +01:00
| waveform_element
Add parse decorations for expressions. Elaboration will need a parse tree for expressions. Create one for the expression types that are currently supported. Also add rules and the keywords for all the remaining binary logical operators.
2011-01-30 02:27:30 +01:00
{ std::list<Expression*>*tmp = new std::list<Expression*>;
tmp->push_back($1);
$$ = tmp;
}
Flesh out VHDL parser engine. Add enough rules to parse a simple VHDL program: Parse library and use clauses, Parse entity declarations, and Parse architecture bodies. Add some parser infrastructure: Handle syntax errors with useful error messages, Include file name and line numbers in parse errors, Add some parser debug aids.
2010-12-15 06:36:47 +01:00
;
waveform_element
: expression
Add parse decorations for expressions. Elaboration will need a parse tree for expressions. Create one for the expression types that are currently supported. Also add rules and the keywords for all the remaining binary logical operators.
2011-01-30 02:27:30 +01:00
{ $$ = $1; }
Flesh out VHDL parser engine. Add enough rules to parse a simple VHDL program: Parse library and use clauses, Parse entity declarations, and Parse architecture bodies. Add some parser infrastructure: Handle syntax errors with useful error messages, Include file name and line numbers in parse errors, Add some parser debug aids.
2010-12-15 06:36:47 +01:00
| K_null
Add parse decorations for expressions. Elaboration will need a parse tree for expressions. Create one for the expression types that are currently supported. Also add rules and the keywords for all the remaining binary logical operators.
2011-01-30 02:27:30 +01:00
{ $$ = 0; }
Flesh out VHDL parser engine. Add enough rules to parse a simple VHDL program: Parse library and use clauses, Parse entity declarations, and Parse architecture bodies. Add some parser infrastructure: Handle syntax errors with useful error messages, Include file name and line numbers in parse errors, Add some parser debug aids.
2010-12-15 06:36:47 +01:00
;
/* Some keywords are optional in some contexts. In all such cases, a
similar rule is used, as described here. */
K_architecture_opt : K_architecture | ;
Entity parsing changed
2011-01-26 19:11:29 +01:00
K_entity_opt : K_entity | ;
Introduce shell of vhdlpp program. Create the makefiles and configuration scripts to hold together the vhdlpp front-end program. Create a shell main.
2010-12-13 05:02:18 +01:00
%%
static void yyerror(const char*msg)
{
Flesh out VHDL parser engine. Add enough rules to parse a simple VHDL program: Parse library and use clauses, Parse entity declarations, and Parse architecture bodies. Add some parser infrastructure: Handle syntax errors with useful error messages, Include file name and line numbers in parse errors, Add some parser debug aids.
2010-12-15 06:36:47 +01:00
fprintf(stderr, "%s\n", msg);
parse_errors += 1;
}
static const char*file_path = "";
static void errormsg(const YYLTYPE&loc, const char*fmt, ...)
{
va_list ap;
va_start(ap, fmt);
fprintf(stderr, "%s:%d: ", file_path, loc.first_line);
vfprintf(stderr, fmt, ap);
va_end(ap);
parse_errors += 1;
}
/*
* This is used only by the lexor, to set the file path used in error
* messages.
*/
void yyparse_set_filepath(const char*path)
{
file_path = path;
Introduce shell of vhdlpp program. Create the makefiles and configuration scripts to hold together the vhdlpp front-end program. Create a shell main.
2010-12-13 05:02:18 +01:00
}