luke
/
abc
mirror of https://github.com/YosysHQ/abc.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity
774 Commits 27 Branches 57 Tags 58 MiB
Commit Graph

774 Commits

Author SHA1 Message Date
Alan Mishchenko fe6d1ff7da New hierarchy manager. 2012-01-18 02:25:12 -08:00
Alan Mishchenko 2fd746ed94 Removing debug print-outs from the SAT solver. 2012-01-17 23:57:02 -08:00
Alan Mishchenko 2a236864ab Changes to the lazy man's synthesis code. 2012-01-17 23:38:11 -08:00
Alan Mishchenko d8d705c717 New hierarchy manager. 2012-01-17 23:19:47 -08:00
Alan Mishchenko 67300e056b Small bug induced by changes in the SAT solver. 2012-01-17 23:09:19 -08:00
Alan Mishchenko 25914e417a Added notification about exceeding the number of nodes. 2012-01-17 22:40:40 -08:00
Alan Mishchenko 6bff2986a2 New hierarchy manager. 2012-01-17 15:02:25 -08:00
Alan Mishchenko 940d5d66b2 Variable timeframe abstraction. 2012-01-16 22:07:09 -08:00
Alan Mishchenko be5256c926 New hierarchy manager. 2012-01-16 22:06:59 -08:00
Alan Mishchenko 08f6d49fb7 Removing additional printout in the GIA package. 2012-01-16 13:29:47 -08:00
Alan Mishchenko 0695ec5473 New hierarchy manager plus additional printout in the GIA package. 2012-01-16 13:07:51 -08:00
Alan Mishchenko ca28f77f3a Variable timeframe abstraction. 2012-01-16 12:21:53 -08:00
Alan Mishchenko 10478a9cbf Variable timeframe abstraction. 2012-01-15 20:47:58 -08:00
Alan Mishchenko bb4897aba6 Changes to the lazy man's synthesis code. 2012-01-15 12:35:04 -08:00
Alan Mishchenko 1f0e5533dc Several small bug fixes in the mapper. 2012-01-15 09:15:10 -08:00
Alan Mishchenko 60a84f7350 Changes to the lazy man's synthesis code. 2012-01-14 23:39:53 -08:00
Alan Mishchenko 868ed19469 Changes to the lazy man's synthesis code. 2012-01-14 22:37:25 -08:00
Alan Mishchenko ac7e665bf6 Bug fixes in the Verilog parser. 2012-01-14 22:21:23 -08:00
Alan Mishchenko c7e215ca31 New hierarchy manager. 2012-01-14 18:05:12 -08:00
Alan Mishchenko 9c409addca Support computation experiments with different network data-structures. 2012-01-14 18:04:47 -08:00
Alan Mishchenko 4748f6988e Small bug fix in printing DSD for Boolean functions. 2012-01-14 18:03:06 -08:00
Alan Mishchenko 7a3c33e169 New hierarchy manager. 2012-01-13 22:49:08 -08:00
Alan Mishchenko 5fff8354ce New hierarchy manager. 2012-01-13 22:02:04 -08:00
Alan Mishchenko b7ba9aa8dc New hierarchy manager. 2012-01-13 20:58:28 -08:00
Alan Mishchenko 37b8a190ba Improving printout in the SAT solver. 2012-01-13 20:57:26 -08:00
Alan Mishchenko c48925dfb6 Commented out a printout line which cases a warning to be printed. 2012-01-13 19:34:00 -08:00
Alan Mishchenko 1aeaacc03d Added bit vector. 2012-01-13 19:31:58 -08:00
Alan Mishchenko 4bd7efa6cd Added counting hits and misses during structural hashing. 2012-01-13 19:31:13 -08:00
Alan Mishchenko edbff75fff New hierarchy manager. 2012-01-13 18:10:00 -08:00
Alan Mishchenko eecbbea24b New hierarchy manager. 2012-01-13 17:50:21 -08:00
Alan Mishchenko 095345fc4a Added new name manager and modified hierarchy manager to use it. 2012-01-13 15:43:09 -08:00
Alan Mishchenko cb2d12bb04 New hierarchy manager. 2012-01-13 00:34:13 -08:00
Alan Mishchenko 2e1dcdd239 Added model ID inside the design. 2012-01-12 23:29:47 -08:00
Alan Mishchenko 56cc5734a4 Bug fix related to not properly resizing SAT solver's model array. 2012-01-12 07:28:01 -08:00
Alan Mishchenko fadde52dc6 Changes to the lazy man's synthesis code. 2012-01-11 22:08:35 -08:00
Alan Mishchenko 22ae2e452a Gate level abstraction. 2012-01-11 14:51:00 -08:00
Alan Mishchenko 564a3553f0 Gate level abstraction. 2012-01-08 13:15:03 +07:00
Alan Mishchenko 03f772d50a Backward reachability using circuit cofactoring. 2012-01-08 09:35:09 +07:00
Alan Mishchenko d1450e7733 Backward reachability using circuit cofactoring. 2012-01-07 21:12:27 +07:00
Alan Mishchenko c3ab7843bb Backward reachability using circuit cofactoring. 2012-01-07 21:04:36 +07:00
Alan Mishchenko 99cc6ae9d2 Crash fix in 'tempor' in case the leading length is 0. 2012-01-07 20:29:11 +07:00
Alan Mishchenko 36bc5703ad Gate level abstraction. 2012-01-07 12:11:25 +07:00
Alan Mishchenko 376bf3a703 Bug fix: changing output number to 0 in the CEX after ORing POs. 2012-01-07 11:19:03 +07:00
Alan Mishchenko 10ad89490a Bug fix related to not properly resizing SAT solver's model array. 2012-01-06 11:34:06 +07:00
Alan Mishchenko 26b87c8c55 Added warning when the network from file has no primary inputs. 2012-01-06 01:36:08 +07:00
Alan Mishchenko 5a45a75dca APIs to represent simple gates in CNF. 2012-01-05 19:19:13 +07:00
Alan Mishchenko fd62957d39 Backward reachability using circuit cofactoring. 2012-01-05 18:48:11 +07:00
Alan Mishchenko 32e7b75829 APIs to represent simple gates in CNF. 2012-01-05 13:15:05 +07:00
Alan Mishchenko 660779b53c Configuration changes in the Boolean matching code. 2012-01-05 13:14:04 +07:00
Alan Mishchenko e3a412b2e7 Backward reachability using circuit cofactoring. 2012-01-01 15:58:49 +07:00