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1369 Commits

Author SHA1 Message Date
Alan Mishchenko fdd043ca34 Upgrading hierarchy timing manager. 2012-09-21 22:00:39 -07:00
Alan Mishchenko c1f8baafb8 Added switch '-E <filename>' to 'read_library' to exclude gates listed while reading a Genlib file. 2012-09-21 12:23:23 -07:00
Alan Mishchenko b5306c1566 Added simplification before the concurrent call to PDR. 2012-09-20 20:13:40 -07:00
Alan Mishchenko 5f09917c22 Added simplification before the concurrent call to PDR. 2012-09-20 19:51:39 -07:00
Alan Mishchenko d21c0be44a Added slack computation to 'stime'. 2012-09-20 14:13:59 -07:00
Alan Mishchenko 266af49386 Modified 'read' to read all types of libraries (genlib, liberty, scl). 2012-09-20 13:12:51 -07:00
Alan Mishchenko bc44087bac Modified 'read' to read all types of libraries (genlib, liberty, scl). 2012-09-20 12:41:59 -07:00
Alan Mishchenko fdfb083c5c Added command 'minsize' to reduce all gates to their minimum size in the library. 2012-09-20 12:01:04 -07:00
Alan Mishchenko f59de3decc Fixes to Verilog parser. 2012-09-20 11:29:37 -07:00
Alan Mishchenko 723f85ef1b Extending Liberty parser to handle multi-output cells. 2012-09-19 20:21:27 -07:00
Alan Mishchenko 5dc50744f0 Extending Liberty parser to handle multi-output cells. 2012-09-19 18:42:00 -07:00
Alan Mishchenko 480ca14c75 Extending Liberty parser to handle multi-output cells. 2012-09-19 17:35:04 -07:00
Alan Mishchenko 3af0f719af Extending BLIF parser/write to hangle multi-output cells. 2012-09-19 16:28:06 -07:00
Alan Mishchenko 60c6614885 Extending Genlib to hangle multi-output cells. 2012-09-19 11:53:40 -07:00
Alan Mishchenko 48996f7a36 Changes to command 'upsize'. 2012-09-18 19:12:54 -07:00
Alan Mishchenko e0eb270324 Changes to command 'upsize'. 2012-09-18 13:23:58 -07:00
Alan Mishchenko 508b6f1b13 Fixing mismatch between declaration of the output value of Extra_CpuTime. 2012-09-18 09:58:06 -07:00
Alan Mishchenko 6dc3a0a246 Bug fix in bmc3. 2012-09-17 17:39:42 -07:00
Alan Mishchenko 1f9abfd7a8 Bug fix: no need to normalize const0 node. 2012-09-17 10:02:37 -07:00
Alan Mishchenko 819b41bb59 Fixed timeout problem in bmc3 -s. 2012-09-17 09:54:45 -07:00
Alan Mishchenko 790ea6545f Moving binary IO streams to the vector package. 2012-09-17 01:01:47 -07:00
Alan Mishchenko 7e843d64a9 Added delay multipliers to 'map'. 2012-09-16 23:34:56 -07:00
Alan Mishchenko 6d05fde2dc Added delay multipliers to 'map'. 2012-09-16 22:05:15 -07:00
Alan Mishchenko bbf4b8bc1e Improving printouts in 'stime'. 2012-09-16 21:40:20 -07:00
Alan Mishchenko 8b2b4fb6b8 Improving printouts in &gla. 2012-09-16 18:57:53 -07:00
Alan Mishchenko 9cbd97b5ef Improving printouts in &gla. 2012-09-16 16:50:18 -07:00
Alan Mishchenko c15137bd3f Improving printouts in &gla. 2012-09-16 16:48:50 -07:00
Alan Mishchenko ee436f9377 Changed a few things in the refinement package of &gla. 2012-09-16 13:56:10 -07:00
Alan Mishchenko 33cd4dea67 Forgot to add one file into Windows project. 2012-09-16 11:21:45 -07:00
Alan Mishchenko 5953beb2da Restructured the code to post-process object used during refinement in &gla. 2012-09-16 09:54:19 -07:00
Alan Mishchenko 5a4f1fe44c Made abstraction and PDR communicate in-memory rather than through a file. 2012-09-16 00:26:18 -07:00
Alan Mishchenko fdf5ad3433 Cleaned 'abc.c' by removing useless procedures. 2012-09-15 23:52:36 -07:00
Alan Mishchenko 69bbfa9856 Created new abstraction package from the code that was all over the place. 2012-09-15 23:27:46 -07:00
Alan Mishchenko ec95f569dd Corrected &gla -a to work as expected. 2012-09-15 21:18:32 -07:00
Alan Mishchenko 152aaedcb2 Prepared &gla to try abstracting and proving concurrently. 2012-09-14 22:45:51 -07:00
Alan Mishchenko 080c325500 Prepared &gla to try abstracting and proving concurrently. 2012-09-14 21:22:31 -07:00
Alan Mishchenko 117bc0dbcd Prepared &gla to try abstracting and proving concurrently. 2012-09-14 21:20:37 -07:00
Alan Mishchenko f64bb36fd5 Prepared &gla to try abstracting and proving concurrently. 2012-09-14 13:33:23 -07:00
Alan Mishchenko 3b14c7b490 Prepared &gla to try abstracting and proving concurrently. 2012-09-14 13:31:29 -07:00
Alan Mishchenko 19c28cae94 Prepared &gla to try abstracting and proving concurrently. 2012-09-14 10:27:48 -07:00
Alan Mishchenko 9b15f71f2f Added new command 'upsize'. 2012-09-12 14:39:50 -07:00
Alan Mishchenko e3d75484ce Reversed to a buggy version of reduceDB in complete proof-logging, because it works with rollback and it is not used in &gla -pn -L 0. 2012-09-12 12:46:56 -07:00
Alan Mishchenko 606341dca6 Added code to collect experimental results. 2012-09-11 22:36:38 -07:00
Alan Mishchenko e95844c0af Added code to collect experimental results. 2012-09-11 22:35:27 -07:00
Alan Mishchenko 087ec9eb1f Added code to collect experimental results. 2012-09-11 22:34:49 -07:00
Alan Mishchenko 825bcd823c Added code to collect experimental results. 2012-09-11 22:33:47 -07:00
Alan Mishchenko 4c06c8afc0 Improved topo print-out. 2012-09-11 19:40:12 -07:00
Alan Mishchenko a246882a5b Scalable gate-level abstraction. 2012-09-11 19:11:51 -07:00
Niklas Een 1c865bf229 Added -C to command line for running commands, then staying in interactive mode 2012-09-11 18:48:43 -07:00
Alan Mishchenko 784a3579e5 Fixing Verilog writer's way of writing module names. 2012-09-11 18:44:07 -07:00