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3,358 Commits 27 Branches 57 Tags 58 MiB
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680 Commits

Author SHA1 Message Date
Alan Mishchenko e9abb0f489 Adding code to support gate profiles. 2015-12-07 01:31:41 -08:00
Alan Mishchenko 0f29ba75f6 Adding commands to read/write/print gate profiles. 2015-12-05 18:10:43 -08:00
Alan Mishchenko f7c969ca66 Improvements to timing optimization. 2015-11-11 23:12:05 -08:00
Alan Mishchenko 3c9f7d2bc8 Extending and improving timing manager. 2015-11-08 19:59:34 -08:00
Alan Mishchenko efb8ad0af8 Extending and improving timing manager. 2015-11-08 12:08:50 -08:00
Alan Mishchenko 96d8f899d9 Extending and improving timing manager. 2015-11-08 11:44:37 -08:00
Baruch Sterin c0ba25a693 silence clang errors when compiling as C++ 2015-11-05 01:23:31 -08:00
Alan Mishchenko 8ee49ff150 Bug fix in constructing internal choices by 'amap'. 2015-11-04 15:15:18 -08:00
Alan Mishchenko 35143e830b Experiments with precomputation and matching. 2015-10-27 10:48:40 -07:00
Alan Mishchenko bd586dd355 Changes for delay-oriented computation. 2015-10-26 16:44:04 -07:00
Alan Mishchenko 9519341aaf Extending library handling to 8 inputs. 2015-10-25 20:23:44 -07:00
Alan Mishchenko 61d4623207 Adding switch in 'print_genlib' and 'write_genlib' to print area-min gates only. 2015-10-23 17:17:23 -07:00
Alan Mishchenko 3712dd30d0 Changes for delay-oriented computation. 2015-10-23 15:14:31 -07:00
Alan Mishchenko 2c37498bfb Compiler warnings. 2015-10-21 23:53:42 -07:00
Alan Mishchenko 0145b0ca72 Moving BDD-based threshold function detection to the BDD part of the code. 2015-10-16 18:34:06 -07:00
Alan Mishchenko 15a86aefd2 Experiments with precomputation and matching. 2015-10-15 15:32:36 -07:00
Alan Mishchenko 20c46b5a45 Experiments with precomputation and matching. 2015-10-12 18:29:15 -07:00
Alan Mishchenko 46223f903b Two fixes in 'dsd_filter'. 2015-10-07 17:48:07 -07:00
Alan Mishchenko b19d09f04c Bug fix in 'if -g' (incorrect use of a macro). 2015-10-07 08:37:25 -07:00
Alan Mishchenko 78951b4c6f Improvements to Scl_Lib/SC_Cell data-structure. 2015-09-24 12:12:36 -07:00
Alan Mishchenko f1bc346894 Several bug-fixed related to synthesis, library handling, and timimg info. 2015-09-23 18:44:07 -07:00
Alan Mishchenko 19a4bb930e Threshold logic checking code by Augusto Neutzling and Jody Matos. 2015-09-23 15:24:25 -07:00
Alan Mishchenko 97751e43b7 New constraint manager and memory reporting 'ps'. 2015-09-08 19:53:49 -07:00
Alan Mishchenko faeeaeb5e7 Updating Mio to use int instead of float. 2015-08-31 15:09:46 -07:00
Alan Mishchenko 4530ef6444 Alternative way to bit-blast a divisor. 2015-08-29 00:08:41 -07:00
Alan Mishchenko 04be8af560 Important bug fixes in standard-cell library handling and mapper &nf. 2015-08-28 17:47:00 -07:00
Alan Mishchenko 77d64787e0 Changes to be able to compile ABC without CUDD. 2015-08-24 19:49:18 -07:00
Alan Mishchenko 1fffe8f6f3 New switch in 'read_lib' to replace gate/pin names by short strings. 2015-08-24 18:07:10 -07:00
Alan Mishchenko 5bf0f86450 New switch in 'read_lib' to replace gate/pin names by short strings. 2015-08-24 17:40:20 -07:00
Alan Mishchenko 0e4561ab9f Experiments with mapping plus small changes. 2015-08-23 20:38:55 -07:00
Alan Mishchenko 10e0f3c58d Small changes to enable collecting results using &ps -D file. 2015-07-09 11:50:24 -07:00
Alan Mishchenko fd5b7e8b5d Bug fix in programmable cell parser and minor tuning. 2015-07-08 16:59:22 -07:00
Alan Mishchenko 609be7a114 C++ compiler typecast problem. 2015-07-08 15:04:26 -07:00
Alan Mishchenko 9894fc762e Add fix to Liberty parser to skip extra semicolon. 2015-07-06 07:57:18 -07:00
Alan Mishchenko b4d0abb77d Undo recent assert. 2015-06-27 21:38:32 -07:00
Alan Mishchenko 66ef4a9ac1 Potential performance bug in the mapper. 2015-06-27 19:57:49 -07:00
Alan Mishchenko d0d7763ef8 Supporting AND-gate cuts in 'if' and '&if' 2015-06-21 13:31:02 -07:00
Alan Mishchenko 14b7a520a1 Bug fix in 'dsd_tune' when processing cells with 0-input LUTs. 2015-05-15 22:36:11 -07:00
Alan Mishchenko 37b6b5f1f8 Making sure 0-input LUTs are supported by the DSD matching code. 2015-05-14 13:12:17 -07:00
Alan Mishchenko c0f0e145c4 Improving the criteria to select representative gates in 'map' with floating-point-delay libraries having more than one gate in some functionality classes. 2015-04-25 14:58:29 -07:00
Alan Mishchenko 9e20b3016d Adding switch 'map -f' to not use large gates for high-fanout nodes (disabled by default). 2015-04-24 14:51:34 -07:00
Alan Mishchenko a78fb767ee Adding platform-independent (alphabetic) way of sorting Genlib gates and selecting representatives based on area/delay. 2015-04-17 21:02:15 +09:00
Alan Mishchenko 3de5d18c5f Adding APIs to retrieve NOR/OR gates from the library. 2015-04-14 18:53:28 +09:00
Alan Mishchenko b3e5ccd256 Getting default AND-node delay from Genlib library. 2015-04-06 10:56:14 +07:00
Alan Mishchenko bb22a20cb0 Support for representing programmable cell configuration data (bug fix). 2015-03-09 08:36:22 -07:00
Alan Mishchenko 193c46e3c6 Support for representing programmable cell configuration data. 2015-03-08 20:19:56 -07:00
Alan Mishchenko 56f783157a Support for representing programmable cell configuration data. 2015-03-08 20:17:59 -07:00
Alan Mishchenko 6da21b8b88 Experiments with SAT-based cube enumeration. 2015-03-05 23:00:30 -08:00
Alan Mishchenko 874d394089 Corner case bug in wire-cap estimation. 2015-02-18 09:18:01 -08:00
Alan Mishchenko fd877c3f37 Several improvements to CBA data-structure. 2015-02-09 15:36:25 -08:00