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5296 Commits

Author SHA1 Message Date
aletempiac d223898f3d Merge remote-tracking branch 'origin/master' into acd 2024-01-16 17:44:45 +01:00
aletempiac 67aab70cff Moving ACD package to if folder 2024-01-16 17:42:43 +01:00
Alan Mishchenko 5bc99574fc Eliminating dependency on "abc.rc" in "&deepsyn". 2024-01-12 22:54:44 -08:00
aletempiac 38e632a954 Consider buffers in matrix covering as free 2024-01-12 14:50:34 +01:00
Alan Mishchenko 8c7327b8df Recognizing interface of the module when writing Verilog. 2024-01-11 22:19:50 -08:00
Alan Mishchenko dc68fe27f9 Saving module interface. 2024-01-11 19:45:42 -08:00
aletempiac 7dcc10a254 Minor fixes 2024-01-10 15:18:39 +01:00
alanminko 7f0a319564
Merge pull request #269 from rmlarsen/speedup_scanning 
Micro-optimizations to speed up the Liberty parser by ~1.67x.
 2023-12-21 12:58:42 +09:00
Alan Mishchenko 5978ccdb52 Updating sleep command to wait for file. 2023-12-21 12:16:33 +09:00
Rasmus Munk Larsen 706112ebd8 Micro-optimizations to speed up the Liberty parser by ~1.67x. 
Signed-off-by: Rasmus Munk Larsen <rmlarsen@google.com>
 2023-12-19 16:13:52 -08:00
Alan Mishchenko 7fe92148cc New command to put computation to sleep. 2023-12-18 21:04:31 +09:00
Alan Mishchenko 16a3c5fc30 Add copying names in &saveaig and &loadaig. 2023-12-09 21:53:48 +08:00
aletempiac b3d2419d9a Formatting, renaming, and cleaning code 2023-11-27 13:38:36 +01:00
aletempiac 6097fd4349 Code formatting 2023-11-24 14:24:20 +01:00
aletempiac 23cfcc1e1f Improving efficiency and removing useless code 2023-11-24 12:18:49 +01:00
aletempiac 43f4dccb4f run time improvements in computing the column multiplicity 2023-11-23 16:29:33 +01:00
aletempiac acdd08fd9b Performance improvements 2023-11-21 11:47:56 +01:00
aletempiac d10d450f38 Final implementation 2023-11-19 21:59:40 +01:00
aletempiac 219d6d86d6 Simplifying code 2023-11-19 19:33:19 +01:00
aletempiac 672fd1b629 removing not used methods 2023-11-19 18:53:54 +01:00
aletempiac f7a520b957 restructuring code 2023-11-19 18:51:50 +01:00
aletempiac 1d7dfd25c6 Improving ACD mapping 2023-11-17 16:58:17 +01:00
aletempiac 3d602e2f00 Adding sorting of columns in heuristic covering 2023-11-17 15:55:10 +01:00
aletempiac 1ca7a3a353 Remove symmetries in covering table 2023-11-17 15:49:29 +01:00
aletempiac b77bdeeb17 Enabling ACD for area 2023-11-16 19:21:29 +01:00
aletempiac 8aa57c5d54 Decisions on late arrival 2023-11-16 18:53:02 +01:00
aletempiac 548fd6afb2 New version of enumeration of combinations 2023-11-16 18:20:05 +01:00
aletempiac b32bbdfef3 Improving set covering using unitary cost 2023-11-16 15:33:19 +01:00
aletempiac dcc960beba Adding local search for covering 2023-11-15 21:57:29 +01:00
aletempiac c07080f818 Adding heuristic set covering solver 2023-11-15 21:32:34 +01:00
aletempiac 66cdd36d20 Runtime improvements in decomposition 2023-11-15 19:03:29 +01:00
aletempiac 1632dc0d4e First version of ACD 2023-11-15 18:38:00 +01:00
Alan Mishchenko 6ca7eab466 Prototype of integrating decomposition into "if". 2023-11-14 12:58:03 -08:00
Alan Mishchenko eb264c5d22 Suggested fixes. 2023-11-13 17:19:54 -08:00
Alan Mishchenko 04dba9eed9 Adding callback for wire caps during sizing. 2023-11-06 17:35:41 -08:00
Alan Mishchenko 5de12aa6b3 Experiments with SAT solving. 2023-10-23 11:30:44 -07:00
Alan Mishchenko 1bf21626c0 Bug fix. 2023-10-23 11:04:35 -07:00
Alan Mishchenko 76e8d21aaf Printout changes. 2023-10-23 10:48:43 -07:00
Alan Mishchenko 538ecb4515 Updating printouts. 2023-10-23 09:38:24 -07:00
Alan Mishchenko 01ad71b26f Experiments with verification. 2023-10-23 09:38:08 -07:00
Alan Mishchenko 8dbf8965fd Adding batch option to "scrgen". 2023-10-23 09:37:04 -07:00
Alan Mishchenko 652a0aaef7 Compiler warning. 2023-10-20 22:42:40 -07:00
Alan Mishchenko 72b423ba14 Experiments with SAT solving. 2023-10-20 20:53:43 -07:00
Alan Mishchenko 3c4c558656 Experiment with script generation. 2023-10-02 16:47:37 -07:00
Alan Mishchenko 65ccd3cc69 Enabled literal remapping. 2023-09-29 16:07:29 -07:00
Alan Mishchenko d971e3ecff Updating windows project file. 2023-09-28 07:17:42 -07:00
Alan Mishchenko cc636a0d83 Experiments with verification. 2023-09-28 06:40:57 -07:00
Alan Mishchenko 0f11580fce Experiments with retiming. 2023-09-24 22:18:45 +08:00
Alan Mishchenko 4d1618f600 Enable dumping Verilog with assign-statements. 2023-09-21 11:08:43 +08:00
Alan Mishchenko 73dac01c15 Warning regarding PathMatchSpec() on Windows. 2023-09-21 11:08:16 +08:00