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743 Commits 27 Branches 57 Tags 58 MiB
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743 Commits

Author SHA1 Message Date
Alan Mishchenko cb2d12bb04 New hierarchy manager. 2012-01-13 00:34:13 -08:00
Alan Mishchenko 2e1dcdd239 Added model ID inside the design. 2012-01-12 23:29:47 -08:00
Alan Mishchenko 56cc5734a4 Bug fix related to not properly resizing SAT solver's model array. 2012-01-12 07:28:01 -08:00
Alan Mishchenko fadde52dc6 Changes to the lazy man's synthesis code. 2012-01-11 22:08:35 -08:00
Alan Mishchenko 22ae2e452a Gate level abstraction. 2012-01-11 14:51:00 -08:00
Alan Mishchenko 564a3553f0 Gate level abstraction. 2012-01-08 13:15:03 +07:00
Alan Mishchenko 03f772d50a Backward reachability using circuit cofactoring. 2012-01-08 09:35:09 +07:00
Alan Mishchenko d1450e7733 Backward reachability using circuit cofactoring. 2012-01-07 21:12:27 +07:00
Alan Mishchenko c3ab7843bb Backward reachability using circuit cofactoring. 2012-01-07 21:04:36 +07:00
Alan Mishchenko 99cc6ae9d2 Crash fix in 'tempor' in case the leading length is 0. 2012-01-07 20:29:11 +07:00
Alan Mishchenko 36bc5703ad Gate level abstraction. 2012-01-07 12:11:25 +07:00
Alan Mishchenko 376bf3a703 Bug fix: changing output number to 0 in the CEX after ORing POs. 2012-01-07 11:19:03 +07:00
Alan Mishchenko 10ad89490a Bug fix related to not properly resizing SAT solver's model array. 2012-01-06 11:34:06 +07:00
Alan Mishchenko 26b87c8c55 Added warning when the network from file has no primary inputs. 2012-01-06 01:36:08 +07:00
Alan Mishchenko 5a45a75dca APIs to represent simple gates in CNF. 2012-01-05 19:19:13 +07:00
Alan Mishchenko fd62957d39 Backward reachability using circuit cofactoring. 2012-01-05 18:48:11 +07:00
Alan Mishchenko 32e7b75829 APIs to represent simple gates in CNF. 2012-01-05 13:15:05 +07:00
Alan Mishchenko 660779b53c Configuration changes in the Boolean matching code. 2012-01-05 13:14:04 +07:00
Alan Mishchenko e3a412b2e7 Backward reachability using circuit cofactoring. 2012-01-01 15:58:49 +07:00
Alan Mishchenko aec5d33889 Backward reachability using circuit cofactoring. 2012-01-01 15:58:17 +07:00
Alan Mishchenko 1e20e2ccbc Delay optimization using precomputed library. 2011-12-30 13:11:52 +07:00
Alan Mishchenko 655d452cbb Delay optimization using precomputed library. 2011-12-30 11:36:25 +07:00
Alan Mishchenko 6ed8340226 Delay optimization using precomputed library. 2011-12-30 11:27:12 +07:00
Alan Mishchenko 64b8aa51e9 Delay optimization using precomputed library. 2011-12-30 09:54:30 +07:00
Alan Mishchenko 6c19c1dfed Delay optimization using precomputed library. 2011-12-29 21:14:01 +07:00
Alan Mishchenko fce98abf43 Experiments with flattening hierarchy. 2011-12-29 10:27:46 +07:00
Alan Mishchenko ed13bd16fd New variable-time frame abstraction. 2011-12-29 10:13:25 +07:00
Alan Mishchenko 21df8bf021 Experiments with flattening hierarchy. 2011-12-28 22:16:04 +07:00
Alan Mishchenko afc8553f89 Experiments with flattening hierarchy. 2011-12-28 21:15:19 +07:00
Alan Mishchenko c59e2e9c96 Transforming the solver to use different clause representation. 2011-12-23 21:45:23 -08:00
Alan Mishchenko 7facbc3cc9 Transforming the solver to use different clause representation. 2011-12-23 10:23:45 -08:00
Alan Mishchenko 94174d0f04 Transforming the solver to use different clause representation. 2011-12-23 00:43:31 -08:00
Alan Mishchenko 9d2893040e Transforming the solver to use different clause representation. 2011-12-23 00:29:26 -08:00
Alan Mishchenko 844c385e2b Transforming the solver to use different clause representation. 2011-12-22 15:38:06 -08:00
Alan Mishchenko 1c51d9577d Added switch -n to 'miter' to ignore PI/PO names. 2011-12-22 14:55:10 -08:00
Alan Mishchenko 810c0be127 Added alias blif2aig = undc; strash; zero 2011-12-22 14:29:36 -08:00
Alan Mishchenko d0da3a8258 Computing interpolants as truth tables. 2011-12-22 14:26:47 -08:00
Alan Mishchenko 82a2495ce9 Improvements to hierarchical BLIF parser. 2011-12-22 14:26:03 -08:00
Alan Mishchenko b3c9609e82 Improvements to hierarchical BLIF parser. 2011-12-21 12:56:28 -08:00
Alan Mishchenko 3418a8820a Fixed a bug in matching code. 2011-12-17 17:51:13 -08:00
Alan Mishchenko cd4752b565 Added utility to sort lines in a file alphabetically. 2011-12-17 13:57:56 -08:00
Alan Mishchenko 024f9a2b13 Performance improvement in 'dch' for designs having nodes with many fanouts. 2011-12-15 19:32:53 -08:00
Alan Mishchenko f67cb76dff Added optional printout of the hierarchy structure before collapsing. 2011-12-15 19:32:05 -08:00
Alan Mishchenko 8404ecda54 Undoing temporary change to the solver. 2011-12-15 17:05:38 -08:00
Alan Mishchenko 4d000265f6 Temporary change to the solver. 2011-12-15 16:47:28 -08:00
Alan Mishchenko 4a7ef41db2 Adding switch '-W' to fx to control the quality of extracted divisors. 2011-12-15 15:46:32 -08:00
Alan Mishchenko 2bb95a97d0 Adding switch '-W' to fx to control the quality of extracted divisors. 2011-12-15 15:44:56 -08:00
Alan Mishchenko c80c0cc6c9 Trying to make sorting of nodes platform-indendent. 2011-12-15 13:39:16 -08:00
Alan Mishchenko 9608bcd1d8 Enabling balance again. 2011-12-15 13:39:03 -08:00
Alan Mishchenko 6531899709 Temporarily disabling balance. 2011-12-15 13:24:27 -08:00