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2,140 Commits 27 Branches 57 Tags 58 MiB
Commit Graph

106 Commits

Author SHA1 Message Date
Alan Mishchenko c62f380eff Debugging and finetuning the flow. 2013-09-17 16:59:22 -07:00
Alan Mishchenko a2d97cf2b6 Debugging and finetuning the flow. 2013-09-17 16:43:42 -07:00
Alan Mishchenko 73a997a8bd Adding commands to set and print timing constraints. 2013-09-17 14:47:34 -07:00
Alan Mishchenko 7d3976a763 Unifying standard cell library representations. 2013-09-17 13:16:20 -07:00
Alan Mishchenko 549fd2ed15 Infrastructure to support full Liberty format and unitification of library representations. 2013-09-15 18:31:02 -07:00
Alan Mishchenko 931e5882b1 Infrastructure to support full Liberty format and unitification of library representations. 2013-09-15 18:28:29 -07:00
Alan Mishchenko ff5d3591d1 Infrastructure to support full Liberty format and unitification of library representations. 2013-09-15 18:23:49 -07:00
Alan Mishchenko ae27704c13 Integrated buffering and sizing. 2013-08-11 11:35:22 -07:00
Alan Mishchenko ec4804aab6 Integrated buffering and sizing. 2013-08-11 00:49:34 -07:00
Alan Mishchenko 679a9a021a Integrated buffering and sizing. 2013-08-10 18:13:03 -07:00
Alan Mishchenko 6c4252c5c9 Integrated buffering and sizing. 2013-08-10 18:11:09 -07:00
Alan Mishchenko 55872bc302 Integrated buffering and sizing. 2013-08-10 11:36:23 -07:00
Alan Mishchenko 5d0ba30518 Bug fix in incremental timing. 2013-08-10 11:14:33 -07:00
Alan Mishchenko 573d6d7ab7 Enable wire load estimation in buffering/sizing. 2013-08-10 10:27:55 -07:00
Alan Mishchenko 118cb03be4 Integrated buffering and sizing. 2013-08-09 22:55:09 -07:00
Alan Mishchenko 6e2ee1d30a Integrated buffering and sizing. 2013-08-09 22:13:13 -07:00
Alan Mishchenko 4af5587cbf Integrated buffering and sizing. 2013-08-09 21:44:18 -07:00
Alan Mishchenko fbdaf2075f Integrated buffering and sizing. 2013-08-09 21:05:06 -07:00
Alan Mishchenko d4ad3b4156 Improvements to buffering and sizing. 2013-08-09 19:47:58 -07:00
Alan Mishchenko 633db0f4ad Improvements to buffering and sizing. 2013-08-09 17:54:18 -07:00
Alan Mishchenko b98345ced5 Improvements to buffering and sizing. 2013-08-09 12:36:48 -07:00
Alan Mishchenko 95684b044a Improvements to buffering and sizing. 2013-08-09 11:15:20 -07:00
Alan Mishchenko 4be8eba9d9 Compiler warnings. 2013-08-08 18:23:40 -07:00
Alan Mishchenko 881b2ec46f Integrated buffering and sizing. 2013-08-08 18:23:00 -07:00
Alan Mishchenko 655dc4e727 Improvements to buffering and sizing. 2013-08-07 12:32:33 -07:00
Alan Mishchenko 8576e4b440 Improvements to buffering and sizing. 2013-08-06 22:51:39 -07:00
Alan Mishchenko 7a6f335ea6 Improvements to buffering and sizing. 2013-08-06 12:22:13 -07:00
Alan Mishchenko 51714ef65d Adding new (un)buffering with phase information. 2013-08-05 19:21:10 -07:00
Alan Mishchenko 1a55882ad9 Adding new (un)buffering with phase information. 2013-08-05 18:33:38 -07:00
Alan Mishchenko 1558fe6110 Adding code to estimate buffer trees. 2013-08-05 10:45:06 -07:00
Alan Mishchenko 9d19598162 Change from input slew to input drive strength in the BLIF file. 2013-08-04 12:19:24 -07:00
Alan Mishchenko 56a233be91 Adding switch 'buffer -p' to enable buffing of the primary inputs. 2013-08-02 23:23:45 -07:00
Alan Mishchenko 710fd8e1ea Internal parameter tuning. 2013-07-31 14:52:59 -07:00
Alan Mishchenko 8e54792cd0 Added commands 'maxsize' and 'unbuffer'. 2013-07-29 22:24:54 -07:00
Alan Mishchenko f09a704250 Added commands 'maxsize' and 'unbuffer'. 2013-07-29 21:01:05 -07:00
Alan Mishchenko b93ead2ad1 Compiler warning. 2013-07-29 19:14:34 -07:00
Alan Mishchenko 1dca7458f3 Improved buffering. 2013-07-29 18:55:13 -07:00
Alan Mishchenko 4c6804c3ae Improved gate-sizing. 2013-07-29 10:10:21 -07:00
Alan Mishchenko 00d023713b Tuning standard-cell mapping flow. 2013-07-24 09:54:53 -07:00
Alan Mishchenko fadcef9eb9 Tuning standard-cell mapping flow. 2013-07-23 18:02:17 -07:00
Alan Mishchenko 606eaafa48 Tuning standard-cell mapping flow. 2013-07-23 16:17:41 -07:00
Alan Mishchenko 84c0b9d69b Tuning standard-cell mapping flow. 2013-07-23 16:15:03 -07:00
Alan Mishchenko 038f296453 Bug fix and warning print. 2013-07-22 23:11:04 -07:00
Alan Mishchenko f392645daf Generating GENLIB library from SCL. 2013-07-22 13:25:51 -07:00
Alan Mishchenko fd28deefc7 Restructuring gate-sizing code trying to separate timing analysis. 2013-07-21 17:55:15 -07:00
Alan Mishchenko 1bdb3773f9 New technology mapper. 2013-07-21 16:36:15 -07:00
Alan Mishchenko a9afe7e8b7 Improvements to post-mapping re-sizing. 2013-07-21 14:56:30 -07:00
Alan Mishchenko 1ed823c67d Adding support for input slew and output capacitance to timer and gate-sizer. 2013-07-21 01:01:53 -07:00
Alan Mishchenko f917de3498 Improvements to the SCL package. 2013-07-20 23:19:28 -07:00
Alan Mishchenko 56592b28c2 Added command 'dnsize' to complement command 'upsize'. 2013-07-20 19:11:29 -07:00