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Enable wire load estimation in buffering/sizing.

This commit is contained in:
Alan Mishchenko 2013-08-10 10:27:55 -07:00
parent 118cb03be4
commit 573d6d7ab7
6 changed files with 46 additions and 38 deletions
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9
src/map/scl/scl.c
View File

@ -715,10 +715,11 @@ int Scl_CommandBufSize( Abc_Frame_t * pAbc, int argc, char ** argv )
pPars->fSizeOnly = 0;
pPars->fAddBufs = 0;
pPars->fBufPis = 0;
pPars->fUseWireLoads = 1;
pPars->fVerbose = 0;
pPars->fVeryVerbose = 0;
Extra_UtilGetoptReset();
while ( ( c = Extra_UtilGetopt( argc, argv, "GSNsbpvwh" ) ) != EOF )
while ( ( c = Extra_UtilGetopt( argc, argv, "GSNsbpcvwh" ) ) != EOF )
{
switch ( c )
{
@ -764,6 +765,9 @@ int Scl_CommandBufSize( Abc_Frame_t * pAbc, int argc, char ** argv )
case 'p':
pPars->fBufPis ^= 1;
break;
case 'c':
pPars->fUseWireLoads ^= 1;
break;
case 'v':
pPars->fVerbose ^= 1;
break;
@ -804,7 +808,7 @@ int Scl_CommandBufSize( Abc_Frame_t * pAbc, int argc, char ** argv )
return 0;
usage:
fprintf( pAbc->Err, "usage: bufsize [-GSM num] [-sbpvwh]\n" );
fprintf( pAbc->Err, "usage: bufsize [-GSM num] [-sbpcvwh]\n" );
fprintf( pAbc->Err, "\t performs buffering and sizing and mapped network\n" );
fprintf( pAbc->Err, "\t-G <num> : target gain percentage [default = %d]\n", pPars->GainRatio );
fprintf( pAbc->Err, "\t-S <num> : target slew in pisoseconds [default = %d]\n", pPars->Slew );
@ -812,6 +816,7 @@ usage:
fprintf( pAbc->Err, "\t-s : toggle performing only sizing [default = %s]\n", pPars->fSizeOnly? "yes": "no" );
fprintf( pAbc->Err, "\t-b : toggle using buffers instead of inverters [default = %s]\n", pPars->fAddBufs? "yes": "no" );
fprintf( pAbc->Err, "\t-p : toggle buffering primary inputs [default = %s]\n", pPars->fBufPis? "yes": "no" );
fprintf( pAbc->Err, "\t-c : toggle using wire-loads if specified [default = %s]\n", pPars->fUseWireLoads? "yes": "no" );
fprintf( pAbc->Err, "\t-v : toggle printing verbose information [default = %s]\n", pPars->fVerbose? "yes": "no" );
fprintf( pAbc->Err, "\t-w : toggle printing more verbose information [default = %s]\n", pPars->fVeryVerbose? "yes": "no" );
fprintf( pAbc->Err, "\t-h : print the command usage\n");

50
src/map/scl/sclBufSize.c
View File

@ -32,15 +32,17 @@ typedef struct Bus_Man_t_ Bus_Man_t;
struct Bus_Man_t_
{
// user data
SC_BusPars * pPars; // parameters
Abc_Ntk_t * pNtk; // user's network
SC_BusPars * pPars; // parameters
Abc_Ntk_t * pNtk; // user's network
// library
SC_Lib * pLib; // cell library
SC_Cell * pInv; // base interter (largest/average/???)
SC_Lib * pLib; // cell library
SC_Cell * pInv; // base interter (largest/average/???)
SC_WireLoad * pWLoadUsed; // name of the used WireLoad model
Vec_Flt_t * vWireCaps; // estimated wire loads
// internal
Vec_Flt_t * vCins; // input cap for fanouts
Vec_Flt_t * vLoads; // loads for all nodes
Vec_Flt_t * vDepts; // departure times
Vec_Flt_t * vCins; // input cap for fanouts
Vec_Flt_t * vLoads; // loads for all nodes
Vec_Flt_t * vDepts; // departure times
};
@ -75,6 +77,17 @@ Bus_Man_t * Bus_ManStart( Abc_Ntk_t * pNtk, SC_Lib * pLib, SC_BusPars * pPars )
p->pNtk = pNtk;
p->pLib = pLib;
p->pInv = Abc_SclFindInvertor(pLib, pPars->fAddBufs)->pAve;
if ( pPars->fUseWireLoads )
{
if ( pNtk->pWLoadUsed == NULL )
{
p->pWLoadUsed = Abc_SclFindWireLoadModel( pLib, Abc_SclGetTotalArea(pNtk) );
pNtk->pWLoadUsed = Abc_UtilStrsav( p->pWLoadUsed->pName );
}
else
p->pWLoadUsed = Abc_SclFetchWireLoadModel( pLib, pNtk->pWLoadUsed );
}
p->vWireCaps = Abc_SclFindWireCaps( p->pWLoadUsed );
p->vCins = Vec_FltStart( 2*Abc_NtkObjNumMax(pNtk) );
p->vLoads = Vec_FltStart( 2*Abc_NtkObjNumMax(pNtk) );
p->vDepts = Vec_FltStart( 2*Abc_NtkObjNumMax(pNtk) );
@ -83,6 +96,7 @@ Bus_Man_t * Bus_ManStart( Abc_Ntk_t * pNtk, SC_Lib * pLib, SC_BusPars * pPars )
}
void Bus_ManStop( Bus_Man_t * p )
{
Vec_FltFree( p->vWireCaps );
Vec_FltFree( p->vCins );
Vec_FltFree( p->vLoads );
Vec_FltFree( p->vDepts );
@ -165,7 +179,7 @@ void Abc_NtkComputeFanoutCins( Abc_Obj_t * pObj )
Bus_SclObjSetCin( pFanout, cap );
}
}
float Abc_NtkComputeNodeLoad( Abc_Obj_t * pObj )
float Abc_NtkComputeNodeLoad( Bus_Man_t * p, Abc_Obj_t * pObj )
{
Abc_Obj_t * pFanout;
float Load = 0;
@ -173,6 +187,7 @@ float Abc_NtkComputeNodeLoad( Abc_Obj_t * pObj )
assert( Bus_SclObjLoad(pObj) == 0 );
Abc_ObjForEachFanout( pObj, pFanout, i )
Load += Bus_SclObjCin( pFanout );
Load += Abc_SclFindWireLoad( p->vWireCaps, pObj );
Bus_SclObjSetLoad( pObj, Load );
return Load;
}
@ -195,21 +210,6 @@ float Abc_NtkComputeNodeDept( Abc_Obj_t * pObj, float Slew )
}
return Bus_SclObjDept( pObj );
}
/*
void Abc_NtkUpdateFaninDeparture( Bus_Man_t * p, Abc_Obj_t * pObj, float Load )
{
SC_Cell * pCell = Abc_SclObjCell( pObj );
Abc_Obj_t * pFanin;
float Dept, Edge;
int i;
Dept = Bus_SclObjDept( pObj );
Abc_ObjForEachFanin( pObj, pFanin, i )
{
Edge = Scl_LibPinArrivalEstimate( pCell, i, Load );
Bus_SclObjUpdateDept( pFanin, Dept + Edge );
}
}
*/
/**Function*************************************************************
@ -301,7 +301,7 @@ Abc_Obj_t * Abc_SclAddOneInv( Bus_Man_t * p, Abc_Obj_t * pObj, Vec_Ptr_t * vFano
Vec_IntSetEntry( p->pNtk->vGates, Abc_ObjId(pInv), pCellNew->Id );
Bus_SclObjSetCin( pInv, SC_CellPinCap(pCellNew, 0) );
// update timing
Abc_NtkComputeNodeLoad( pInv );
Abc_NtkComputeNodeLoad( p, pInv );
Abc_NtkComputeNodeDept( pInv, p->pPars->Slew );
// update phases
if ( p->pNtk->vPhases && Abc_SclIsInv(pInv) )
@ -323,7 +323,7 @@ void Abc_SclBufSize( Bus_Man_t * p )
{
// compute load
Abc_NtkComputeFanoutCins( pObj );
Load = Abc_NtkComputeNodeLoad( pObj );
Load = Abc_NtkComputeNodeLoad( p, pObj );
// consider the gate
pCell = Abc_SclObjCell( pObj );
Cin = SC_CellPinCapAve( pCell->pAve );

1
src/map/scl/sclLib.h
View File

@ -95,6 +95,7 @@ struct SC_BusPars_
int fSizeOnly; // perform only sizing
int fAddBufs; // add buffers
int fBufPis; // use CI buffering
int fUseWireLoads; // wire loads
int fVerbose; // verbose
int fVeryVerbose; // verbose
};

12
src/map/scl/sclLoad.c
View File

@ -42,7 +42,7 @@ ABC_NAMESPACE_IMPL_START
SeeAlso []
***********************************************************************/
Vec_Flt_t * Abc_SclFindWireCaps( SC_Man * p, SC_WireLoad * pWL )
Vec_Flt_t * Abc_SclFindWireCaps( SC_WireLoad * pWL )
{
Vec_Flt_t * vCaps = NULL;
float EntryPrev, EntryCur;
@ -79,14 +79,14 @@ Vec_Flt_t * Abc_SclFindWireCaps( SC_Man * p, SC_WireLoad * pWL )
SeeAlso []
***********************************************************************/
static inline float Abc_SclFindWireLoad( SC_Man * p, Abc_Obj_t * pObj )
float Abc_SclFindWireLoad( Vec_Flt_t * vWireCaps, Abc_Obj_t * pObj )
{
int nFans = Abc_MinInt( Vec_FltSize(p->vWireCaps)-1, Abc_ObjFanoutNum(pObj) );
return p->vWireCaps ? Vec_FltEntry(p->vWireCaps, nFans) : 0;
int nFans = Abc_MinInt( Vec_FltSize(vWireCaps)-1, Abc_ObjFanoutNum(pObj) );
return vWireCaps ? Vec_FltEntry(vWireCaps, nFans) : 0;
}
void Abc_SclAddWireLoad( SC_Man * p, Abc_Obj_t * pObj, int fSubtr )
{
float Load = Abc_SclFindWireLoad( p, pObj );
float Load = Abc_SclFindWireLoad( p->vWireCaps, pObj );
Abc_SclObjLoad(p, pObj)->rise += fSubtr ? -Load : Load;
Abc_SclObjLoad(p, pObj)->fall += fSubtr ? -Load : Load;
}
@ -125,7 +125,7 @@ void Abc_SclComputeLoad( SC_Man * p )
if ( p->pWLoadUsed != NULL )
{
if ( p->vWireCaps == NULL )
p->vWireCaps = Abc_SclFindWireCaps( p, p->pWLoadUsed );
p->vWireCaps = Abc_SclFindWireCaps( p->pWLoadUsed );
Abc_NtkForEachNode1( p->pNtk, pObj, i )
Abc_SclAddWireLoad( p, pObj, 0 );
Abc_NtkForEachPi( p->pNtk, pObj, i )

6
src/map/scl/sclSize.c
View File

@ -136,7 +136,7 @@ void Abc_SclTimeNtkPrint( SC_Man * p, int fShowAll, int fPrintPath )
printf( "Gates = %6d ", Abc_NtkNodeNum(p->pNtk) );
printf( "Cave = %5.1f ", p->EstLoadAve );
printf( "Min = %5.1f %% ", 100.0 * Abc_SclCountMinSize(p->pLib, p->pNtk, 0) / Abc_NtkNodeNum(p->pNtk) );
printf( "Area = %12.2f ", Abc_SclGetTotalArea( p ) );
printf( "Area = %12.2f ", Abc_SclGetTotalArea(p->pNtk) );
printf( "Delay = %8.2f ps ", maxDelay );
printf( "Min = %5.1f %% ", 100.0 * Abc_SclCountNearCriticalNodes(p) / Abc_NtkNodeNum(p->pNtk) );
printf( " \n" );
@ -324,7 +324,7 @@ void Abc_SclTimeNtkRecompute( SC_Man * p, float * pArea, float * pDelay, int fRe
if ( fReverse && DUser > 0 && D < DUser )
D = DUser;
if ( pArea )
*pArea = Abc_SclGetTotalArea( p );
*pArea = Abc_SclGetTotalArea(p->pNtk);
if ( pDelay )
*pDelay = D;
if ( fReverse )
@ -600,7 +600,7 @@ SC_Man * Abc_SclManStart( SC_Lib * pLib, Abc_Ntk_t * pNtk, int fUseWireLoads, in
{
if ( pNtk->pWLoadUsed == NULL )
{
p->pWLoadUsed = Abc_SclFindWireLoadModel( pLib, Abc_SclGetTotalArea(p) );
p->pWLoadUsed = Abc_SclFindWireLoadModel( pLib, Abc_SclGetTotalArea(p->pNtk) );
pNtk->pWLoadUsed = Abc_UtilStrsav( p->pWLoadUsed->pName );
}
else

6
src/map/scl/sclSize.h
View File

@ -400,12 +400,12 @@ static inline void Abc_SclConeClean( SC_Man * p, Vec_Int_t * vCone )
SeeAlso []
***********************************************************************/
static inline float Abc_SclGetTotalArea( SC_Man * p )
static inline float Abc_SclGetTotalArea( Abc_Ntk_t * pNtk )
{
double Area = 0;
Abc_Obj_t * pObj;
int i;
Abc_NtkForEachNode1( p->pNtk, pObj, i )
Abc_NtkForEachNode1( pNtk, pObj, i )
Area += Abc_SclObjCell(pObj)->area;
return Area;
}
@ -508,6 +508,8 @@ extern Abc_Ntk_t * Abc_SclBufPerform( Abc_Ntk_t * pNtk, int FanMin, int FanMax
/*=== sclDnsize.c ===============================================================*/
extern void Abc_SclDnsizePerform( SC_Lib * pLib, Abc_Ntk_t * pNtk, SC_SizePars * pPars );
/*=== sclLoad.c ===============================================================*/
extern Vec_Flt_t * Abc_SclFindWireCaps( SC_WireLoad * pWL );
extern float Abc_SclFindWireLoad( Vec_Flt_t * vWireCaps, Abc_Obj_t * pObj );
extern void Abc_SclAddWireLoad( SC_Man * p, Abc_Obj_t * pObj, int fSubtr );
extern void Abc_SclComputeLoad( SC_Man * p );
extern void Abc_SclUpdateLoad( SC_Man * p, Abc_Obj_t * pObj, SC_Cell * pOld, SC_Cell * pNew );