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505 Commits

Author SHA1 Message Date
Alan Mishchenko ac7e665bf6 Bug fixes in the Verilog parser. 2012-01-14 22:21:23 -08:00
Alan Mishchenko c7e215ca31 New hierarchy manager. 2012-01-14 18:05:12 -08:00
Alan Mishchenko 9c409addca Support computation experiments with different network data-structures. 2012-01-14 18:04:47 -08:00
Alan Mishchenko 7a3c33e169 New hierarchy manager. 2012-01-13 22:49:08 -08:00
Alan Mishchenko 5fff8354ce New hierarchy manager. 2012-01-13 22:02:04 -08:00
Alan Mishchenko b7ba9aa8dc New hierarchy manager. 2012-01-13 20:58:28 -08:00
Alan Mishchenko 4bd7efa6cd Added counting hits and misses during structural hashing. 2012-01-13 19:31:13 -08:00
Alan Mishchenko edbff75fff New hierarchy manager. 2012-01-13 18:10:00 -08:00
Alan Mishchenko eecbbea24b New hierarchy manager. 2012-01-13 17:50:21 -08:00
Alan Mishchenko 095345fc4a Added new name manager and modified hierarchy manager to use it. 2012-01-13 15:43:09 -08:00
Alan Mishchenko cb2d12bb04 New hierarchy manager. 2012-01-13 00:34:13 -08:00
Alan Mishchenko 2e1dcdd239 Added model ID inside the design. 2012-01-12 23:29:47 -08:00
Alan Mishchenko fadde52dc6 Changes to the lazy man's synthesis code. 2012-01-11 22:08:35 -08:00
Alan Mishchenko 564a3553f0 Gate level abstraction. 2012-01-08 13:15:03 +07:00
Alan Mishchenko 376bf3a703 Bug fix: changing output number to 0 in the CEX after ORing POs. 2012-01-07 11:19:03 +07:00
Alan Mishchenko 26b87c8c55 Added warning when the network from file has no primary inputs. 2012-01-06 01:36:08 +07:00
Alan Mishchenko aec5d33889 Backward reachability using circuit cofactoring. 2012-01-01 15:58:17 +07:00
Alan Mishchenko 1e20e2ccbc Delay optimization using precomputed library. 2011-12-30 13:11:52 +07:00
Alan Mishchenko 655d452cbb Delay optimization using precomputed library. 2011-12-30 11:36:25 +07:00
Alan Mishchenko 6ed8340226 Delay optimization using precomputed library. 2011-12-30 11:27:12 +07:00
Alan Mishchenko 64b8aa51e9 Delay optimization using precomputed library. 2011-12-30 09:54:30 +07:00
Alan Mishchenko 6c19c1dfed Delay optimization using precomputed library. 2011-12-29 21:14:01 +07:00
Alan Mishchenko ed13bd16fd New variable-time frame abstraction. 2011-12-29 10:13:25 +07:00
Alan Mishchenko 21df8bf021 Experiments with flattening hierarchy. 2011-12-28 22:16:04 +07:00
Alan Mishchenko 1c51d9577d Added switch -n to 'miter' to ignore PI/PO names. 2011-12-22 14:55:10 -08:00
Alan Mishchenko d0da3a8258 Computing interpolants as truth tables. 2011-12-22 14:26:47 -08:00
Alan Mishchenko 82a2495ce9 Improvements to hierarchical BLIF parser. 2011-12-22 14:26:03 -08:00
Alan Mishchenko b3c9609e82 Improvements to hierarchical BLIF parser. 2011-12-21 12:56:28 -08:00
Alan Mishchenko 3418a8820a Fixed a bug in matching code. 2011-12-17 17:51:13 -08:00
Alan Mishchenko f67cb76dff Added optional printout of the hierarchy structure before collapsing. 2011-12-15 19:32:05 -08:00
Alan Mishchenko 2bb95a97d0 Adding switch '-W' to fx to control the quality of extracted divisors. 2011-12-15 15:44:56 -08:00
Alan Mishchenko b63b332bac Trying to make sorting of nodes platform-indendent. 2011-12-15 12:42:42 -08:00
Alan Mishchenko 40ddda3edd Trying to make sorting of nodes platform-indendent. 2011-12-15 12:27:35 -08:00
Alan Mishchenko bc2f199bd3 Started SAT-based reparameterization. 2011-12-13 23:38:41 -08:00
Alan Mishchenko 8fdc5d220f g++ portability changes. 2011-12-13 12:17:03 -08:00
Alan Mishchenko 23af7f9036 Added command &read_blif to read hierarchical BLIF directly into the &-space. 2011-12-12 19:10:33 -08:00
Alan Mishchenko be874a7abe Added command &read_blif to read hierarchical BLIF directly into the &-space. 2011-12-12 18:43:49 -08:00
Alan Mishchenko ed4f4adeee Added the hierarchy printout. 2011-12-11 17:29:25 -08:00
Alan Mishchenko eb35f0ef65 Added support for generating a library of real-life truth-tables. 2011-12-09 01:05:18 -08:00
Alan Mishchenko beb29257bf Added support for generating a library of real-life truth-tables. 2011-12-09 00:38:16 -08:00
Alan Mishchenko 200c5cc659 Added support for generating a library of real-life truth-tables. 2011-12-09 00:37:05 -08:00
Alan Mishchenko 07405ca1c5 Integrated new proof-logging into proof-based gate-level abstraction. 2011-12-08 22:42:50 -08:00
Alan Mishchenko e84dcb7862 g++ portability changes. 2011-12-06 16:06:59 -08:00
Alan Mishchenko ef37d14bc6 Added recording of AIG subgraphs. 2011-12-06 15:37:09 -08:00
Alan Mishchenko f95e73c40b Added recording of AIG subgraphs. 2011-12-06 14:29:32 -08:00
Alan Mishchenko 0f8b68aef8 Performance bug fix in SOP balancing. 2011-12-06 13:15:53 -08:00
Alan Mishchenko 360c705fc4 Added recording of AIG subgraphs. 2011-12-06 12:42:00 -08:00
Alan Mishchenko d2db956a61 Started experiments with a new solver. 2011-11-25 18:08:48 -08:00
Alan Mishchenko 0a5d856cec Making GLA PBA and GLA CBA communicate information. 2011-11-22 19:07:00 -08:00
Alan Mishchenko 30ea50a3b4 Temporary debugging change. 2011-11-12 23:21:41 -08:00