luke
/
abc
mirror of https://github.com/YosysHQ/abc.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity
3,397 Commits 27 Branches 57 Tags 58 MiB
Commit Graph

3397 Commits

Author SHA1 Message Date
Alan Mishchenko 8bcf8fd3c9 Supporting X-valued constants in Wlc_Ntk_t. 2016-02-02 16:40:29 -08:00
Alan Mishchenko 094c68f921 Supporting X-valued constants in Wlc_Ntk_t. 2016-02-02 16:20:19 -08:00
Alan Mishchenko c81b6cb515 Supporting X-valued constants in Wlc_Ntk_t. 2016-02-02 15:43:19 -08:00
Alan Mishchenko 02725c9eca An add-on to write Verilog for circuits mapped into simple gates. 2016-02-01 15:56:53 -08:00
Alan Mishchenko 81dade194e Rare bug fix in 'dch' resulting in choice nodes having internal fanout. 2016-01-31 16:38:49 -08:00
Alan Mishchenko 367b20f04d Fixing mismatch in the TLS flow induced by adding cell configs in the DSD manager. 2016-01-30 20:59:57 -08:00
Alan Mishchenko 951ca48b9c Small changes to sort for timing. 2016-01-24 15:32:12 -08:00
Alan Mishchenko 9ef447658e Bug fix in 'aig', for the case of non-min-base SOPs. 2016-01-20 15:01:53 -08:00
Alan Mishchenko df34a26216 Generating sorting network as a PLA file. 2016-01-20 15:01:27 -08:00
Alan Mishchenko f5ee46eb3c New command to dump LUT network. 2016-01-16 17:35:46 -08:00
Alan Mishchenko 579bcccc65 Changing the resource file to get rid of a warning on Linux. 2016-01-14 21:34:47 -08:00
Alan Mishchenko 334f4a29ca Compiler warning. 2016-01-14 20:44:45 -08:00
Alan Mishchenko c4446189a9 Changes to PDR to compute f-inf clauses and import invariant (or clauses) as a network. 2016-01-14 20:42:22 -08:00
Alan Mishchenko f30facfec8 Experiments with SAT-based mapping. 2016-01-14 14:03:53 -08:00
Alan Mishchenko 4ecf43f1f0 Adding a way to derive cardinality constraint as a sorting network. 2016-01-13 20:32:26 -08:00
Alan Mishchenko 87f6828d50 Adding support for delay/area tradeoff. 2016-01-13 12:13:54 -08:00
Alan Mishchenko 8dd31fb4a9 Integrating new CNF generation into &bmc. 2016-01-12 22:07:01 -08:00
Alan Mishchenko de695c9d4c Better print-out of SOPs. Changing default of 'fx'. Updating 'satclp' to fine prine SOPs. 2016-01-12 11:55:50 -08:00
Alan Mishchenko 7984628d7f Experiments with SAT-based mapping. 2016-01-10 21:06:04 -08:00
Alan Mishchenko 1bbf239843 Experiments with SAT-based mapping. 2016-01-10 21:04:17 -08:00
Alan Mishchenko d6178631be Adding support of candinality clause to the SAT solver. 2016-01-10 10:19:26 -08:00
Alan Mishchenko a4f9776388 Consolidating timing manager Scl_Con_t and propagating changes. 2016-01-07 16:50:01 -08:00
Alan Mishchenko 15a891f97a Bug fix in constraint file reader. 2016-01-07 11:57:16 -08:00
Alan Mishchenko 5453820cd5 Adding switch &miter -x for XORs outputs of two word-level POs. 2016-01-06 16:50:42 -08:00
Alan Mishchenko 3240abdb63 Fixing last-minute bug fix in &nf. 2016-01-05 22:35:44 -08:00
Alan Mishchenko b9e71bba0c Buf fix in floating time reporting. 2016-01-05 19:45:07 -08:00
Alan Mishchenko 7bf3f5e186 Fix in &nf for the case when PO can be driven by an inverter. 2016-01-05 19:25:46 -08:00
Alan Mishchenko 30d09e2cbe Fix in &nf for the case when PO can be driven by an inverter. 2016-01-05 18:40:38 -08:00
Alan Mishchenko c158dd5a94 Migrating to using 32-bit timing representation in &nf. 2016-01-05 16:40:00 -08:00
Alan Mishchenko 19ad75f125 Migrating back to using 'float' in area-flow computation in &nf. 2016-01-05 14:05:07 -08:00
Alan Mishchenko 6642e40af5 Corner-case bug in 'read_profile'. 2015-12-22 22:09:25 -10:00
Alan Mishchenko 68bc46be0e Adding names to GIA inputs/outputs (addressing x-valued flops). 2015-12-22 14:58:04 -10:00
Alan Mishchenko 617055f5a2 Adding names to GIA inputs/outputs. Changing polarity of invariant generated by PDR. 2015-12-22 06:39:13 -10:00
Alan Mishchenko 2e8543fca1 Adding names to GIA inputs/outputs. Changing polarity of invariant generated by PDR. 2015-12-21 23:22:17 -10:00
Alan Mishchenko 1228e26cc3 Adding names to GIA inputs/outputs. Changing polarity of invariant generated by PDR. 2015-12-21 23:21:16 -10:00
Alan Mishchenko ba5e69952d Corner-case bug in invariant profiling. 2015-12-18 12:25:24 -10:00
Alan Mishchenko 54269c7cec Compiler warning. 2015-12-16 09:18:56 -10:00
Alan Mishchenko 09a17b89fe Branch merge. 2015-12-14 00:49:37 -08:00
Alan Mishchenko 19586f105c Adding code to support gate profiles. 2015-12-14 00:44:33 -08:00
Alan Mishchenko e8f459d85f Extending Verilog parser to handle 'default' in the case-statement (bug fix). 2015-12-07 22:56:29 -08:00
Alan Mishchenko 64afe6e9f8 Extending Verilog parser to handle 'default' in the case-statement. 2015-12-07 16:17:17 -08:00
Alan Mishchenko e9abb0f489 Adding code to support gate profiles. 2015-12-07 01:31:41 -08:00
Alan Mishchenko 0f29ba75f6 Adding commands to read/write/print gate profiles. 2015-12-05 18:10:43 -08:00
Alan Mishchenko 56880eab52 New command %psinv. 2015-11-23 23:42:20 +07:00
Baruch Sterin 63fcf25aea add a new #define ABC_NAMESPACE_USING_NAMESPACE that adds a using decelaration when needed 2015-11-20 21:07:01 -08:00
Baruch Sterin 11581ca9ee move namespace logic into a separate file. It is useful for users of ABC that need to use symbols without the entire baggage of including abc_global.h 2015-11-20 21:06:23 -08:00
Baruch Sterin 5df0cf98e6 main: add option -Q for execute command quietly, then interactive 2015-11-18 16:32:39 -08:00
Baruch Sterin 2ac47fe584 CMake: make it possible to pass ABC_USE_NAMESPACE=FALSE, instead of just empty ABC_USE_NAMESPACE 2015-11-13 03:42:12 -08:00
Baruch Sterin 3237ebafaa CMake, Makefile: pass the location of arch_flags to the makefile, this way the cmake build does not write to the soruce directory 2015-11-12 11:43:59 -08:00
Alan Mishchenko f7c969ca66 Improvements to timing optimization. 2015-11-11 23:12:05 -08:00