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Extending Verilog parser to handle 'default' in the case-statement (bug fix).

This commit is contained in:
Alan Mishchenko 2015-12-07 22:56:29 -08:00
parent 64afe6e9f8
commit e8f459d85f
1 changed files with 4 additions and 1 deletions
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5
src/base/wlc/wlcReadVer.c
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@ -1085,7 +1085,10 @@ startword:
if ( fDefaultFound )
{
int EntryLast = Vec_IntEntryLast( p->vFanins );
Vec_IntFillExtra( p->vFanins, nValues + 1, EntryLast );
if (nValues != Vec_IntSize(p->vFanins)-2)
Vec_IntFillExtra( p->vFanins, nValues + 1, EntryLast );
else
Vec_IntPop(p->vFanins);
// get next line and check its opening character
pStart = Wlc_PrsStr(p, Vec_IntEntry(p->vStarts, ++i));
pStart = Wlc_PrsSkipSpaces( pStart );