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3,086 Commits 30 Branches 59 Tags
85b33df1e133b478ee5d1cd28bc9e055e8f62cf0
Commit Graph
243 Commits
Author SHA1 Message Date
Alan Mishchenko 85b33df1e1 Improvements in reading timing information from BLIF. 2015-04-05 13:03:25 +07:00
Alan Mishchenko 3a15f34307 Properly copying and saving the timing info in &get and &put. 2015-04-04 16:15:07 +07:00
Alan Mishchenko 7c3eab6eb4 Properly copying and saving the timing info in &get and &put. 2015-04-04 16:01:12 +07:00
Alan Mishchenko fb5d4a664d Adding switch '-b' in 'read_pla'. 2015-03-18 10:18:46 +07:00
Alan Mishchenko e3f87e189c Propagating changes after updating flag of 'sop'. 2015-02-19 12:57:05 -08:00
Alan Mishchenko 8cabdcb55d Adding resource limit switch -C to 'sop'. 2015-02-11 12:33:54 -08:00
Alan Mishchenko 68467cfff7 Fixed a typo in variable names. 2015-02-07 22:29:14 -08:00
Alan Mishchenko 8410daf3e4 Improvements and tuning of CBA with buffering/sizing. 2015-02-04 16:29:55 -08:00
Alan Mishchenko eb270018b9 Esperiments with MO PLA optimization. 2015-02-03 17:24:30 -08:00
Alan Mishchenko e30dae5a61 Preprocessing for multi-output PLA tables. 2015-01-31 15:10:01 -08:00
Alan Mishchenko 13cd3a6a4c Preprocessing for multi-output PLA tables. 2015-01-31 14:53:58 -08:00
Alan Mishchenko e293489f71 Preprocessing for multi-output PLA tables. 2015-01-31 13:42:14 -08:00
Alan Mishchenko 6c3f191172 Preprocessing for multi-output PLA tables. 2015-01-31 11:23:22 -08:00
Alan Mishchenko ff1fb1757b Preprocessing for multi-output PLA tables. 2015-01-31 11:10:07 -08:00
Alan Mishchenko 6b6e5861e5 Integrating barrier buffers. 2014-12-13 20:45:11 -08:00
Alan Mishchenko 968be1577b Generation of barrier-buffers for hierarchical design. 2014-11-11 23:17:48 -08:00
Alan Mishchenko 5ebf135b6a Adding cyclicity check for netlist with boxes. 2014-11-10 14:55:27 -08:00
Alan Mishchenko fa5f05e3a2 Deriving AIG after cell mapping. 2014-10-03 17:15:43 -07:00
Alan Mishchenko 0c070a35e5 Adding out-of-bounds checks to AIGER readers. 2014-09-28 12:17:02 -07:00
Alan Mishchenko 98e377bdff Adding features to CNF generation. 2014-09-28 12:10:13 -07:00
Alan Mishchenko dcb7d0d3fc New word-level representation package. 2014-09-12 13:40:48 -07:00
Alan Mishchenko 49f2ec22b9 Bug fix in transferring timing info. 2014-09-09 22:50:15 -07:00
Alan Mishchenko 17343bf144 Compiler warning. 2014-08-27 23:03:39 -07:00
Alan Mishchenko 6db6607114 Improvements BLIF parser. 2014-08-27 18:47:45 -07:00
Alan Mishchenko 2edf2a970e Improvements to power-aware mapping. 2014-06-23 18:05:51 -07:00
Alan Mishchenko f79d8e4b04 Improvements to CNF generation. 2014-06-23 14:50:46 -07:00
Alan Mishchenko 44d9c7e543 Improvements to CNF generation. 2014-06-23 13:11:59 -07:00
Alan Mishchenko f04d32732b Added quick GIG parser. 2014-06-19 21:16:30 -07:00
Alan Mishchenko a03a726de2 Bug fix in writing latch init values in 'write_aiger'. 2014-06-17 14:21:28 -07:00
Alan Mishchenko 5c0c8e1ae2 Fix PLA reader to correctly report error file numbers. 2014-06-02 17:27:21 -07:00
Baruch Sterin 26c92f161a add an option to write_cex to write the CEX in AIGER 1.9 format. 2014-05-12 15:20:17 -07:00
Alan Mishchenko 6095b15174 Added dumping original object names into a file. 2014-04-26 23:47:54 -07:00
Alan Mishchenko b94b810297 Renamed Abc_Lib_t into Abc_Des_t and removed some dead code. 2014-04-09 10:16:07 -07:00
Alan Mishchenko f6ae0e41f3 Better CEX minimization and renaming of write_counter into write_cex. 2014-04-04 13:14:16 -07:00
Alan Mishchenko fa1fafe4de Adding functionally observable fault testing. 2014-03-31 21:33:02 -07:00
Alan Mishchenko 4745eac324 Improving network visualization in show/&show. 2014-03-28 15:32:29 -07:00
Alan Mishchenko f329105403 Adding barrier buffers. 2014-03-18 12:51:39 -07:00
Alan Mishchenko 89eed1aaf9 Adding barrier buffers. 2014-03-16 21:56:28 -07:00
Alan Mishchenko c97a9c0d18 Changes to LUT mappers. 2014-03-09 20:21:09 -07:00
Alan Mishchenko 737e4671ce Adding check for the presence of precomputed data. 2013-12-29 14:39:25 +07:00
Alan Mishchenko 227963f03d New command &write_cnf. 2013-12-18 00:22:26 +07:00
Alan Mishchenko 681483c904 Bug fixes in the above patches. 2013-12-03 00:38:37 -08:00
Alan Mishchenko 34ab59574e Suggested patch of AIG writers. 2013-12-03 00:26:43 -08:00
Alan Mishchenko b21447b6df Bug fix in writing constants in write_verilog. 2013-11-21 11:39:57 -08:00
Alan Mishchenko cb4631e64e Compiler warnings. 2013-10-17 18:04:07 -07:00
Alan Mishchenko efa6b54b5e Debugging and finetuning the flow. 2013-09-17 21:47:39 -07:00
Alan Mishchenko 7d3976a763 Unifying standard cell library representations. 2013-09-17 13:16:20 -07:00
Alan Mishchenko d1b9ade535 Adding switch 'ps -s' to skip counting buffers/inverters as nodes. 2013-09-02 23:15:15 -07:00
Alan Mishchenko b6cb626a12 Removing some old useless code. 2013-09-02 22:14:20 -07:00
Alan Mishchenko e16e3edae8 Removing some old useless code. 2013-09-02 22:10:27 -07:00