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273 Commits

Author SHA1 Message Date
Alan Mishchenko 680af1891b Bug fix in 'write_aiger_cex'. 2017-12-20 15:41:39 -08:00
Alan Mishchenko 1743979b75 Adding switch -a to 'write_verilog' to write factored forms without XORs and MUXes. 2017-12-03 14:39:11 -08:00
Alan Mishchenko d0286dce37 Fixing minimize_assuptions using Glucose. 2017-10-02 21:31:34 +03:00
Alan Mishchenko c696ae95d0 Maintenance and updates. 2017-09-24 23:38:01 -07:00
Alan Mishchenko 2e56f44c66 Compiler warnings. 2017-07-22 11:41:17 +07:00
Alan Mishchenko 8bff9aa1cd Adding PDR with abstraction. 2017-02-10 17:36:20 -08:00
Alan Mishchenko f2d096c9f0 Improving CEX minimization. 2017-02-10 13:20:20 -08:00
Alan Mishchenko f34029dd09 Improvements in AIG visualization. 2017-02-05 12:28:34 -08:00
Alan Mishchenko e21c7d72f3 Updates to arithmetic verification. 2017-01-30 08:39:26 -08:00
Alan Mishchenko b3514ee7e0 Commenting out bailout in 'print_cex' when CEX has latches initialized to 1. 2016-11-30 12:07:08 -08:00
Alan Mishchenko 6b55bf0205 New SAT-based optimization package. 2016-11-26 14:28:12 -08:00
Alan Mishchenko 76c4d22229 Parser for JSON format. 2016-10-25 17:17:37 -07:00
Alan Mishchenko f03512bad1 Unsuccessful attempt to improve quality of factoring by limiting distance-1 merge during preprocessing. 2016-08-06 00:17:18 -07:00
Alan Mishchenko 2ba46d52f0 Extension in the detection code. 2016-07-19 20:44:02 -07:00
Alan Mishchenko a309569390 New multi-output PLA reader and preprocessor (read_plamo) (updated dist-1 merge). 2016-06-17 22:30:54 -07:00
Alan Mishchenko 3c3a770a17 New multi-output PLA reader and preprocessor (read_plamo) (added dist-1 merge). 2016-06-16 21:09:39 -07:00
Alan Mishchenko e06c04a3ef Change to BENCH reader to read DFF with four inputs. 2016-06-16 16:48:45 -07:00
Alan Mishchenko ada21a655f New multi-output PLA reader and preprocessor (read_plamo). 2016-06-16 15:22:03 -07:00
Alan Mishchenko a18da5c878 Detecting properties of internal nodes. 2016-06-12 19:07:46 -07:00
Alan Mishchenko ea7d10d45d Adding 'read_pla -d' to read dc-set along with on-set (useful to derive offset). 2016-05-12 13:59:30 -07:00
Alan Mishchenko 11f1a249ae Updating GIG parser. 2016-05-01 17:43:50 -07:00
Alan Mishchenko 2d6a6f6654 Added Exorcism package, reading ESOP (read_pla -x file.esop) and deriving AIG (cubes -x; st). 2016-04-11 21:42:00 -07:00
Alan Mishchenko 02725c9eca An add-on to write Verilog for circuits mapped into simple gates. 2016-02-01 15:56:53 -08:00
Alan Mishchenko 41d18ca051 Changing 'refactor' to work with truth tables. 2015-08-25 11:02:34 -07:00
Alan Mishchenko 9ef96ae8a6 Changes to be able to compile ABC without CUDD. 2015-08-24 20:55:07 -07:00
Alan Mishchenko 99e3e3bc7e Changes to be able to compile ABC without CUDD. 2015-08-24 20:21:30 -07:00
Alan Mishchenko 77d64787e0 Changes to be able to compile ABC without CUDD. 2015-08-24 19:49:18 -07:00
Alan Mishchenko bab71101ec Improvements to Cba data-structure. 2015-07-29 23:13:39 -07:00
Alan Mishchenko 7f7b7671b0 Improvements to Cba data-structure. 2015-07-28 17:17:32 -07:00
Alan Mishchenko b6b9d284c4 Several additional fixed in the timing manager. 2015-04-07 00:33:20 +07:00
Alan Mishchenko 85b33df1e1 Improvements in reading timing information from BLIF. 2015-04-05 13:03:25 +07:00
Alan Mishchenko 3a15f34307 Properly copying and saving the timing info in &get and &put. 2015-04-04 16:15:07 +07:00
Alan Mishchenko 7c3eab6eb4 Properly copying and saving the timing info in &get and &put. 2015-04-04 16:01:12 +07:00
Alan Mishchenko fb5d4a664d Adding switch '-b' in 'read_pla'. 2015-03-18 10:18:46 +07:00
Alan Mishchenko e3f87e189c Propagating changes after updating flag of 'sop'. 2015-02-19 12:57:05 -08:00
Alan Mishchenko 8cabdcb55d Adding resource limit switch -C to 'sop'. 2015-02-11 12:33:54 -08:00
Alan Mishchenko 68467cfff7 Fixed a typo in variable names. 2015-02-07 22:29:14 -08:00
Alan Mishchenko 8410daf3e4 Improvements and tuning of CBA with buffering/sizing. 2015-02-04 16:29:55 -08:00
Alan Mishchenko eb270018b9 Esperiments with MO PLA optimization. 2015-02-03 17:24:30 -08:00
Alan Mishchenko e30dae5a61 Preprocessing for multi-output PLA tables. 2015-01-31 15:10:01 -08:00
Alan Mishchenko 13cd3a6a4c Preprocessing for multi-output PLA tables. 2015-01-31 14:53:58 -08:00
Alan Mishchenko e293489f71 Preprocessing for multi-output PLA tables. 2015-01-31 13:42:14 -08:00
Alan Mishchenko 6c3f191172 Preprocessing for multi-output PLA tables. 2015-01-31 11:23:22 -08:00
Alan Mishchenko ff1fb1757b Preprocessing for multi-output PLA tables. 2015-01-31 11:10:07 -08:00
Alan Mishchenko 6b6e5861e5 Integrating barrier buffers. 2014-12-13 20:45:11 -08:00
Alan Mishchenko 968be1577b Generation of barrier-buffers for hierarchical design. 2014-11-11 23:17:48 -08:00
Alan Mishchenko 5ebf135b6a Adding cyclicity check for netlist with boxes. 2014-11-10 14:55:27 -08:00
Alan Mishchenko fa5f05e3a2 Deriving AIG after cell mapping. 2014-10-03 17:15:43 -07:00
Alan Mishchenko 0c070a35e5 Adding out-of-bounds checks to AIGER readers. 2014-09-28 12:17:02 -07:00
Alan Mishchenko 98e377bdff Adding features to CNF generation. 2014-09-28 12:10:13 -07:00