luke
/
abc
mirror of https://github.com/YosysHQ/abc.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity
4,264 Commits 27 Branches 57 Tags 58 MiB
Commit Graph

4264 Commits

Author SHA1 Message Date
Alan Mishchenko 76b00a2d3e Compilation problem with pow(). 2018-02-19 09:07:44 -08:00
Alan Mishchenko 1d1b11cb65 Improvements to circuit based solver. 2018-02-17 13:10:48 -08:00
Alan Mishchenko fd390aae9d Extending MiniLUT to return attributes. 2018-02-11 17:14:07 -08:00
Alan Mishchenko f716948c27 Experiments with LUT mapping. 2018-02-10 15:45:54 -08:00
Alan Mishchenko c6bce9c20e Fixing input swapping issue in MUXes derived from NDR. 2018-02-07 09:02:28 -08:00
Alan Mishchenko e839091ba0 Suggested fix to compile on FreeBSD. 2018-02-05 19:00:46 -08:00
Alan Mishchenko f8d9fc3a9d Improvements to NDR to represent hierarchical designs. 2018-02-05 00:41:05 -08:00
Alan Mishchenko 28602ccf2c Improvements to NDR to represent hierarchical designs. 2018-02-05 00:39:10 -08:00
Alan Mishchenko 3202c2581e Improvements to NDR to represent hierarchical designs. 2018-02-05 00:37:39 -08:00
Alan Mishchenko 00fb1d706b Suggested fix to compile on FreeBSD. 2018-02-04 21:09:33 -08:00
Alan Mishchenko 30a06d002a Adding support of reading and writing designs using a new internal format (bug fix). 2018-01-29 17:01:01 -08:00
Alan Mishchenko 99ddb64095 Adding support of reading and writing designs using a new internal format. 2018-01-28 18:53:20 -08:00
Alan Mishchenko c8008383cf Experiments with circuit-based SAT. 2018-01-27 20:29:46 -08:00
Alan Mishchenko 20603c7585 Experiments with circuit-based SAT. 2018-01-27 15:25:31 -08:00
Alan Mishchenko f826956b07 Experiments with circuit-based SAT. 2018-01-27 14:33:49 -08:00
Alan Mishchenko 99c4dda767 Experiments with circuit-based SAT. 2018-01-27 14:05:00 -08:00
Alan Mishchenko 5158acb113 Experiments with circuit-based SAT. 2018-01-27 13:05:37 -08:00
Alan Mishchenko e4cd0d60f1 Experiments with SAT-based simulation. 2018-01-25 00:09:27 -08:00
Alan Mishchenko 066e8d1b17 Experiments with SAT-based simulation. 2018-01-23 19:45:17 -08:00
Alan Mishchenko 67e820a5eb Updates to exact synthesis commands. 2018-01-22 14:28:49 -08:00
Alan Mishchenko 6274498e01 Updates to exact synthesis commands. 2018-01-19 14:03:24 -08:00
Alan Mishchenko c2b6e03c61 Backing up node's truth-table to make sure it is not destroyed while deriving AIG. 2018-01-19 12:22:48 -08:00
Alan Mishchenko 0ec5d2f7bc Fixed crash in &nf when there is no buffer gate. 2018-01-12 22:28:30 -08:00
Alan Mishchenko 29895ca2f8 Merged in Fatsie/abc/liberty_value_expression (pull request #87) 
Allow expression in value in liberty file
 2018-01-05 06:47:44 +00:00
Alan Mishchenko 7d781c37e8 New command 'testexact'. 2018-01-04 22:35:11 -08:00
Alan Mishchenko 834e248019 New command 'testexact'. 2018-01-04 22:33:29 -08:00
Staf Verhaegen e513afae09 Created new branch liberty_value_expression 2018-01-04 22:05:57 +00:00
Staf Verhaegen e4875df4e5 Value of properties can be expression. 
Example found in the 2007.03 Liberty Reference Manual that was also found
in the wild:

    input_voltage(CMOS) {
        vil : 0.3 * VDD ;
        vih : 0.7 * VDD ;
        vimin : -0.5 ;
        vimax : VDD + 0.5 ;
    }

Current implementation just parses the expression but no interpretation is done.
 2018-01-03 21:54:38 +00:00
Alan Mishchenko f3dcf87cea New exact synthesis command 'allexact'. 2017-12-30 16:13:52 -08:00
Alan Mishchenko 75d334a0df New exact synthesis command 'allexact'. 2017-12-28 23:05:36 -08:00
Alan Mishchenko 7d7ce3ecd0 New exact synthesis command 'allexact'. 2017-12-28 23:04:24 -08:00
Alan Mishchenko c3dccf3020 Corner-case bug fixed in CNF generation. 2017-12-28 13:32:02 -08:00
Alan Mishchenko feebac4156 Corner-case bug fixed in CNF generation. 2017-12-28 13:26:08 -08:00
Alan Mishchenko 680af1891b Bug fix in 'write_aiger_cex'. 2017-12-20 15:41:39 -08:00
Alan Mishchenko c7b65a15d3 Adding parameter structure to 'twoexact' and 'lutexact'. 2017-12-06 15:09:11 -08:00
Alan Mishchenko 93b96fc35c An improvement to 'twoexact' and 'lutexact'. 2017-12-06 14:34:03 -08:00
Alan Mishchenko c6b962efc8 An improvement to 'twoexact' and 'lutexact'. 2017-12-06 13:51:10 -08:00
Alan Mishchenko e37bbba72d An improvement to 'twoexact' and 'lutexact'. 2017-12-06 13:00:08 -08:00
Alan Mishchenko 9e515ae363 An improvement to 'twoexact' and 'lutexact'. 2017-12-06 12:31:24 -08:00
Alan Mishchenko 67181d0446 An improvement to 'twoexact' and 'lutexact'. 2017-12-06 11:18:43 -08:00
Alan Mishchenko c4322a0afd Switch -a to use only AND-gates in 'twoexact' and 'lutexact'. 2017-12-06 10:31:21 -08:00
Alan Mishchenko b258db83b8 An improvement to 'twoexact' and 'lutexact'. 2017-12-06 09:53:25 -08:00
Alan Mishchenko 3f35ac8180 New command 'lutexact'. 2017-12-05 18:22:27 -08:00
Alan Mishchenko e5d8335268 Experiments with AIG-based simulation. 2017-12-05 09:49:02 -08:00
Alan Mishchenko 1743979b75 Adding switch -a to 'write_verilog' to write factored forms without XORs and MUXes. 2017-12-03 14:39:11 -08:00
Alan Mishchenko a49dfbcf91 Portability changes for gcc-6 suggested by Clifford. 2017-12-03 08:08:36 -08:00
Alan Mishchenko 46175d0429 Portability changes for gcc-6 suggested by Clifford. 2017-12-02 19:47:24 -08:00
Alan Mishchenko 3cc4080c55 Portability changes for gcc-6 suggested by Clifford. 2017-12-02 19:44:08 -08:00
Alan Mishchenko c681506b48 Improvements to AIG-based quantification. 2017-11-26 14:41:05 -08:00
Baruch Sterin 7bcfe64369 C++ comaptibility: add namespace support to Glucose 2017-11-23 23:32:44 -08:00