luke
/
abc
mirror of https://github.com/YosysHQ/abc.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity
5,379 Commits 27 Branches 57 Tags 58 MiB
Commit Graph

1674 Commits

Author SHA1 Message Date
aletempiac 6052d10fde Adding new command if -U for 2-LUT decompositions under delay profile 2024-04-11 15:45:37 +02:00
aletempiac 32bc1d4ab2 Cleaning and generalizing code 2024-04-11 11:31:28 +02:00
aletempiac db72df7a63 Merge remote-tracking branch 'origin/master' into acd66 2024-03-18 10:08:48 +01:00
alanminko 3040b8ddd5
Merge pull request #282 from allen1236/master 
&brecover with speculative reduction
 2024-03-16 08:52:57 +09:00
Allen Ho b7884aaf2b clean up & add options for &brecover 2024-03-16 01:40:11 +08:00
Allen Ho 015dd2a367 use speculative in &brecover 2024-03-15 16:56:10 +08:00
Alan Mishchenko a16a0f1027 Writing Verilog for AIG using NAND gates. 2024-03-06 01:40:48 -08:00
Allen Ho bfbec71211 &stc_eco and &brecover done 2024-03-04 09:36:35 +08:00
Allen Ho bcf04fadb6 &brecover done 2024-03-04 00:54:23 +08:00
alanminko 390a0e8ef3
Merge pull request #279 from allen1236/master 
Sat-sweeping-based ECO (&str_eco)
 2024-03-02 15:38:08 -08:00
Allen Ho 23654254e1 clean up 2024-03-03 03:06:13 +08:00
Allen Ho f5f4dca013 clean up 2024-03-02 21:08:10 +08:00
aletempiac 9bec2afd60 Removing -z flag to execute delay-driven ACD 2024-03-01 10:04:48 +01:00
Allen Ho 6f5656c188 shared EI/EO not handled yet 2024-03-01 16:05:41 +08:00
Alan Mishchenko 1fd79c8430 Fixing a bug in input/output name ordering. 2024-02-29 15:19:47 -08:00
aletempiac f72000f5ae Adding ACD cascade 666, performance improvements 2024-02-21 18:25:48 +01:00
aletempiac 17afd93c78 Extending ACD to work up to 11 variables 2024-02-08 15:36:09 +01:00
aletempiac 2d9af6c9a4 Adding ACD for 66 LUT structure using a new method 2024-02-08 09:36:58 +01:00
Alan Mishchenko e9a0bf6bf9 Adding reversing of simulation bits in &sim_read. 2024-02-05 20:32:11 -08:00
Allen Ho c74144c6eb str_eco ver1 2024-02-01 07:25:46 +08:00
Alan Mishchenko d6555f48dd Adding a switch to not write the timestamp in the AIGER file. 2024-01-26 07:31:20 -08:00
Alan Mishchenko 8da884de85 Switch to reverse the order of bits. 2024-01-18 18:23:11 -08:00
Allen Ho 284b9d6a9c extended box report; 2023-12-10 21:30:46 +08:00
Allen Ho 9bb5333f62 extend bo 2023-12-07 19:07:52 +08:00
aletempiac b3d2419d9a Formatting, renaming, and cleaning code 2023-11-27 13:38:36 +01:00
aletempiac 1632dc0d4e First version of ACD 2023-11-15 18:38:00 +01:00
Alan Mishchenko 6ca7eab466 Prototype of integrating decomposition into "if". 2023-11-14 12:58:03 -08:00
WWFUG 67a2b97cf0 added -I options in &bmiter 2023-11-08 19:00:03 +08:00
Alan Mishchenko 01ad71b26f Experiments with verification. 2023-10-23 09:38:08 -07:00
Alan Mishchenko 652a0aaef7 Compiler warning. 2023-10-20 22:42:40 -07:00
Alan Mishchenko 72b423ba14 Experiments with SAT solving. 2023-10-20 20:53:43 -07:00
Alan Mishchenko cc636a0d83 Experiments with verification. 2023-09-28 06:40:57 -07:00
Alan Mishchenko 4d1618f600 Enable dumping Verilog with assign-statements. 2023-09-21 11:08:43 +08:00
Allen Ho 31ad17fa1a add abc9RecoverBoundary 2023-09-20 14:23:47 +08:00
Alan Mishchenko 09b0295c1a Adding aliases for some commands. 2023-09-18 16:27:54 +08:00
Alan Mishchenko 9399faac48 Improvements to &gen_hie. 2023-09-17 12:40:33 +08:00
Alan Mishchenko 475c8dad8e Compiler problem. 2023-09-16 07:13:10 +08:00
Cunxi Yu 1261f71248
Merge branch 'berkeley-abc:master' into master 2023-09-15 13:25:27 -07:00
Alan Mishchenko 57cc2bd089 Compiler problem. 2023-09-15 22:51:11 +08:00
Alan Mishchenko 09013f3a6e New command &gen_hie to generate hierarchical designs. 2023-09-15 22:44:31 +08:00
Alan Mishchenko 588122dc72 Writing an interface module when dumping Verilog. 2023-09-11 09:44:22 +07:00
Alan Mishchenko a4755a37cb Experiments with CEC. 2023-09-08 22:42:41 +07:00
Alan Mishchenko f844fb1057 Command to add one flop to the design. 2023-09-08 16:46:14 +07:00
alanminko 00fa1e3714
Merge pull request #241 from wjrforcyber/typo 
Refactor(Typo):Typo currently exists
 2023-09-05 14:09:40 +07:00
CUNXI YU 855976c61d correct the naming of augmentation 2023-08-27 11:19:26 -06:00
CUNXI YU 0fe977a33c correct the naming of augmentation 2023-08-27 11:18:35 -06:00
Daniel Gröber b7d1435db1 treewide: Fix spelling mistakes 
A particularly pedantic set of changes currently used in Debian

Authored-By: Ruben Undheim <ruben.undheim@gmail.com>
 2023-08-27 14:13:20 +02:00
wjrforcyber 0971429b56 Refactor(Typo):rec_add2 is no longer exist 2023-08-18 12:42:13 +08:00
lyj1201 0fab82384a add AIG random synthesis based RTL argumentation; command = aigarg 2023-08-14 12:04:33 -06:00
Alan Mishchenko a603186d8e "Fixing usage message of &ps." 2023-08-11 07:14:11 +07:00