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767 Commits

Author SHA1 Message Date
Alan Mishchenko 5cf9d6ddd7 Experiments with mini AIG manager. 2012-09-29 16:17:19 -04:00
Alan Mishchenko ae1dddbcc3 Experiments with mini AIG manager. 2012-09-29 15:37:31 -04:00
Alan Mishchenko 62a6152b6c Experiments with mini AIG manager. 2012-09-29 15:29:07 -04:00
Alan Mishchenko 74c9a068eb Updated version of LMS code. 2012-09-26 08:50:15 -07:00
Alan Mishchenko 27383e8be2 Updated version of LMS code. 2012-09-26 08:36:05 -07:00
Alan Mishchenko 794b4cd8ce Updated version of LMS code. 2012-09-26 08:23:40 -07:00
Alan Mishchenko 8c369788b3 Improvements to the NPN semi-canonical form computation package. 2012-09-25 13:20:18 -07:00
Alan Mishchenko 0a9236add5 Improvements to the NPN semi-canonical form computation package. 2012-09-25 13:10:52 -07:00
Alan Mishchenko aed3b3a13a Cleaned up interfaces of genlib/liberty/supergate reading/writing. 2012-09-25 01:34:26 -07:00
Alan Mishchenko d0197d8378 Changed printouts in a few places in supergate computation. 2012-09-24 22:57:01 -07:00
Alan Mishchenko 6f03813557 Testing GIA with time manager. 2012-09-24 01:13:51 -07:00
Alan Mishchenko 40d9b5853b Testing GIA with time manager. 2012-09-23 18:34:10 -07:00
Alan Mishchenko f7caf84f21 Modified structural constraint extraction (unfold -s) to work for multi-output testcases. 2012-09-23 14:30:17 -07:00
Alan Mishchenko c8ed816714 Migrating to array-based traversal ID. 2012-09-23 12:29:16 -07:00
Alan Mishchenko 6e774ef541 Cleaing AIG manager by removing pointers to HAIG. 2012-09-23 12:01:59 -07:00
Alan Mishchenko a50a38155c Integrating time manager into choice computation. 2012-09-22 17:57:06 -07:00
Alan Mishchenko b5306c1566 Added simplification before the concurrent call to PDR. 2012-09-20 20:13:40 -07:00
Alan Mishchenko 5f09917c22 Added simplification before the concurrent call to PDR. 2012-09-20 19:51:39 -07:00
Alan Mishchenko d21c0be44a Added slack computation to 'stime'. 2012-09-20 14:13:59 -07:00
Alan Mishchenko 266af49386 Modified 'read' to read all types of libraries (genlib, liberty, scl). 2012-09-20 13:12:51 -07:00
Alan Mishchenko bc44087bac Modified 'read' to read all types of libraries (genlib, liberty, scl). 2012-09-20 12:41:59 -07:00
Alan Mishchenko f59de3decc Fixes to Verilog parser. 2012-09-20 11:29:37 -07:00
Alan Mishchenko 723f85ef1b Extending Liberty parser to handle multi-output cells. 2012-09-19 20:21:27 -07:00
Alan Mishchenko 5dc50744f0 Extending Liberty parser to handle multi-output cells. 2012-09-19 18:42:00 -07:00
Alan Mishchenko 480ca14c75 Extending Liberty parser to handle multi-output cells. 2012-09-19 17:35:04 -07:00
Alan Mishchenko 3af0f719af Extending BLIF parser/write to hangle multi-output cells. 2012-09-19 16:28:06 -07:00
Alan Mishchenko e0eb270324 Changes to command 'upsize'. 2012-09-18 13:23:58 -07:00
Alan Mishchenko 508b6f1b13 Fixing mismatch between declaration of the output value of Extra_CpuTime. 2012-09-18 09:58:06 -07:00
Alan Mishchenko 7e843d64a9 Added delay multipliers to 'map'. 2012-09-16 23:34:56 -07:00
Alan Mishchenko 6d05fde2dc Added delay multipliers to 'map'. 2012-09-16 22:05:15 -07:00
Alan Mishchenko ee436f9377 Changed a few things in the refinement package of &gla. 2012-09-16 13:56:10 -07:00
Alan Mishchenko 5953beb2da Restructured the code to post-process object used during refinement in &gla. 2012-09-16 09:54:19 -07:00
Alan Mishchenko fdf5ad3433 Cleaned 'abc.c' by removing useless procedures. 2012-09-15 23:52:36 -07:00
Alan Mishchenko 69bbfa9856 Created new abstraction package from the code that was all over the place. 2012-09-15 23:27:46 -07:00
Alan Mishchenko 117bc0dbcd Prepared &gla to try abstracting and proving concurrently. 2012-09-14 21:20:37 -07:00
Alan Mishchenko 3b14c7b490 Prepared &gla to try abstracting and proving concurrently. 2012-09-14 13:31:29 -07:00
Alan Mishchenko 19c28cae94 Prepared &gla to try abstracting and proving concurrently. 2012-09-14 10:27:48 -07:00
Alan Mishchenko a246882a5b Scalable gate-level abstraction. 2012-09-11 19:11:51 -07:00
Niklas Een 1c865bf229 Added -C to command line for running commands, then staying in interactive mode 2012-09-11 18:48:43 -07:00
Alan Mishchenko 784a3579e5 Fixing Verilog writer's way of writing module names. 2012-09-11 18:44:07 -07:00
Alan Mishchenko d40af538e2 Unified print-out of property failures produced by all engines. 2012-09-09 20:46:34 -07:00
Alan Mishchenko 56117d56e8 Added switch '-p' to '&gla -n' to use full proof for UNSAT core computation (for experiments). 2012-09-09 15:28:31 -07:00
Alan Mishchenko 4333fd24d2 Started CEX minimization procedure. 2012-09-08 18:28:13 -07:00
Alan Mishchenko 5ca4f3cf9f Updating &gla_refine to perform suffic refinement. 2012-09-07 23:26:23 -07:00
Alan Mishchenko 548e04192b Updating &gla_refine to perform suffic refinement. 2012-09-07 20:44:12 -07:00
Alan Mishchenko 39fe23f079 Integrated new fast semi-canonical form for Boolean functions up to 16 inputs. 2012-09-06 15:52:54 -07:00
Alan Mishchenko 9c8be56ccd Integrated new fast semi-canonical form for Boolean functions up to 16 inputs. 2012-09-06 15:32:07 -07:00
Alan Mishchenko cd2bd70865 Added switch 'dch -r' to skip choices with structural support redundancy. 2012-09-05 19:39:25 -07:00
Alan Mishchenko c1f4545e07 Added error message when the user is trying 'dsat' for multi-output comb miters. 2012-09-05 18:53:21 -07:00
Alan Mishchenko f6b67d7846 Added new command &gla_shrink. 2012-09-04 23:57:58 -07:00