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4627 Commits

Author SHA1 Message Date
Alan Mishchenko 4b4646283f Experiments with ICCAD CAD benchmarks (Problem A). 2020-09-03 16:43:53 -07:00
Alan Mishchenko 26e03ef6a0 Experiments with window computation. 2020-08-15 17:12:41 -07:00
Alan Mishchenko 850d39fec3 Making &cec use precomputed simulation info. 2020-08-12 19:32:42 -07:00
Alan Mishchenko b74b7dfc2d Extending &sim_read to use non-64-divisible pattern counts. 2020-08-12 15:33:09 -07:00
Alan Mishchenko 5c8ee4a2c1 New ways of reading MiniAIG. 2020-07-29 19:50:10 -07:00
Alan Mishchenko aaeadb1438 New ways of reading MiniAIG. 2020-07-29 19:48:36 -07:00
Alan Mishchenko 448f263443 Fixing new resub code. 2020-07-20 19:56:06 -07:00
Alan Mishchenko 25538c23c5 Fixing new resub code. 2020-07-20 19:52:45 -07:00
Alan Mishchenko 22d9b1d38b Experiment with structural similarity. 2020-07-16 20:33:03 -07:00
Alan Mishchenko ba063a1b55 Correctly handling transfer of additional AIG info when AIG has no internal nodes. 2020-07-13 11:23:11 -07:00
Alan Mishchenko 2ba092e4cc Fixing commands 'putontop' and 'topmost'; adding command 'bottommost'. 2020-07-11 10:14:43 -07:00
Alan Mishchenko 0b734d10e0 Adding new resub code. 2020-07-08 10:56:59 -07:00
Alan Mishchenko 83f54185ef Bug fix in &cec (properly updating the status after the corner case bug fix\). 2020-06-24 10:57:47 -07:00
Alan Mishchenko 322cea8234 Bug fix in &cec (handling the case when the miter is disproved by the all-0 pattern). 2020-06-24 10:20:28 -07:00
Alan Mishchenko 58e3a5caff Compiler error. 2020-06-04 16:48:06 -07:00
Alan Mishchenko a3c6f33a87 Experimental simulation. 2020-06-04 16:24:43 -07:00
Alan Mishchenko 491e4ebfd1 Experimental simulation. 2020-06-03 14:52:42 -07:00
Alan Mishchenko 97c826a6e6 Dumping BDD variable order after 'clp'. 2020-05-18 16:02:57 -07:00
Alan Mishchenko 0ae0744e73 Experimental resubstitution. 2020-05-15 22:11:10 -07:00
Alan Mishchenko a8bd59bd68 Experimental resubstitution. 2020-05-13 10:40:09 -07:00
Alan Mishchenko 9bfccf76c1 Experimental resubstitution. 2020-05-11 17:40:40 -07:00
Alan Mishchenko 1c0ea1022f Adding new utility procedures. 2020-05-11 17:08:00 -07:00
Alan Mishchenko a3ada00d86 Adding new utility procedures. 2020-05-10 19:44:59 -07:00
Alan Mishchenko a7871d24cd Experimental resubstitution. 2020-05-08 13:50:29 -07:00
Alan Mishchenko a918e2dab1 Experimental resubstitution. 2020-05-07 21:44:35 -07:00
Alan Mishchenko 372eb7bdef Experimental resubstitution. 2020-05-07 20:06:39 -07:00
Alan Mishchenko f8b6d615bf Fixing the accidentally broken build. 2020-05-06 12:48:11 -07:00
Alan Mishchenko 234b5d771b Experiment with permutations. 2020-05-03 21:59:33 -07:00
Alan Mishchenko f543d39ec8 Experiment with permutations. 2020-05-03 21:09:02 -07:00
Alan Mishchenko f026e65339 Compiler warnings and errors. 2020-05-03 19:09:02 -07:00
Alan Mishchenko e149cdcd77 Compiler warnings. 2020-05-03 12:15:54 -07:00
Alan Mishchenko 2b58a83ac0 Adding dumping of genlib library in Verilog. 2020-05-03 12:11:48 -07:00
Alan Mishchenko 559f8f5b5e Adding dumping of genlib library in Verilog. 2020-05-03 12:09:55 -07:00
Alan Mishchenko 3e150dd553 Adding dumping of genlib library in Verilog. 2020-05-03 12:07:52 -07:00
Alan Mishchenko d51f798956 Experimental resubstitution. 2020-05-03 10:32:30 -07:00
alanminko 8de27b691b
Merge pull request #57 from whitequark/patch-1 
Make use of setrlimit conditional on ABC_NO_RLIMIT
 2020-04-30 14:03:26 -07:00
alanminko fb8d13a1c5
Merge pull request #65 from FPGeh/fix_seq_synth 
Gia_ManDupPermFlop to behave as Gia_ManDupPerm
 2020-04-30 14:01:08 -07:00
whitequark 8afd927d60 Make use of setrlimit conditional on ABC_NO_RLIMIT. 
This is useful for POSIX-like platforms that do not have rlimit,
such as WASI.
 2020-04-30 02:17:03 +00:00
Alan Mishchenko 5f16cd94d6 Adding new API to MiniAIG. 2020-04-29 15:13:36 -07:00
Alan Mishchenko f030a2a5e2 Adding new API to MiniAIG. 2020-04-29 14:41:57 -07:00
Alan Mishchenko cf1fdc82e4 Bug fix in 'resub' to enable additional divisors, by Siang-Yun Lee. 2020-04-27 18:52:19 -07:00
Eddie Hung f2316ab7c8 Gia_ManDupPermFlop to behave as Gia_ManDupPerm 
Fixes sequential synthesis (e.g. &scl) for multiple domains
 2020-04-27 15:09:04 -07:00
Alan Mishchenko ea1fbfc971 New AIG restructuring feature. 2020-04-23 15:33:49 -07:00
Alan Mishchenko 978b5db039 Fix a bug in comb loop detection. 2020-04-22 16:49:21 -07:00
Alan Mishchenko 94a2cffefe Improving simulation patterns by local search. 2020-04-17 18:58:21 -07:00
Alan Mishchenko d0e316df5b Improving simulation patterns by local search. 2020-04-17 18:56:12 -07:00
Alan Mishchenko 5f163c0152 Fixing broken build and compiler warnings. 2020-04-17 10:32:38 -07:00
Alan Mishchenko 61a88f164c Fixing broken build and compiler warnings. 2020-04-17 10:16:26 -07:00
Alan Mishchenko 203a7d6ad8 Fixing broken build and compiler warnings. 2020-04-17 10:14:44 -07:00
Alan Mishchenko 92abe5cb87 Removing debug stop. 2020-04-17 09:55:54 -07:00