luke
/
UberDDR3
mirror of https://github.com/AngeloJacobo/UberDDR3.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity
Opensource DDR3 Controller
237 Commits 6 Branches 0 Tags 65 MiB
Verilog 58.7%
SystemVerilog 21.3%
Tcl 15.6%
Makefile 1.7%
Shell 1.3%
Other 1.4%
Go to file
Angelo Jacobo 72b249a862
Update README.md 		2023-09-21 06:07:03 +08:00
kintex_switch_files add wbscope 2023-09-15 20:05:31 +08:00
rtl add reset control from controller to phy 2023-09-15 19:59:39 +08:00
testbench update simulation files 2023-09-15 20:04:55 +08:00
.gitignore update gitignore 2023-07-24 17:37:07 +08:00
.gitmodules added uart submodule 2023-08-17 11:36:15 +08:00
LICENSE changed license to Apache 2.0 2023-03-23 20:18:46 +08:00
README.md Update README.md 2023-09-21 06:07:03 +08:00
ddr3.sby not yet working when real parameter is used 2023-08-24 18:03:12 +08:00
ddr3_controller.sby set depth to 7 (minimum) 2023-07-13 18:43:47 +08:00
ddr3_dimm_micron_sim_behav.wcfg update wave files 2023-09-15 20:00:29 +08:00
formal.gtkw update wave files 2023-09-15 20:00:29 +08:00
formal_wb2.gtkw Update formal_wb2.gtkw 2023-07-13 19:34:56 +08:00
run_compile.sh script for running verilator, yosys, iverilog, and then symbiyosys 2023-07-24 17:33:56 +08:00

README.md

DDR3_Controller (This repo will SOON be documented)

🚧 👷‍♂️ 👷‍♂️ UNDER CONSTRUCTION 👷‍♂️ 👷‍♂️ 🚧