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UberDDR3
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Opensource DDR3 Controller
8 Commits 6 Branches 0 Tags 65 MiB
Verilog 58.7%
SystemVerilog 21.3%
Tcl 15.6%
Makefile 1.7%
Shell 1.3%
Other 1.4%
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Angelo Jacobo 71df6f7515
moved all parameters to the main verilog file 		2023-03-09 18:01:58 +08:00
rtl moved all parameters to the main verilog file 2023-03-09 18:01:58 +08:00
LICENSE Initial commit 2023-03-02 19:44:58 +08:00
README.md Update README.md 2023-03-02 20:32:12 +08:00
ddr3_controller.sby added sby file for formal verif 2023-03-02 20:11:10 +08:00
run.sh include directory on iverilog command 2023-03-02 20:20:14 +08:00

README.md

DDR3_Controller

🚧 🚧 🚧 👷‍♂️ 👷‍♂️ UNDER CONSTRUCTION 👷‍♂️ 👷‍♂️ 🚧 🚧 🚧