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UberDDR3
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Opensource DDR3 Controller
3 Commits 6 Branches 0 Tags 65 MiB
Verilog 58.7%
SystemVerilog 21.3%
Tcl 15.6%
Makefile 1.7%
Shell 1.3%
Other 1.4%
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Angelo Jacobo 0f6f52390c
added shell script for compiling RTL 		2023-03-02 20:07:08 +08:00
rtl added initial RTLs 2023-03-02 20:04:37 +08:00
LICENSE Initial commit 2023-03-02 19:44:58 +08:00
README.md Initial commit 2023-03-02 19:44:58 +08:00
run.sh added shell script for compiling RTL 2023-03-02 20:07:08 +08:00

README.md

DDR3_Controller