fb8dd029e3
Delete ug586_7Series_MIS.pdf
2023-05-28 16:08:40 +08:00
5092543e74
Add files via upload
2023-05-25 19:45:06 +08:00
30b5675b41
Update README.md
2023-05-25 19:41:51 +08:00
6710b5b62b
Add files via upload
2023-05-25 19:14:12 +08:00
1e89a236df
fixed implementation errors in Vivado
2023-05-25 19:13:30 +08:00
4e07df4018
Update README.md
2023-05-22 19:59:17 +08:00
a7de749ddf
Add files via upload
2023-05-22 19:53:20 +08:00
f91e5ea75d
Update README.md
2023-05-18 11:51:19 +08:00
94d6253069
Add files via upload
2023-05-18 11:02:40 +08:00
991dcad40b
Add files via upload
2023-05-18 10:50:30 +08:00
8e6c422689
complete read and write calibration
2023-05-18 10:45:26 +08:00
ee990dd647
Update README.md
2023-05-11 19:36:56 +08:00
9602a4225d
Update README.md
2023-05-11 19:23:11 +08:00
614fd7dfe2
Update README.md
2023-05-11 19:22:34 +08:00
520300ecb0
Update README.md
2023-05-11 19:12:16 +08:00
f280ba3efd
Update README.md
2023-05-11 19:07:17 +08:00
233b89dafb
Update README.md
2023-05-11 18:58:25 +08:00
c21879c165
Update README.md
2023-05-11 18:50:59 +08:00
b631fe7ebc
Update README.md
2023-05-11 18:24:12 +08:00
ec8d957291
Update README.md
2023-05-11 18:03:30 +08:00
c33bc40bd3
Update ddr3_controller.v
2023-05-11 15:35:34 +08:00
9be5b5a616
Update ddr3_controller.v
2023-05-11 14:49:47 +08:00
f3c4b1b465
Update ddr3_controller.v
2023-05-10 15:23:48 +08:00
6c67942a80
Update README.md
2023-04-27 20:02:37 +08:00
d7db0d33e0
Update README.md
2023-04-27 19:56:43 +08:00
fd09ce2ed9
Update README.md
2023-04-27 19:48:59 +08:00
c0172c24a3
added read phy interface
2023-04-27 19:40:35 +08:00
7debc3a4ce
Update README.md
2023-04-20 22:20:44 +08:00
4c503e7225
Update README.md
2023-04-20 19:59:55 +08:00
a5b14accf4
added PHY interface
2023-04-20 19:37:15 +08:00
92b9d4b909
Update README.md
2023-04-20 19:20:47 +08:00
060a0373e9
Update ddr3_controller.v
2023-04-06 19:56:55 +08:00
9a0b0cde36
Add files via upload
2023-04-06 19:45:09 +08:00
7c47580d4d
Delete formal_cover.gtkw
2023-04-06 19:44:30 +08:00
3b110018c7
Update ddr3_controller.v
2023-04-06 19:43:32 +08:00
328bcf761a
Update README.md
2023-04-06 19:41:57 +08:00
5b22cf3f3b
Update README.md
2023-04-06 19:22:22 +08:00
fec8b5b3fc
Update ddr3_controller.v
2023-04-06 19:01:02 +08:00
b7dc38c510
Update README.md
2023-04-06 17:54:16 +08:00
7bb755b9d5
Update README.md
2023-04-06 17:34:05 +08:00
1380c03c85
Update README.md
2023-04-06 17:31:23 +08:00
ae201bfd04
removed irrelevant comments
2023-03-30 19:18:55 +08:00
192a9950e4
applied :retab
2023-03-30 18:27:58 +08:00
7e1a145238
added gtkwave template
2023-03-30 18:19:14 +08:00
fa5fcc2615
use a 4-bit counter plus a 4-bit mask for tracking delay in every bank
...
this is the optimized delay-tracking mechanism on which the 32-bit shift regs is replaced by a 4-bit counter plus a 4-bit mask. This uses lower resources but still able to track the delays and the exact slot number where the delay is already satisfied (hence no added latency)
2023-03-30 18:17:46 +08:00
fa3f5e0d65
use 32-bit shift reg for tracking delay inside every bank
...
There are 4 delays being tracked (delay_before_precharge, delay_before_activate, delay_before_read, and delay_before_write) and 8 banks, that means 32x4x8 = 1024 bits needed for this tracking delay mechanism (totally wasteful!)
2023-03-30 18:14:09 +08:00
73e5f6b3de
added begin-end in short if-else statement
2023-03-23 20:35:37 +08:00
2018aa7ef7
changed license to Apache 2.0
2023-03-23 20:18:46 +08:00
97092cf869
added logic for refresh sequence and bank access
2023-03-23 20:17:12 +08:00
59ac654990
Delete LICENSE
2023-03-23 20:10:22 +08:00
Angelo Jacobo