3 Commits

Author	SHA1	Message	Date
Angelo Jacobo	71df6f7515	moved all parameters to the main verilog file	2023-03-09 18:01:58 +08:00
Angelo Jacobo	3633613c47	Update ddr3_controller.v	2023-03-02 20:12:28 +08:00
Angelo Jacobo	38109d8297	added initial RTLs	2023-03-02 20:04:37 +08:00