Cho Moon 5c6fb74389 enhance verilog reader to support uninstantiated modules ... Signed-off-by: Cho Moon <cmoon@precisioninno.com>		2024-12-20 01:47:09 +00:00
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Verilog.i	mv copyright to top in swig files	2024-07-24 09:04:08 -07:00
Verilog.tcl	update copyright	2024-01-11 16:34:49 -08:00
VerilogLex.ll	Fixes constant integer verilog parsing	2024-10-08 20:40:07 +00:00
VerilogParse.yy	Fixes memory leak in verilog attribute code.	2024-04-22 21:54:12 +00:00
VerilogReader.cc	enhance verilog reader to support uninstantiated modules	2024-12-20 01:47:09 +00:00
VerilogReaderPvt.hh	enhance verilog reader to support uninstantiated modules	2024-12-20 01:47:09 +00:00
VerilogWriter.cc	write_verilog unconnected wire dcls for non-top level modules	2024-10-21 11:33:11 -07:00