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write_verilog unconnected wire dcls for non-top level modules 

Signed-off-by: James Cherry <cherry@parallaxsw.com>
This commit is contained in:
James Cherry 2024-10-21 11:33:11 -07:00
parent 1dbcb32923
commit a2d445b00a
1 changed files with 3 additions and 12 deletions
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15
verilog/VerilogWriter.cc
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@ -66,8 +66,7 @@ protected:
bool &first_member);
void writeAssigns(const Instance *inst);
int findUnconnectedNetCount();
int findNCcount(const Instance *inst);
int findUnconnectedNetCount(const Instance *inst);
int findChildNCcount(const Instance *child);
int findPortNCcount(const Instance *inst,
const Port *port);
@ -304,7 +303,7 @@ VerilogWriter::writeWireDcls(const Instance *inst)
}
// Wire net dcls for writeInstBusPinBit.
int nc_count = findUnconnectedNetCount();
int nc_count = findUnconnectedNetCount(inst);
for (int i = 1; i < nc_count + 1; i++)
fprintf(stream_, " wire _NC%d;\n", i);
}
@ -469,16 +468,8 @@ VerilogWriter::writeAssigns(const Instance *inst)
////////////////////////////////////////////////////////////////
// Walk the hierarchy counting unconnected nets used to connect to
// bus ports with concatenation.
int
VerilogWriter::findUnconnectedNetCount()
{
return findNCcount(network_->topInstance());
}
int
VerilogWriter::findNCcount(const Instance *inst)
VerilogWriter::findUnconnectedNetCount(const Instance *inst)
{
int nc_count = 0;
InstanceChildIterator *child_iter = network_->childIterator(inst);