enhance verilog reader to support uninstantiated modules

Signed-off-by: Cho Moon <cmoon@precisioninno.com>

include/sta/ConcreteNetwork.hh

@@ -59,7 +59,8 @@ public:
   void clear() override;
   bool linkNetwork(const char *top_cell_name,
                    bool make_black_boxes,
-                   Report *report) override;
+                   Report *report,
+                   bool use_top_cell_name) override;
   Instance *topInstance() const override;
 
   const char *name(const Library *library) const override;

include/sta/Network.hh

@@ -37,6 +37,7 @@ typedef Map<const char*, LibertyLibrary*, CharPtrLess> LibertyLibraryMap;
 typedef Instance *(LinkNetworkFunc)(const char *top_cell_name,
 				    bool make_black_boxes,
 				    Report *report,
+                                    bool use_top_cell_name,
 				    NetworkReader *network);
 typedef Map<const Net*, PinSet*> NetDrvrPinsMap;
 
@@ -96,7 +97,8 @@ public:
   // Return true if successful.
   virtual bool linkNetwork(const char *top_cell_name,
 			   bool make_black_boxes,
-			   Report *report) = 0;
+			   Report *report,
+                           bool use_top_cell_name = false) = 0;
   virtual bool isLinked() const;
   virtual bool isEditable() const { return false; }
 

include/sta/SdcNetwork.hh

@@ -30,7 +30,8 @@ public:
   NetworkNameAdapter(Network *network);
   bool linkNetwork(const char *top_cell_name,
                    bool make_black_boxes,
-                   Report *report) override;
+                   Report *report,
+                   bool use_top_cell_name) override;
 
   const char *name(const Library *library) const override;
   ObjectId id(const Library *library) const override;

network/ConcreteNetwork.cc

@@ -1959,12 +1959,13 @@ ConcreteNetwork::setLinkFunc(LinkNetworkFunc *link)
 bool
 ConcreteNetwork::linkNetwork(const char *top_cell_name,
 			     bool make_black_boxes,
-			     Report *report)
+			     Report *report,
+                             bool use_top_cell_name)
 {
   if (link_func_) {
     clearConstantNets();
     deleteTopInstance();
-    top_instance_ = link_func_(top_cell_name, make_black_boxes, report, this);
+    top_instance_ = link_func_(top_cell_name, make_black_boxes, report, use_top_cell_name, this);
     if (top_instance_)
       checkNetworkLibertyCorners();
     return top_instance_ != nullptr;

network/SdcNetwork.cc

@@ -41,9 +41,10 @@ NetworkNameAdapter::NetworkNameAdapter(Network *network) :
 bool
 NetworkNameAdapter::linkNetwork(const char *top_cell_name,
 				bool make_black_boxes,
-				Report *report)
+				Report *report,
+                                bool use_top_cell_name)
 {
-  return network_->linkNetwork(top_cell_name, make_black_boxes, report);
+  return network_->linkNetwork(top_cell_name, make_black_boxes, report, use_top_cell_name);
 }
 
 Instance *

verilog/VerilogReader.cc

@@ -48,6 +48,7 @@ Instance *
 linkVerilogNetwork(const char *top_cell_name,
 		   bool make_black_boxes,
 		   Report *report,
+                   bool use_top_cell_name,
 		   NetworkReader *network);
 
 bool
@@ -1790,9 +1791,11 @@ Instance *
 linkVerilogNetwork(const char *top_cell_name,
 		   bool make_black_boxes,
 		   Report *report,
+                   bool use_top_cell_name,
 		   NetworkReader *)
 {
-  return verilog_reader->linkNetwork(top_cell_name, make_black_boxes, report);
+  return verilog_reader->linkNetwork(top_cell_name, make_black_boxes, report,
+                                     use_top_cell_name);
 }
 
 // Verilog net name to network net map.
@@ -1820,14 +1823,16 @@ private:
 Instance *
 VerilogReader::linkNetwork(const char *top_cell_name,
 			   bool make_black_boxes,
-			   Report *report)
+			   Report *report,
+                           bool use_top_cell_name)
 {
   if (library_) {
     Cell *top_cell = network_->findCell(library_, top_cell_name);
     VerilogModule *module = this->module(top_cell);
     if (module) {
       // Seed the recursion for expansion with the top level instance.
-      Instance *top_instance = network_->makeInstance(top_cell, "", nullptr);
+      Instance *top_instance = network_->makeInstance(top_cell,
+        (use_top_cell_name ? top_cell_name : ""), nullptr);
       VerilogBindingTbl bindings(zero_net_name_, one_net_name_);
       VerilogNetSeq::Iterator port_iter(module->ports());
       while (port_iter.hasNext()) {
@@ -1848,7 +1853,7 @@ VerilogReader::linkNetwork(const char *top_cell_name,
       }
       makeModuleInstBody(module, top_instance, &bindings, make_black_boxes);
       bool errors = reportLinkErrors(report);
-      deleteModules();
+      // deleteModules();
       if (errors) {
 	network_->deleteInstance(top_instance);
 	return nullptr;

verilog/VerilogReaderPvt.hh

@@ -156,7 +156,8 @@ public:
   VerilogModule *module(Cell *cell);
   Instance *linkNetwork(const char *top_cell_name,
 			bool make_black_boxes,
-			Report *report);
+			Report *report,
+                        bool use_top_cell_name = false);
   int line() const { return line_; }
   const char *filename() const { return filename_; }
   void incrLine();