Commit Graph

8 Commits

Author SHA1 Message Date
Jaehyun Kim b6d598a119 test: strengthen assertions, add sorted SDC diff, and clean up tests
- Add diff_files_sorted to test/helpers.tcl for hash-order-independent
  SDC comparison (fixes non-deterministic write_sdc output ordering)
- Use diff_files_sorted in sdc_derate_disable_deep and
  sdc_port_delay_advanced tests
- Remove stale coverage percentages from test comments (Comment 1)
- Remove unnecessary catch blocks in search property tests (Comment 3)
- Strengthen load-only tests with actual data verification (Comment 8)
- Remove orphan .ok files for deleted monolithic tests (Comment 9)
- Add golden .sdcok/.libok/.vok/.sdfok files for SDC/liberty/verilog
  write-and-diff tests
- Add -B (clean rebuild) option to make_coverage_report.sh
- Replace (void) casts and EXPECT_TRUE(true) with real assertions in
  TestSdc.cc and TestVerilog.cc

Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
Signed-off-by: Jaehyun Kim <jhkim@precisioninno.com>
2026-02-23 11:50:23 +09:00
Jaehyun Kim 98e00b0348 test: Delete dead code from Tcl tests and remove broken write_gate_spice tests
Remove dead code blocks that reference non-exposed Tcl commands (e.g.,
sta::find_pi_pole_residue) and delete all write_gate_spice catch blocks
from spice tests since write_gate_spice_cmd SWIG binding is missing,
making all write_gate_spice calls always fail. Added bug report for the
missing binding. All 6531 tests pass.

Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
2026-02-20 21:40:50 +09:00
Jaehyun Kim 2d2762437a test: Remove unnecessary catch blocks from Tcl tests across all modules
Remove bare catch blocks that silently swallowed errors instead of
properly testing them. Fix underlying issues revealed by catch removal
including wrong API calls ([$role name] on strings, invalid properties
like cell_leakage_power/is_register, nonexistent Tcl bindings) and
incorrect library names. Update golden .ok files to match new output.

Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
2026-02-20 21:07:40 +09:00
Jaehyun Kim 726a64a961 test: Add explanatory comments to all catch blocks in Tcl tests
Document why each catch block is needed across 48 test files,
covering liberty, search, sdc, spice, network, parasitics, util,
and verilog modules.

Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
2026-02-20 15:39:36 +09:00
Jaehyun Kim e57c8043cd test: Apply review feedback - part3
Remove unnecessary catch blocks from Tcl test files across all modules,
add report_checks after each set_wire_load_model in liberty_wireload,
rewrite liberty_sky130_corners for actual multi-corner timing analysis
with define_corners, and expand C++ tests (TestSearchIncremental 8→36,
TestPower 71→96, TestSpice 98→126 tests).

Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
2026-02-20 13:05:07 +09:00
Jaehyun Kim 547737f71e test: Apply review feedback - part2
- Remove stale line-number coverage comments (# Targets: line NNN, hit=0)
- Remove useless file-existence checks from verilog/sdf tests
- Delete 21 orphaned dcalc Tcl tests (C++ tests already cover them)
- Rename liberty_ccsn_ecsm -> liberty_ccsn (no ECSM libs available)
- Fix liberty_sky130_corners to use define_corners/-corner for real multi-corner testing
- Add report_checks per wireload model in liberty_wireload
- Fix test/regression to work from test/ directory (label mismatch)
- Refactor all module CMakeLists.txt with sta_module_tests() macro

Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
2026-02-20 01:13:42 +09:00
Jaehyun Kim 6799b1909a test: Apply review feedback - part1
Signed-off-by: Jaehyun Kim <jhkim@precisioninno.com>
2026-02-19 23:30:23 +09:00
Jaehyun Kim d6c09372ba test: Initial upload
Signed-off-by: Jaehyun Kim <jhkim@precisioninno.com>
2026-02-13 19:19:09 +09:00