James Cherry
|
6ac93c8c7d
|
vertex_pin -> leaf_pin
|
2019-10-25 08:51:59 -07:00 |
|
James Cherry
|
37ee851943
|
sync
|
2019-09-17 17:48:11 -06:00 |
|
James Cherry
|
f9bc74e962
|
format_distance, area
|
2019-08-16 17:34:48 -07:00 |
|
James Cherry
|
9d93130ff2
|
range iterators
|
2019-07-18 06:19:00 -07:00 |
|
James Cherry
|
fa849908d7
|
set_cmd_units
|
2019-07-08 11:50:41 -07:00 |
|
James Cherry
|
db6b650a52
|
splash include git sha1
|
2019-07-07 09:58:47 -07:00 |
|
James Cherry
|
eb9fdd1be0
|
write verilog match liberty bus bit order
|
2019-07-02 07:07:34 -07:00 |
|
James Cherry
|
389b9b8276
|
set_data_check no -setup|-hold
|
2019-06-26 15:58:23 -07:00 |
|
James Cherry
|
11aa6e759a
|
tclListSeqLibertyCell
|
2019-06-23 21:59:02 -07:00 |
|
James Cherry
|
b9a7b349eb
|
template tcl typemap(in) seqs/sets
|
2019-06-22 11:17:13 -07:00 |
|
James Cherry
|
78fa68cc7a
|
TclListSeqLibertyLibrary
|
2019-06-21 21:42:45 -07:00 |
|
James Cherry
|
5f23536b17
|
support equiv cells across libraries
|
2019-06-20 21:41:49 -07:00 |
|
James Cherry
|
1def4110c0
|
report_power NaN
|
2019-06-19 07:55:04 -07:00 |
|
James Cherry
|
1a84830895
|
sta::worst_slack args, sta to verilog name args
|
2019-06-18 15:52:12 -07:00 |
|
James Cherry
|
de34f8b6b2
|
report_tns/wns
|
2019-06-05 10:20:48 -07:00 |
|
James Cherry
|
61b1ac4d12
|
sync
|
2019-06-04 08:12:22 -07:00 |
|
James Cherry
|
736a977a6d
|
Liberty equiv cells in LibertyCell instead of map
|
2019-05-28 07:45:05 -07:00 |
|
James Cherry
|
53df9472d7
|
resizer support
|
2019-05-27 22:46:24 -07:00 |
|
James Cherry
|
8242035b22
|
LibertyCell::isBuffer()
|
2019-05-25 20:02:33 -07:00 |
|
James Cherry
|
6a194ef6ee
|
LibertyCell::higherDrive(), slowerDrive()
|
2019-05-25 17:08:53 -07:00 |
|
James Cherry
|
a988588dac
|
sync
|
2019-05-19 17:06:06 -06:00 |
|
James Cherry
|
d1a602cefc
|
2.0.15
|
2019-04-29 08:39:05 -07:00 |
|
James Cherry
|
12ca613886
|
2.0.14
|
2019-04-18 18:01:10 -07:00 |
|
James Cherry
|
fcfec7ae54
|
2.0.13
|
2019-04-01 09:05:07 -07:00 |
|
James Cherry
|
e141c83b2e
|
cmakefile
|
2019-03-24 23:04:20 -07:00 |
|
James Cherry
|
e5c9bc43fd
|
2.0.10
|
2019-03-12 17:25:53 -07:00 |
|
James Cherry
|
0f2dba7eff
|
sync
|
2019-02-26 08:26:12 -08:00 |
|
James Cherry
|
bbd18d7bed
|
report_power -instances *
|
2019-02-16 15:31:39 -08:00 |
|
James Cherry
|
d8146af755
|
remove autotools/configure support
|
2019-02-16 12:07:59 -08:00 |
|
James Cherry
|
9bf1591d62
|
2.0.6
|
2019-01-28 09:31:56 -08:00 |
|
James Cherry
|
3f65204717
|
2.0.6
|
2019-01-26 23:03:01 -08:00 |
|
James Cherry
|
92f4968feb
|
write_path_spice bug fixes
|
2019-01-20 09:44:24 -08:00 |
|
James Cherry
|
316742202f
|
sync
|
2019-01-16 15:37:31 -08:00 |
|
James Cherry
|
3d8d088b89
|
sync
|
2019-01-05 16:09:27 -08:00 |
|
James Cherry
|
9e5aac37f4
|
cmake, write_path_spice
|
2019-01-03 16:14:15 -08:00 |
|
James Cherry
|
b075ccc783
|
update copyright
|
2019-01-01 12:26:11 -08:00 |
|
James Cherry
|
9435640d5a
|
write_spice alpha
|
2019-01-01 12:25:25 -08:00 |
|
James Cherry
|
a6e21377e6
|
2.0.2
|
2018-12-26 11:03:31 -08:00 |
|
James Cherry
|
4f381f6669
|
2018/12/24 all_fanout from input port
|
2018-12-24 13:07:10 -08:00 |
|
James Cherry
|
0a693f3236
|
get_prpperty PathEnd points, PathRef arrival, required, slack, pin
|
2018-12-21 09:15:32 -08:00 |
|
James Cherry
|
e1059eac12
|
find_timing_paths
|
2018-12-20 22:41:54 -08:00 |
|
James Cherry
|
b8c43f0e93
|
sync
|
2018-12-13 23:53:17 -08:00 |
|
James Cherry
|
d84c24882b
|
sync
|
2018-12-11 10:47:04 -08:00 |
|
James Cherry
|
f49dc75d32
|
sync
|
2018-12-05 14:18:41 -08:00 |
|
James Cherry
|
ddf897d4e6
|
report_power, pocv support
|
2018-11-26 09:15:52 -08:00 |
|
James Cherry
|
e9bde796ec
|
2018/11/08 corners > 2 causes internal error, 2018/11/09 Verilog ignore attributes (* blah *)
|
2018-11-09 10:04:16 -08:00 |
|
James Cherry
|
d0ca009460
|
sync
|
2018-10-23 16:28:41 -07:00 |
|
James Cherry
|
e68203dcf4
|
^/v for arc display
|
2018-10-02 16:20:18 -07:00 |
|
James Cherry
|
1154fb89fd
|
and then there was light...
|
2018-09-28 08:54:21 -07:00 |