James Cherry
|
b57fcf173e
|
leaks
|
2020-09-05 17:20:21 -07:00 |
|
James Cherry
|
ee326f165c
|
public headers in include/sta
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2020-04-05 14:53:44 -07:00 |
|
James Cherry
|
804953e317
|
mv public headers to include/sta
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2020-04-05 11:35:51 -07:00 |
|
James Cherry
|
4a017e86eb
|
update copyright
|
2020-03-06 18:50:37 -08:00 |
|
James Cherry
|
5edc2ba7ef
|
groupBusPorts: sort memebers by bus index
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2020-02-01 17:38:33 -07:00 |
|
James Cherry
|
435bc2ba98
|
write_verilog bus ports missing bits
|
2019-12-09 16:57:18 -07:00 |
|
James Cherry
|
0c97a10f9a
|
network external cell/port member vars
|
2019-11-13 14:58:38 -07:00 |
|
James Cherry
|
3ae920be7d
|
write_verilog escaped bus name
|
2019-08-13 21:34:35 -07:00 |
|
James Cherry
|
93f5f9d664
|
no need for virtuals in Concrete network objects
|
2019-06-28 13:38:56 -07:00 |
|
James Cherry
|
88331ab9b1
|
Network bus brkts use library values
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2019-06-28 11:51:43 -07:00 |
|
James Cherry
|
96fcf1d8b2
|
ConcreteCell/Port pointers to corresponding liberty
|
2019-06-15 22:20:54 -07:00 |
|
James Cherry
|
2d519b4740
|
ucsd 20190410 seg fault accessing/setting power_default_signal_toggle_rate
|
2019-04-10 20:36:48 -07:00 |
|
James Cherry
|
e5c9bc43fd
|
2.0.10
|
2019-03-12 17:25:53 -07:00 |
|
James Cherry
|
dae85f08e0
|
misspelled "Deescription", gcc warnings
|
2019-03-03 17:50:56 -08:00 |
|
James Cherry
|
d8146af755
|
remove autotools/configure support
|
2019-02-16 12:07:59 -08:00 |
|
James Cherry
|
316742202f
|
sync
|
2019-01-16 15:37:31 -08:00 |
|
James Cherry
|
b075ccc783
|
update copyright
|
2019-01-01 12:26:11 -08:00 |
|
James Cherry
|
1154fb89fd
|
and then there was light...
|
2018-09-28 08:54:21 -07:00 |