* Add read_vcd -begin_time/-end_time activity windowing.
Limit VCD transition and duty counting to an optional time window so
activity annotation can ignore regions outside the interval of interest.
Co-authored-by: Cursor <[email protected]>
* Format VcdCount::setFilter parameters one per line.
Co-authored-by: Cursor <[email protected]>
* Address VCD begin/end review: VcdTime, sentinel, rename.
Use VcdTime and vcd_null_time instead of int64_t/-1, rename
VcdCount filter bounds to begin/end_time, rename the regression to
vcd_begin_end_time, and document read_vcd -begin_time/-end_time in
ChangeLog.txt.
Co-authored-by: Cursor <[email protected]>
---------
Co-authored-by: Cursor <[email protected]>
Co-authored-by: James Cherry <[email protected]>
* write_path_spice: match side input values to the path arc's transitions
gatePortValues() chose side input values from the first CUDD cube of the
Boolean difference d(f)/d(input), which sensitizes the gate but ignores
the transition directions of the arc the path used:
- For non-unate gates whose Boolean difference is a tautology (xor2,
xnor2) every side variable came back don't-care, and the unknown value
fell through to tie-low in writeSubcktInstVoltSrcs() -- wrong whenever
the path used the when-condition requiring the side high.
- For mux select arcs the cube was an arbitrary data assignment,
unrelated to the output edge the path reported.
Either way the written deck's gate drives the opposite direction from
the reported path: the simulated chain switches with inverted polarity
from that gate onward, edge-qualified arrival measurements fail, and
the deck sums delays from the wrong rise/fall tables.
Constrain the side input condition to the cofactor pair matching this
arc -- f1 & !f0 when the input and driver edges agree (non-inverting),
f0 & !f1 when they differ (inverting) -- threading the gate input
RiseFall from the path stage into gatePortValues(). Also release the
CUDD nodes that were previously leaked (the old code Cudd_Ref'd the
Boolean difference after the generator was freed and never deref'd it).
Fixes#474
Co-Authored-By: Claude Fable 5 <[email protected]>
* test: write_path_spice
arc-sense regression for #474, and outlined in #475
---------
Co-authored-by: Brian Degnan <[email protected]>
Co-authored-by: Claude Fable 5 <[email protected]>
* support for filter in get_scene/mode
Signed-off-by: dsengupta0628 <[email protected]>
* extend user defined property to all 10 objects
Signed-off-by: dsengupta0628 <[email protected]>
* address reviews
Signed-off-by: dsengupta0628 <[email protected]>
---------
Signed-off-by: dsengupta0628 <[email protected]>
* support for filter in get_scene/mode
Signed-off-by: dsengupta0628 <[email protected]>
* defineProperty overload
Signed-off-by: dsengupta0628 <[email protected]>
* define and set user property
Signed-off-by: dsengupta0628 <[email protected]>
* address review comments to generalize- current support for mode and scene
Signed-off-by: dsengupta0628 <[email protected]>
* address second round comments- removed user from cmd names
Signed-off-by: dsengupta0628 <[email protected]>
* remove defaults, check property vals against type defined
Signed-off-by: dsengupta0628 <[email protected]>
* address reviews, indent
Signed-off-by: dsengupta0628 <[email protected]>
* indent fix
Signed-off-by: dsengupta0628 <[email protected]>
---------
Signed-off-by: dsengupta0628 <[email protected]>
* Update STA to exclude bias pins from timing graph and subsequently in write_verilog
Signed-off-by: dsengupta0628 <[email protected]>
* unnecessary space in orig verilog
Signed-off-by: dsengupta0628 <[email protected]>
* Update to use well supplies rather than bias pins
Signed-off-by: dsengupta0628 <[email protected]>
---------
Signed-off-by: dsengupta0628 <[email protected]>
* feat(ci): add GitHub Action for push and pull request
* fix(ci): fix broken testcases
* chore: add CODEOWNERS for ci
* ci: bump actions/upload-artifact from 6 to 7
* a
* Revert "a"
This reverts commit 2717585799dc829618bc523a4b1525df2a298cf1.
* bus issue
* reverse string to match vcd bits
* requested changes
* clearer
* this makes more sense
* revert
* comment
* add test case
* Add parser support for specify blocks and specparam
Treated like regular parameters, and so ignored
* Add regression test
* Apply PR feedback
* missed the verilog_lang
Deepashree Sengupta
James Cherry
Drew Lewis
James Cherry
Deepashree Sengupta
Kazuto Iris
nataliakokoromyti
Stan Lee
ambd161