Bias pin handling (#409)

* Update STA to exclude bias pins from timing graph and subsequently in write_verilog

Signed-off-by: dsengupta0628 <[email protected]>

* unnecessary space in orig verilog

Signed-off-by: dsengupta0628 <[email protected]>

* Update to use well supplies rather than bias pins

Signed-off-by: dsengupta0628 <[email protected]>

---------

Signed-off-by: dsengupta0628 <[email protected]>

test/regression_vars.tcl

@@ -165,6 +165,7 @@ record_public_tests {
   report_json2
   suppress_msg
   verilog_attribute
+  verilog_well_supplies
   verilog_specify
   verilog_write_escape
   verilog_unconnected_hpin

test/verilog_well_supplies.ok

@@ -0,0 +1,26 @@
+module top (y,
+    a);
+ output y;
+ input a;
+
+
+ sky130_fd_sc_hd__buf_1 u1 (.A(a),
+    .X(y));
+endmodule
+module top (y,
+    a);
+ output y;
+ input a;
+
+ wire VGND;
+ wire VNB;
+ wire VPB;
+ wire VPWR;
+
+ sky130_fd_sc_hd__buf_1 u1 (.VGND(VGND),
+    .VNB(VNB),
+    .VPB(VPB),
+    .VPWR(VPWR),
+    .A(a),
+    .X(y));
+endmodule

test/verilog_well_supplies.tcl

@@ -0,0 +1,12 @@
+# Check that write_verilog excludes well pins along with power/ground pins.
+source helpers.tcl
+read_liberty ../examples/sky130hd_tt.lib.gz
+read_verilog verilog_well_supplies.v
+link_design top
+set verilog_file [make_result_file "verilog_well_supplies.v"]
+write_verilog $verilog_file
+report_file $verilog_file
+
+set verilog_pwr_file [make_result_file "verilog_well_supplies_pwr.v"]
+write_verilog -include_pwr_gnd $verilog_pwr_file
+report_file $verilog_pwr_file

test/verilog_well_supplies.v

@@ -0,0 +1,17 @@
+module top (
+    output y,
+    input  a
+);
+  supply1 VPWR;
+  supply0 VGND;
+  supply1 VPB;
+  supply0 VNB;
+  sky130_fd_sc_hd__buf_1 u1 (
+      .X(y),
+      .A(a),
+      .VPWR(VPWR),
+      .VGND(VGND),
+      .VPB(VPB),
+      .VNB(VNB)
+  );
+endmodule