Remove bare catch blocks that silently swallowed errors instead of
properly testing them. Fix underlying issues revealed by catch removal
including wrong API calls ([$role name] on strings, invalid properties
like cell_leakage_power/is_register, nonexistent Tcl bindings) and
incorrect library names. Update golden .ok files to match new output.
Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
Document why each catch block is needed across 48 test files,
covering liberty, search, sdc, spice, network, parasitics, util,
and verilog modules.
Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
Remove unnecessary catch blocks in network, parasitics, sdc, spice,
and util test modules. Add report_checks after set_wire_load_model
in parasitics_wireload.tcl to verify timing changes per wireload.
Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
Remove unnecessary catch blocks from Tcl test files across all modules,
add report_checks after each set_wire_load_model in liberty_wireload,
rewrite liberty_sky130_corners for actual multi-corner timing analysis
with define_corners, and expand C++ tests (TestSearchIncremental 8→36,
TestPower 71→96, TestSpice 98→126 tests).
Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
- Remove stale line-number coverage comments (# Targets: line NNN, hit=0)
- Remove useless file-existence checks from verilog/sdf tests
- Delete 21 orphaned dcalc Tcl tests (C++ tests already cover them)
- Rename liberty_ccsn_ecsm -> liberty_ccsn (no ECSM libs available)
- Fix liberty_sky130_corners to use define_corners/-corner for real multi-corner testing
- Add report_checks per wireload model in liberty_wireload
- Fix test/regression to work from test/ directory (label mismatch)
- Refactor all module CMakeLists.txt with sta_module_tests() macro
Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
Jaehyun Kim