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356 Commits

Author SHA1 Message Date
Jaehyun Kim 2d2762437a test: Remove unnecessary catch blocks from Tcl tests across all modules 
Remove bare catch blocks that silently swallowed errors instead of
properly testing them. Fix underlying issues revealed by catch removal
including wrong API calls ([$role name] on strings, invalid properties
like cell_leakage_power/is_register, nonexistent Tcl bindings) and
incorrect library names. Update golden .ok files to match new output.

Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
 2026-02-20 21:07:40 +09:00
Jaehyun Kim 726a64a961 test: Add explanatory comments to all catch blocks in Tcl tests 
Document why each catch block is needed across 48 test files,
covering liberty, search, sdc, spice, network, parasitics, util,
and verilog modules.

Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
 2026-02-20 15:39:36 +09:00
Jaehyun Kim ce45133c84 test: Fix wrong API calls in Tcl tests and remove unnecessary catches 
Replace wrong/non-existent command calls with correct OpenSTA APIs:
- sta::pin_slack → get_property $pin slack_max_rise
- sta::slow_drivers_cmd → sta::slow_drivers
- set_latch_borrow_limit → set_max_time_borrow
- remove_data_check → unset_data_check
- remove_clock → delete_clock
- reset_path → unset_path_exceptions
- sta::report_path_end 3-arg → sta::report_path_end2
- sta::design_power "NULL" → sta::design_power [sta::cmd_corner]
- report_path $path → sta::report_path_cmd $path
- connect_pin 3-arg → connect_pin net inst/port
- set_power_activity positional → -input_ports flag
- sta::is_clock [get_ports] → sta::is_clock [sta::get_port_pin]
- get_property $inst lib_name → liberty_cell/liberty_library
- get_property $pin net_name → [$pin net] + get_full_name
- get_property $net is_power → $net is_power method
- Removed unnecessary catch around sta::write_liberty

23 catch blocks removed. Tests now execute real API calls instead
of silently failing.

Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
 2026-02-20 15:32:08 +09:00
Jaehyun Kim 5c9b4d7a15 test: Apply review feedback - part3 
Remove unnecessary catch blocks across all test modules (graph,
liberty, network, parasitics, power, sdc, sdf, search, spice,
verilog), expand C++ tests (TestSearchIncremental 8→36 tests,
TestPower 71→96, TestSpice 98→126), add report_checks after each
set_wire_load_model in liberty_wireload.tcl, and rewrite
liberty_sky130_corners.tcl with actual multi-corner timing analysis.

Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
 2026-02-20 13:46:30 +09:00
Jaehyun Kim e57c8043cd test: Apply review feedback - part3 
Remove unnecessary catch blocks from Tcl test files across all modules,
add report_checks after each set_wire_load_model in liberty_wireload,
rewrite liberty_sky130_corners for actual multi-corner timing analysis
with define_corners, and expand C++ tests (TestSearchIncremental 8→36,
TestPower 71→96, TestSpice 98→126 tests).

Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
 2026-02-20 13:05:07 +09:00
Jaehyun Kim 547737f71e test: Apply review feedback - part2 
- Remove stale line-number coverage comments (# Targets: line NNN, hit=0)
- Remove useless file-existence checks from verilog/sdf tests
- Delete 21 orphaned dcalc Tcl tests (C++ tests already cover them)
- Rename liberty_ccsn_ecsm -> liberty_ccsn (no ECSM libs available)
- Fix liberty_sky130_corners to use define_corners/-corner for real multi-corner testing
- Add report_checks per wireload model in liberty_wireload
- Fix test/regression to work from test/ directory (label mismatch)
- Refactor all module CMakeLists.txt with sta_module_tests() macro

Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
 2026-02-20 01:13:42 +09:00
Jaehyun Kim 6799b1909a test: Apply review feedback - part1 
Signed-off-by: Jaehyun Kim <jhkim@precisioninno.com>
 2026-02-19 23:30:23 +09:00
Jaehyun Kim b77779f7a6 test: Refactoring. Standardize Google Test naming conventions by removing `R#_` prefixes, improve temporary file creation with `mkstemp`, etc 
Signed-off-by: Jaehyun Kim <jhkim@precisioninno.com>
 2026-02-13 20:36:42 +09:00
Jaehyun Kim d6c09372ba test: Initial upload 
Signed-off-by: Jaehyun Kim <jhkim@precisioninno.com>
 2026-02-13 19:19:09 +09:00
Matt Liberty e872c55bfe Merge remote-tracking branch 'parallax/master' 2026-02-05 04:12:23 +00:00
James Cherry cde32a1572 leakage power well pg pin resolves #377 
Signed-off-by: James Cherry <cherry@parallaxsw.com>
 2026-02-04 16:50:28 -07:00
Matt Liberty ec62b3a5b9 Merge remote-tracking branch 'parallax/master' 2026-02-04 07:51:04 +00:00
James Cherry 3136871ecd LibertyCell::isClockGateLatchNegedge resolves #375 
Signed-off-by: James Cherry <cherry@parallaxsw.com>
 2026-02-03 08:33:46 -07:00
James Cherry 87ea907884 defineScalingFactorVisitors min_pulse_width resolves #376 
Signed-off-by: James Cherry <cherry@parallaxsw.com>
 2026-02-03 08:18:41 -07:00
Matt Liberty 4966240d28 Merge remote-tracking branch 'parallax/master' 2026-01-09 18:28:40 +00:00
James Cherry 6ef25d488a more unit issues 
Signed-off-by: James Cherry <cherry@parallaxsw.com>
 2025-12-05 14:47:16 -07:00
James Cherry e8c7a6541b more unit fallout 
Signed-off-by: James Cherry <cherry@parallaxsw.com>
 2025-12-05 09:51:15 -07:00
Matt Liberty eb8ab089df Merge remote-tracking branch 'parallax/master' 2025-11-25 16:53:40 +00:00
Matt Liberty 574379eb32
rm stray semicolon (#338) 
Signed-off-by: Matt Liberty <mliberty@precisioninno.com>
 2025-11-21 07:01:39 -08:00
Matt Liberty 1d6e79a327 Merge remote-tracking branch 'upstream/master' 2025-11-18 06:35:29 +00:00
Logikable c4b94c3ee5
Add missing system header includes. (#330) 
Signed-off-by: Sean Luchen <seanluchen@google.com>
 2025-11-17 09:23:32 -08:00
Akash Levy 16a92707fb
Fix `isBuffer` (#329) 
* Add support for "well" direction type (nwell, pwell, etc.), and fix isBuffer (+ other functions) to accommodate wells

* Just fix isBuffer issue
 2025-11-16 15:34:37 -08:00
Matt Liberty 7b4cea532b Merge remote-tracking branch 'upstream/master' 2025-11-13 03:32:56 +00:00
James Cherry cf903f4db6 suppress rapidus liberty warning 
Signed-off-by: James Cherry <cherry@parallaxsw.com>
 2025-11-09 08:23:53 -07:00
James Cherry 8287aec5f6 Verilog make pins for liberty pg_pins resolves #326 
commit b4a89c93965c49a8685fd41cb6aee10635d7a7f3
Author: James Cherry <cherry@parallaxsw.com>
Date:   Fri Nov 7 11:48:10 2025 -0700

    pg_ -> PwrGnd

    Signed-off-by: James Cherry <cherry@parallaxsw.com>

commit 12ddba4bf220cec8459c15e483a871b13e507bf2
Author: James Cherry <cherry@parallaxsw.com>
Date:   Fri Nov 7 08:56:02 2025 -0700

    pg_port

    Signed-off-by: James Cherry <cherry@parallaxsw.com>

Signed-off-by: James Cherry <cherry@parallaxsw.com>
 2025-11-07 11:55:43 -07:00
Matt Liberty d7cb9be1ca Merge remote-tracking branch 'upstream/master' 2025-11-07 04:44:07 +00:00
James Cherry 351b8287a7 issue 322 revisited 
Signed-off-by: James Cherry <cherry@parallaxsw.com>
 2025-11-06 12:34:53 -07:00
Matt Liberty 2412feec33
pad cells are not buffers or inverters (#294) 
Signed-off-by: Matt Liberty <mliberty@precisioninno.com>
 2025-09-08 17:04:21 -07:00
Matt Liberty e475ee2c98 Merge remote-tracking branch 'upstream/master' 
Signed-off-by: Matt Liberty <mliberty@precisioninno.com>
 2025-09-03 23:00:11 +00:00
Matt Liberty 5e1cecc38b pad cells are not buffers or inverters 
Signed-off-by: Matt Liberty <mliberty@precisioninno.com>
 2025-09-02 17:42:06 +00:00
James Cherry b654fd48a8 read_liberty leak resolves ORFS#1184 
Signed-off-by: James Cherry <cherry@parallaxsw.com>
 2025-08-20 16:00:33 -07:00
Matt Liberty 2c33fb5583 Merge remote-tracking branch 'parallax/master' 2025-08-04 04:38:33 +00:00
Akash Levy 2e903ab4da
Allow Liberty floats as strings for `voltage_map` and `capacitive_load_unit` (#280) 
* Allow Liberty floats as strings for voltage_map and capacitive_load_unit

* Update liberty_float_as_str.lib

* Use valid bool

* Remove unused include
 2025-08-01 17:41:56 -07:00
Matt Liberty a74903cd3c Merge remote-tracking branch 'parallax/master' 2025-07-31 22:24:43 +00:00
Akash Levy ec3208bfbf
Allow backslash-EOL to end tokens in Liberty file (#279) 
* Allow backslash EOL to end tokens in Liberty file

* Update liberty_backslash_eol.lib

* Update liberty_backslash_eol.lib
 2025-07-31 12:19:36 -07:00
James Cherry 3620d7a259 liberty min_period timing group support resolves #275 
Signed-off-by: James Cherry <cherry@parallaxsw.com>
 2025-07-27 18:12:26 -07:00
James Cherry 0d7c89f544 cp liberty bus properties to bit ports resolves #273 
Signed-off-by: James Cherry <cherry@parallaxsw.com>
 2025-07-21 14:35:53 -07:00
Matt Liberty 06f94cafd8
Add a less operator to BddPortVarMap (#258) 
bdd_port_var_map_, of type BddPortVarMap, is iterated over in
Power::evalBddActivity.  Previously the map used pointer comparison so
the iteration order was non-deterministic.  The computed density was
therefore non-deterministic due to the non-associativity of
floating-point addition.

Signed-off-by: Matt Liberty <mliberty@precisioninno.com>
 2025-07-13 10:59:51 -07:00
James Cherry fa70c6cf2b read_spef incremental rm min/max reduced parasitics 
Signed-off-by: James Cherry <cherry@parallaxsw.com>
 2025-07-12 17:26:09 -07:00
Matt Liberty 966cdc80fb Merge remote-tracking branch 'parallax/master' 2025-07-09 19:02:06 +00:00
James Cherry 5e4ce2fd23 replace_cell equiv funcs, diff arcs resolves #267 
Signed-off-by: James Cherry <cherry@parallaxsw.com>
 2025-07-09 11:50:36 -07:00
James Cherry 606c666180 set_min/max_delay -from reg/D startpoint warning resolves #265 
Signed-off-by: James Cherry <cherry@parallaxsw.com>
 2025-07-03 17:08:44 -07:00
Matt Liberty 5ee1a31514 Merge remote-tracking branch 'parallax/master' 
Signed-off-by: Matt Liberty <mliberty@precisioninno.com>
 2025-06-24 14:57:14 +00:00
James Cherry c5b62b5cc8 liberty valgrind issues 
Signed-off-by: James Cherry <cherry@parallaxsw.com>
 2025-06-23 08:19:27 -07:00
James Cherry f3b785361d equiv cells only require timing arc equivs missing functions 
Signed-off-by: James Cherry <cherry@parallaxsw.com>
 2025-06-20 16:15:54 -07:00
Matt Liberty 522fc9563f Merge remote-tracking branch 'parallax/master' 
Signed-off-by: Matt Liberty <mliberty@precisioninno.com>
 2025-06-16 15:15:34 +00:00
James Cherry c2a0c4db30 liberty bundle ports apply func's to members resolves #256 
commit d7629119c261bbc1551f7a6b008475b194a9ff91
Author: James Cherry <cherry@parallaxsw.com>
Date:   Tue Jun 10 13:59:36 2025 +0200

    issue256

    Signed-off-by: James Cherry <cherry@parallaxsw.com>

Signed-off-by: James Cherry <cherry@parallaxsw.com>
 2025-06-16 16:45:21 +02:00
Matt Liberty fa0cdd6529 Merge https://github.com/parallaxsw/OpenSTA/pull/258 
Anticipating the merge to the upstream and trying to stabilize the OR CI.

Signed-off-by: Matt Liberty <mliberty@precisioninno.com>
 2025-06-15 05:31:12 +00:00
Matt Liberty b64d149ce5 Add a less operator to BddPortVarMap 
bdd_port_var_map_, of type BddPortVarMap, is iterated over in
Power::evalBddActivity.  Previously the map used pointer comparison so
the iteration order was non-deterministic.  The computed density was
therefore non-deterministic due to the non-associativity of
floating-point addition.

Signed-off-by: Matt Liberty <mliberty@precisioninno.com>
 2025-06-14 05:52:32 +00:00
James Cherry 343b93b633 min pulse width lib/sdf resolves #255 
Signed-off-by: James Cherry <cherry@parallaxsw.com>
 2025-06-06 20:36:59 -07:00