* Update STA to exclude bias pins from timing graph and subsequently in write_verilog
Signed-off-by: dsengupta0628 <dsengupta@precisioninno.com>
* unnecessary space in orig verilog
Signed-off-by: dsengupta0628 <dsengupta@precisioninno.com>
* Update to use well supplies rather than bias pins
Signed-off-by: dsengupta0628 <dsengupta@precisioninno.com>
---------
Signed-off-by: dsengupta0628 <dsengupta@precisioninno.com>
Revert error-on-mismatch back to return 1, as the new GitHub Action
(github-actions-are-differences-found) now detects "Differences found"
in CI output, making the error approach unnecessary.
Co-Authored-By: Claude <noreply@anthropic.com>
Signed-off-by: Jaehyun Kim <jhkim@precisioninno.com>
Previously these functions returned 1 on mismatch but no caller
checked the return value, allowing roundtrip failures to go
undetected. Now they call error() so the sta process exits
non-zero and the regression runner catches the failure.
Co-Authored-By: Claude <noreply@anthropic.com>
Signed-off-by: Jaehyun Kim <jhkim@precisioninno.com>
After merging upstream changes, fix all build errors in C++ test files
and regolden Tcl test golden files to match updated code output.
Build fixes:
- dcalc/test/cpp/TestDcalc.cc: Fix const char* loop iterations, use
EXPECT_NEAR for uninitialized subnormal float comparison
- liberty/test/cpp/TestLibertyStaBasicsB.cc: Wrap tests using removed
LibertyBuilder() default constructor in #if 0
- liberty/test/cpp/TestLibertyStaCallbacks.cc: Fix LibertyBuilder()
call to use sta_->debug()/report(); wrap old visitor tests in #if 0
- search/test/cpp/TestSearchStaDesignB.cc: Fix pg->name() nullptr
comparison (now returns std::string&)
- search/test/cpp/TestSearchStaInit.cc: Fix 5 clkPinsInvalid/isIdealClock
tests to expect throw (API now requires linked network)
Tcl test fixes:
- Remove calls to removed APIs: report_path_end_header/footer, report_path_end2
from 6 search test scripts; regolden their .ok files
- Regolden .ok files for liberty (15), graph (1), network (8),
parasitics (3), sdc (3), util (2), verilog (8) modules to reflect
upstream format changes (timing arcs output, pin ordering, spacing)
All 6103 tests now pass.
Signed-off-by: Jaehyun Kim <jhkim@precisioninno.com>
Update test code to match API changes from upstream master:
- TestGraph.cc: Fix makeScenes() call to pass reference instead of pointer
- TestLibertyClasses.cc: Fix ScaleFactorType wire_res/wire_cap name mapping;
fix TablePtr usage by calling .get() where const TableModel* is expected
- TestLibertyClasses.cc: Update liberty_read_nangate.ok for new timing arc output
- TestPower.cc: Replace PwrActivityOrigin::defaulted with ::unknown;
fix isSet() expectations (unknown origin returns false)
- TestSdcClasses.cc, TestSdf.cc, TestUtil.cc, TestSpice.cc:
Fix RiseFall::to_string() expected values from short form ("^"/"v")
to long form ("rise"/"fall")
- TestUtil.cc: Remove tests for deleted StringVector/split/TokenParser
and StringSet::deleteContents (removed from master)
- TestSpice.cc: Replace StdStringSeq with StringSeq
- helpers.tcl: Use pwd-based result_dir so module tests write results
to their own test/results/ directory
- verilog_bus.ok: Update golden file for new port ordering from master
Signed-off-by: Jaehyun Kim <jhkim@precisioninno.com>
* feat(ci): add GitHub Action for push and pull request
* fix(ci): fix broken testcases
* chore: add CODEOWNERS for ci
* ci: bump actions/upload-artifact from 6 to 7
dsengupta0628
James Cherry
Jaehyun Kim
Matt Liberty
Cho Moon
Vitor Bandeira
Deepashree Sengupta
Kazuto Iris