Renamed tests to match prlx repo, updated test to repro error without my fix

Signed-off-by: dsengupta0628 <dsengupta@precisioninno.com>

network/VerilogNamespace.cc

@@ -91,8 +91,8 @@ staToVerilog(const char *sta_name)
       escaped = true;
       char next_ch = s[1];
       if (next_ch == verilog_escape) {
-	escaped_name += next_ch;
-	s++;
+	      escaped_name += next_ch;
+	      s++;
       }
     }
     else {
@@ -126,8 +126,8 @@ staToVerilog2(const char *sta_name)
       escaped = true;
       char next_ch = s[1];
       if (next_ch == verilog_escape) {
-	escaped_name += next_ch;
-	s++;
+	      escaped_name += next_ch;
+	      s++;
       }
     }
     else {

test/regression_vars.tcl

@@ -163,9 +163,9 @@ record_public_tests {
   report_json1
   report_json2
   suppress_msg
-  test_write_verilog_escape
   verilog_attribute
   verilog_specify
+  verilog_write_escape
 }
 
 define_test_group fast [group_tests all]

test/verilog_write_escape.tcl

@@ -1,14 +1,14 @@
 # Check if "h1\x" and \Y[2:1] are correctly processed from input to output of Verilog
 read_liberty gf180mcu_sram.lib.gz
 read_liberty asap7_small.lib.gz
-read_verilog test_write_verilog_escape.v
+read_verilog verilog_write_escape.v
 link_design multi_sink
-write_verilog test_write_verilog_escape_out.v
-set input_file "test_write_verilog_escape_out.v"
-set fp [open $input_file r]
+set output_file "verilog_write_escape_out.v"
+write_verilog $output_file
+set fp [open $output_file r]
 while {[gets $fp line] >= 0} {
     puts $line
 }
 close $fp
-file delete "test_write_verilog_escape_out.v"
-
+read_verilog $output_file
+file delete $output_file

test/verilog_write_escape.v

@@ -1,4 +1,3 @@
-
 module \multi_sink (clk);
  input clk;
  wire \alu_adder_result_ex[0] ;
@@ -12,4 +11,3 @@ module \hier_block (childclk, \Y[2:1] );
    BUFx2_ASAP7_75t_R \abuf_$100  (.A(childclk));
    BUFx2_ASAP7_75t_R \ff0/name (.A(childclk));
 endmodule // hier_block1
-