update STA to Parallaxsw version on 4/7 with fix for issue 416 and some unrelated stuff
Signed-off-by: dsengupta0628 <dsengupta@precisioninno.com>
This commit is contained in:
dsengupta0628
commit
3eec04f4e8
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@ -236,7 +236,6 @@ private:
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int pin_n_;
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ArnoldiReduce *reduce_;
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delay_work *delay_work_;
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std::vector<rcmodel*> unsaved_parasitics_;
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};
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ArcDelayCalc *
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@ -247,6 +246,7 @@ makeArnoldiDelayCalc(StaState *sta)
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ArnoldiDelayCalc::ArnoldiDelayCalc(StaState *sta) :
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LumpedCapDelayCalc(sta),
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rcmodel_(nullptr),
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reduce_(new ArnoldiReduce(sta)),
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delay_work_(delay_work_create())
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{
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@ -267,6 +267,7 @@ ArnoldiDelayCalc::~ArnoldiDelayCalc()
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free(_delayV);
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free(_slewV);
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delete reduce_;
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delete rcmodel_;
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}
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Parasitic *
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@ -297,12 +298,11 @@ ArnoldiDelayCalc::findParasitic(const Pin *drvr_pin,
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}
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if (parasitic_network) {
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rcmodel *rcmodel = reduce_->reduceToArnoldi(parasitic_network, drvr_pin,
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parasitics->couplingCapFactor(),
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drvr_rf, scene, min_max);
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rcmodel_ = reduce_->reduceToArnoldi(parasitic_network, drvr_pin,
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parasitics->couplingCapFactor(),
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drvr_rf, scene, min_max);
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// Arnoldi parasitics are their own class that are not saved in the parasitic db.
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unsaved_parasitics_.push_back(rcmodel);
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parasitic = rcmodel;
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parasitic = rcmodel_;
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}
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return parasitic;
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}
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@ -321,9 +321,8 @@ ArnoldiDelayCalc::reduceParasitic(const Parasitic *,
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void
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ArnoldiDelayCalc::finishDrvrPin()
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{
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for (auto parasitic : unsaved_parasitics_)
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delete parasitic;
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unsaved_parasitics_.clear();
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delete rcmodel_;
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rcmodel_ = nullptr;
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}
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ArcDcalcResult
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@ -445,14 +445,13 @@ CcsCeffDelayCalc::findVlTime(double v,
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{
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double t_init = region_ramp_times_[0];
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double t_final = region_ramp_times_[region_count_];
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bool root_fail = false;
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double time = findRoot(
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[&](double t, double &y, double &dy) {
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vl(t, elmore, y, dy);
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y -= v;
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},
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t_init, t_final + elmore * 3.0, .001, 20, root_fail);
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vl_fail_ |= root_fail;
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auto [time, failed] =
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findRoot([&](double t, double &y, double &dy) {
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vl(t, elmore, y, dy);
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y -= v;
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},
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t_init, t_final + elmore * 3.0, .001, 20);
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vl_fail_ |= failed;
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return time;
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}
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815
dcalc/DmpCeff.cc
815
dcalc/DmpCeff.cc
File diff suppressed because it is too large
Load Diff
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@ -24,6 +24,9 @@
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#pragma once
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#include <optional>
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#include <utility>
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#include "LibertyClass.hh"
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#include "LumpedCapDelayCalc.hh"
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@ -71,13 +74,10 @@ protected:
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// Return values.
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double &wire_delay,
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double &load_slew) = 0;
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void gateDelaySlew(// Return values.
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double &delay,
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double &slew);
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void loadDelaySlewElmore(const Pin *load_pin,
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double elmore,
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double &delay,
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double &slew);
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std::pair<double, double> gateDelaySlew();
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std::optional<std::pair<double, double>>
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loadDelaySlewElmore(const Pin *load_pin,
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double elmore);
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// Select the appropriate special case Dartu/Menezes/Pileggi algorithm.
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void setCeffAlgorithm(const LibertyLibrary *library,
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const LibertyCell *cell,
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@ -125,8 +125,12 @@ DmpCeffElmoreDelayCalc::loadDelaySlew(const Pin *load_pin,
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float elmore = 0.0;
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if (parasitic)
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parasitics_->findElmore(parasitic, load_pin, elmore, elmore_exists);
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if (elmore_exists)
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loadDelaySlewElmore(load_pin, elmore, wire_delay, load_slew);
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if (elmore_exists) {
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if (auto r = loadDelaySlewElmore(load_pin, elmore)) {
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wire_delay = r->first;
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load_slew = r->second;
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}
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}
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thresholdAdjust(load_pin, drvr_library, rf, wire_delay, load_slew);
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}
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@ -28,47 +28,38 @@
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namespace sta {
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double
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std::pair<double, bool>
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findRoot(FindRootFunc func,
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double x1,
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double x2,
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double x_tol,
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int max_iter,
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// Return value.
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bool &fail)
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int max_iter)
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{
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double y1, y2, dy1;
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func(x1, y1, dy1);
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func(x2, y2, dy1);
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return findRoot(func, x1, y1, x2, y2, x_tol, max_iter, fail);
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return findRoot(func, x1, y1, x2, y2, x_tol, max_iter);
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}
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double
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std::pair<double, bool>
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findRoot(FindRootFunc func,
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double x1,
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double y1,
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double x2,
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double y2,
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double x_tol,
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int max_iter,
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// Return value.
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bool &fail)
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int max_iter)
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{
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if ((y1 > 0.0 && y2 > 0.0) || (y1 < 0.0 && y2 < 0.0)) {
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// Initial bounds do not surround a root.
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fail = true;
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return 0.0;
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return {0.0, true};
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}
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if (y1 == 0.0) {
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fail = false;
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return x1;
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}
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if (y1 == 0.0)
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return {x1, false};
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if (y2 == 0.0) {
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fail = false;
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return x2;
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}
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if (y2 == 0.0)
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return {x2, false};
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if (y1 > 0.0)
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// Swap x1/x2 so func(x1) < 0.
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@ -95,8 +86,7 @@ findRoot(FindRootFunc func,
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}
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if (std::abs(dx) <= x_tol * std::abs(root)) {
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// Converged.
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fail = false;
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return root;
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return {root, false};
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}
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func(root, y, dy);
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@ -105,8 +95,7 @@ findRoot(FindRootFunc func,
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else
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x2 = root;
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}
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fail = true;
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return root;
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return {root, true};
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}
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} // namespace
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@ -25,6 +25,7 @@
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#pragma once
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#include <functional>
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#include <utility>
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namespace sta {
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@ -33,24 +34,22 @@ using FindRootFunc = const std::function<void (double x,
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double &y,
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double &dy)>;
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double
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// first: root estimate; second: true if the search failed.
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std::pair<double, bool>
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findRoot(FindRootFunc func,
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double x1,
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double x2,
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double x_tol,
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int max_iter,
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// Return value.
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bool &fail);
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int max_iter);
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double
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// first: root estimate; second: true if the search failed.
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std::pair<double, bool>
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findRoot(FindRootFunc func,
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double x1,
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double y1,
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double x2,
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double y2,
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double x_tol,
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int max_iter,
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// Return value.
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bool &fail);
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int max_iter);
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} // namespace
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@ -648,12 +648,12 @@ GraphDelayCalc::findInputArcDelay(const Pin *drvr_pin,
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LoadPinIndexMap load_pin_index_map = makeLoadPinIndexMap(drvr_vertex);
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ArcDcalcResult intrinsic_result =
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arc_delay_calc->gateDelay(drvr_pin, arc, Slew(from_slew), 0.0, nullptr,
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arc_delay_calc->gateDelay(drvr_pin, arc, from_slew, 0.0, nullptr,
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load_pin_index_map, scene, min_max);
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const ArcDelay &intrinsic_delay = intrinsic_result.gateDelay();
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ArcDcalcResult gate_result = arc_delay_calc->gateDelay(drvr_pin, arc,
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Slew(from_slew), load_cap,
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from_slew, load_cap,
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parasitic,
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load_pin_index_map,
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scene, min_max);
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@ -194,8 +194,8 @@ PrimaDelayCalc::gateDelay(const Pin *drvr_pin,
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ArcDcalcArgSeq dcalc_args;
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dcalc_args.emplace_back(nullptr, drvr_pin, nullptr, arc, in_slew, load_cap,
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parasitic);
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ArcDcalcResultSeq dcalc_results =
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gateDelays(dcalc_args, load_pin_index_map, scene, min_max);
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ArcDcalcResultSeq dcalc_results = gateDelays(dcalc_args, load_pin_index_map,
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scene, min_max);
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return dcalc_results[0];
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}
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@ -399,6 +399,7 @@ void
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PrimaDelayCalc::initSim()
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{
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ceff_.resize(drvr_count_);
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ceff_vth_.resize(drvr_count_);
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drvr_current_.resize(drvr_count_);
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findNodeCount();
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@ -615,8 +616,12 @@ PrimaDelayCalc::updateCeffIdrvr()
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if (drvr_rf_ == RiseFall::rise()) {
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if (drvr_current != 0.0 && dv > 0.0) {
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double ceff = drvr_current * time_step_ / dv;
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if (output_waveforms_[drvr_idx]->capAxis()->inBounds(ceff))
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if (output_waveforms_[drvr_idx]->capAxis()->inBounds(ceff)) {
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ceff_[drvr_idx] = ceff;
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// Record the Ceff at Vth.
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if (v1 >= vth_ && v2 < vth_)
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ceff_vth_[drvr_idx] = ceff;
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}
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}
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if (v1 > (vdd_ - .01))
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// Whoa partner. Head'n for the weeds.
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@ -628,8 +633,12 @@ PrimaDelayCalc::updateCeffIdrvr()
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else {
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if (drvr_current != 0.0 && dv < 0.0) {
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double ceff = drvr_current * time_step_ / dv;
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if (output_waveforms_[drvr_idx]->capAxis()->inBounds(ceff))
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if (output_waveforms_[drvr_idx]->capAxis()->inBounds(ceff)) {
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ceff_[drvr_idx] = ceff;
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// Record the Ceff at Vth.
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if (v1 <= vth_ && v2 > vth_)
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ceff_vth_[drvr_idx] = ceff;
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}
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}
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if (v1 < 0.01) {
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// Whoa partner. Head'n for the weeds.
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@ -711,8 +720,13 @@ PrimaDelayCalc::dcalcResults()
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float ref_time = output_waveforms_[drvr_idx]->referenceTime(dcalc_arg.inSlewFlt());
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double gate_delay = drvr_times[threshold_vth] - ref_time;
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double drvr_slew = std::abs(drvr_times[threshold_vh] - drvr_times[threshold_vl]);
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dcalc_result.setGateDelay(gate_delay);
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dcalc_result.setDrvrSlew(drvr_slew);
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ArcDelay gate_delay2(gate_delay);
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Slew drvr_slew2(drvr_slew);
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delaySlewPocv(dcalc_arg, drvr_idx, gate_delay2, drvr_slew2);
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dcalc_result.setGateDelay(gate_delay2);
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dcalc_result.setDrvrSlew(drvr_slew2);
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debugPrint(debug_, "ccs_dcalc", 2, "{} gate delay {} slew {}",
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network_->pathName(drvr_pin), delayAsString(gate_delay, this),
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delayAsString(drvr_slew, this));
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@ -740,6 +754,28 @@ PrimaDelayCalc::dcalcResults()
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return dcalc_results;
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}
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// Fill in pocv parameters in gate_delay/drvr_slew.
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void
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PrimaDelayCalc::delaySlewPocv(ArcDcalcArg &dcalc_arg,
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size_t drvr_idx,
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ArcDelay &gate_delay,
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Slew &drvr_slew)
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{
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if (variables_->pocvEnabled()) {
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GateTableModel *table_model = dcalc_arg.arc()->gateTableModel(scene_, min_max_);
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if (table_model) {
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double ceff = ceff_vth_[drvr_idx];
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if (ceff == 0.0)
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ceff = dcalc_arg.loadCap();
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float in_slew = delayAsFloat(dcalc_arg.inSlew());
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const Pvt *pvt = pinPvt(dcalc_arg.drvrPin(), scene_, min_max_);
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table_model->gateDelayPocv(pvt, in_slew, ceff, min_max_,
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variables_->pocvMode(),
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gate_delay, drvr_slew);
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}
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}
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}
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////////////////////////////////////////////////////////////////
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void
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@ -895,7 +931,7 @@ std::string
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PrimaDelayCalc::reportGateDelay(const Pin *drvr_pin,
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const TimingArc *arc,
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const Slew &in_slew,
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float load_cap,
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float,
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const Parasitic *,
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const LoadPinIndexMap &,
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const Scene *scene,
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@ -905,8 +941,9 @@ PrimaDelayCalc::reportGateDelay(const Pin *drvr_pin,
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GateTimingModel *model = arc->gateModel(scene, min_max);
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if (model) {
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float in_slew1 = delayAsFloat(in_slew);
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float ceff = ceff_vth_[0];
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return model->reportGateDelay(pinPvt(drvr_pin, scene, min_max),
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in_slew1, load_cap, min_max,
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in_slew1, ceff, min_max,
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PocvMode::scalar, digits);
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}
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return "";
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@ -108,6 +108,10 @@ public:
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Waveform watchWaveform(const Pin *pin) override;
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protected:
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void delaySlewPocv(ArcDcalcArg &dcalc_arg,
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size_t drvr_idx,
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ArcDelay &gate_delay,
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Slew &drvr_slew);
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ArcDcalcResultSeq tableDcalcResults();
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void simulate();
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void simulate1(const MatrixSd &G,
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@ -215,6 +219,8 @@ protected:
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// Indexed by driver index.
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std::vector<double> ceff_;
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// Ceff at Vth
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std::vector<double> ceff_vth_;
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std::vector<double> drvr_current_;
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double time_step_;
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@ -56,8 +56,8 @@ using ConcretePortMemberIterator = VectorIterator<ConcretePortSeq, ConcretePort*
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class ConcreteLibrary
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{
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public:
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ConcreteLibrary(std::string name,
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std::string filename,
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ConcreteLibrary(std::string_view name,
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std::string_view filename,
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bool is_liberty);
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virtual ~ConcreteLibrary();
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const std::string &name() const { return name_; }
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|
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@ -24,14 +24,15 @@
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#pragma once
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#include <algorithm>
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#include <functional>
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#include <map>
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#include <ranges>
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#include <set>
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#include <string_view>
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#include <type_traits>
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#include <utility> // for std::declval
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#include <map>
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#include <set>
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#include <vector>
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#include <algorithm>
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#include <ranges>
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#include <functional>
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namespace sta {
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|
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@ -40,67 +40,56 @@ class Report;
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PortSeq
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filterPorts(std::string_view filter_expression,
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PortSeq *objects,
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bool bool_props_as_int,
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Sta *sta);
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InstanceSeq
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filterInstances(std::string_view filter_expression,
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InstanceSeq *objects,
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bool bool_props_as_int,
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Sta *sta);
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PinSeq
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filterPins(std::string_view filter_expression,
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PinSeq *objects,
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bool bool_props_as_int,
|
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Sta *sta);
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|
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NetSeq
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filterNets(std::string_view filter_expression,
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NetSeq *objects,
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bool bool_props_as_int,
|
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Sta *sta);
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ClockSeq
|
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filterClocks(std::string_view filter_expression,
|
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ClockSeq *objects,
|
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bool bool_props_as_int,
|
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Sta *sta);
|
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LibertyCellSeq
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filterLibCells(std::string_view filter_expression,
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LibertyCellSeq *objects,
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bool bool_props_as_int,
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Sta *sta);
|
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|
||||
LibertyPortSeq
|
||||
filterLibPins(std::string_view filter_expression,
|
||||
LibertyPortSeq *objects,
|
||||
bool bool_props_as_int,
|
||||
Sta *sta);
|
||||
|
||||
LibertyLibrarySeq
|
||||
filterLibertyLibraries(std::string_view filter_expression,
|
||||
LibertyLibrarySeq *objects,
|
||||
bool bool_props_as_int,
|
||||
Sta *sta);
|
||||
|
||||
EdgeSeq
|
||||
filterTimingArcs(std::string_view filter_expression,
|
||||
EdgeSeq *objects,
|
||||
bool bool_props_as_int,
|
||||
Sta *sta);
|
||||
|
||||
PathEndSeq
|
||||
filterPathEnds(std::string_view filter_expression,
|
||||
PathEndSeq *objects,
|
||||
bool bool_props_as_int,
|
||||
Sta *sta);
|
||||
|
||||
// For FilterExpr unit tests.
|
||||
StringSeq
|
||||
filterExprToPostfix(std::string_view expr,
|
||||
bool bool_props_as_int,
|
||||
Report *report);
|
||||
|
||||
} // namespace
|
||||
|
|
|
|||
|
|
@ -69,7 +69,7 @@ class DriverWaveform;
|
|||
class ModeValueDef
|
||||
{
|
||||
public:
|
||||
ModeValueDef(std::string value);
|
||||
ModeValueDef(std::string_view value);
|
||||
ModeValueDef(ModeValueDef &&other) noexcept;
|
||||
~ModeValueDef();
|
||||
const std::string &value() const { return value_; }
|
||||
|
|
@ -204,8 +204,8 @@ timingSenseOpposite(TimingSense sense);
|
|||
class LibertyLibrary : public ConcreteLibrary
|
||||
{
|
||||
public:
|
||||
LibertyLibrary(std::string name,
|
||||
std::string filename);
|
||||
LibertyLibrary(std::string_view name,
|
||||
std::string_view filename);
|
||||
virtual ~LibertyLibrary();
|
||||
LibertyCell *findLibertyCell(std::string_view name) const;
|
||||
LibertyCellSeq findLibertyCellsMatching(PatternMatch *pattern);
|
||||
|
|
@ -215,12 +215,12 @@ public:
|
|||
|
||||
DelayModelType delayModelType() const { return delay_model_type_; }
|
||||
void setDelayModelType(DelayModelType type);
|
||||
BusDcl *makeBusDcl(std::string name,
|
||||
BusDcl *makeBusDcl(std::string_view name,
|
||||
int from,
|
||||
int to);
|
||||
BusDcl *findBusDcl(std::string_view name);
|
||||
BusDclSeq busDcls() const;
|
||||
TableTemplate *makeTableTemplate(std::string name,
|
||||
TableTemplate *makeTableTemplate(std::string_view name,
|
||||
TableTemplateType type);
|
||||
TableTemplate *findTableTemplate(std::string_view name,
|
||||
TableTemplateType type);
|
||||
|
|
@ -235,7 +235,7 @@ public:
|
|||
|
||||
void setScaleFactors(ScaleFactors *scales);
|
||||
// Make named scale factor group. Returns pointer to the inserted element.
|
||||
ScaleFactors *makeScaleFactors(std::string name);
|
||||
ScaleFactors *makeScaleFactors(std::string_view name);
|
||||
ScaleFactors *findScaleFactors(std::string_view name);
|
||||
ScaleFactors *scaleFactors() const { return scale_factors_; }
|
||||
float scaleFactor(ScaleFactorType type,
|
||||
|
|
@ -336,18 +336,18 @@ public:
|
|||
Units *units() { return units_; }
|
||||
const Units *units() const { return units_; }
|
||||
|
||||
Wireload *makeWireload(std::string name);
|
||||
Wireload *makeWireload(std::string_view name);
|
||||
const Wireload *findWireload(std::string_view name);
|
||||
void setDefaultWireload(const Wireload *wireload);
|
||||
const Wireload *defaultWireload() const;
|
||||
WireloadSelection *makeWireloadSelection(std::string name);
|
||||
WireloadSelection *makeWireloadSelection(std::string_view name);
|
||||
const WireloadSelection *findWireloadSelection(std::string_view name) const;
|
||||
const WireloadSelection *defaultWireloadSelection() const;
|
||||
WireloadMode defaultWireloadMode() const;
|
||||
void setDefaultWireloadMode(WireloadMode mode);
|
||||
void setDefaultWireloadSelection(const WireloadSelection *selection);
|
||||
|
||||
OperatingConditions *makeOperatingConditions(std::string name);
|
||||
OperatingConditions *makeOperatingConditions(std::string_view name);
|
||||
OperatingConditions *findOperatingConditions(std::string_view name);
|
||||
OperatingConditions *defaultOperatingConditions() const;
|
||||
void setDefaultOperatingConditions(OperatingConditions *op_cond);
|
||||
|
|
@ -358,9 +358,9 @@ public:
|
|||
void setOcvArcDepth(float depth);
|
||||
OcvDerate *defaultOcvDerate() const;
|
||||
void setDefaultOcvDerate(OcvDerate *derate);
|
||||
OcvDerate *makeOcvDerate(std::string name);
|
||||
OcvDerate *makeOcvDerate(std::string_view name);
|
||||
OcvDerate *findOcvDerate(std::string_view derate_name);
|
||||
void addSupplyVoltage(std::string suppy_name,
|
||||
void addSupplyVoltage(std::string_view suppy_name,
|
||||
float voltage);
|
||||
bool supplyExists(std::string_view supply_name) const;
|
||||
void supplyVoltage(std::string_view supply_name,
|
||||
|
|
@ -369,8 +369,8 @@ public:
|
|||
bool &exists) const;
|
||||
|
||||
// Make scaled cell. Call LibertyCell::addScaledCell after it is complete.
|
||||
LibertyCell *makeScaledCell(std::string name,
|
||||
std::string filename);
|
||||
LibertyCell *makeScaledCell(std::string_view name,
|
||||
std::string_view filename);
|
||||
|
||||
static void
|
||||
makeSceneMap(LibertyLibrary *lib,
|
||||
|
|
@ -395,7 +395,7 @@ public:
|
|||
|
||||
DriverWaveform *findDriverWaveform(std::string_view name);
|
||||
DriverWaveform *driverWaveformDefault() { return findDriverWaveform(""); }
|
||||
DriverWaveform *makeDriverWaveform(std::string name,
|
||||
DriverWaveform *makeDriverWaveform(std::string_view name,
|
||||
TablePtr waveforms);
|
||||
|
||||
protected:
|
||||
|
|
@ -474,8 +474,8 @@ class LibertyCell : public ConcreteCell
|
|||
{
|
||||
public:
|
||||
LibertyCell(LibertyLibrary *library,
|
||||
std::string name,
|
||||
std::string filename);
|
||||
std::string_view name,
|
||||
std::string_view filename);
|
||||
virtual ~LibertyCell();
|
||||
LibertyLibrary *libertyLibrary() const { return liberty_library_; }
|
||||
LibertyLibrary *libertyLibrary() { return liberty_library_; }
|
||||
|
|
@ -484,7 +484,7 @@ public:
|
|||
bool hasInternalPorts() const { return has_internal_ports_; }
|
||||
ScaleFactors *scaleFactors() const { return scale_factors_; }
|
||||
void setScaleFactors(ScaleFactors *scale_factors);
|
||||
ModeDef *makeModeDef(std::string name);
|
||||
ModeDef *makeModeDef(std::string_view name);
|
||||
const ModeDef *findModeDef(std::string_view name) const;
|
||||
|
||||
float area() const { return area_; }
|
||||
|
|
@ -544,7 +544,7 @@ public:
|
|||
const Statetable *statetable() const { return statetable_; }
|
||||
|
||||
// Find bus declaration local to this cell.
|
||||
BusDcl *makeBusDcl(std::string name,
|
||||
BusDcl *makeBusDcl(std::string_view name,
|
||||
int from,
|
||||
int to);
|
||||
BusDcl *findBusDcl(std::string_view name);
|
||||
|
|
@ -565,7 +565,7 @@ public:
|
|||
// AOCV
|
||||
float ocvArcDepth() const;
|
||||
OcvDerate *ocvDerate() const;
|
||||
OcvDerate *makeOcvDerate(std::string name);
|
||||
OcvDerate *makeOcvDerate(std::string_view name);
|
||||
OcvDerate *findOcvDerate(std::string_view derate_name);
|
||||
|
||||
// Build helpers.
|
||||
|
|
@ -620,9 +620,9 @@ public:
|
|||
static void checkLibertyScenes();
|
||||
void ensureVoltageWaveforms(const SceneSeq &scenes);
|
||||
const std::string &footprint() const { return footprint_; }
|
||||
void setFootprint(std::string footprint);
|
||||
void setFootprint(std::string_view footprint);
|
||||
const std::string &userFunctionClass() const { return user_function_class_; }
|
||||
void setUserFunctionClass(std::string user_function_class);
|
||||
void setUserFunctionClass(std::string_view user_function_class);
|
||||
|
||||
protected:
|
||||
void addPort(ConcretePort *port);
|
||||
|
|
@ -758,7 +758,7 @@ public:
|
|||
PwrGndType pwrGndType() const { return pwr_gnd_type_; }
|
||||
void setPwrGndType(PwrGndType type);
|
||||
const std::string &voltageName() const { return voltage_name_; }
|
||||
void setVoltageName(std::string voltage_name);
|
||||
void setVoltageName(std::string_view voltage_name);
|
||||
////////////////////////////////////////////////////////////////
|
||||
|
||||
ScanSignalType scanSignalType() const { return scan_signal_type_; }
|
||||
|
|
@ -906,7 +906,7 @@ public:
|
|||
protected:
|
||||
// Constructor is internal to LibertyBuilder.
|
||||
LibertyPort(LibertyCell *cell,
|
||||
std::string name,
|
||||
std::string_view name,
|
||||
bool is_bus,
|
||||
BusDcl *bus_dcl,
|
||||
int from_index,
|
||||
|
|
@ -1016,7 +1016,7 @@ protected:
|
|||
class OperatingConditions : public Pvt
|
||||
{
|
||||
public:
|
||||
OperatingConditions(std::string name);
|
||||
OperatingConditions(std::string_view name);
|
||||
const std::string &name() const { return name_; }
|
||||
WireloadTree wireloadTree() const { return wire_load_tree_; }
|
||||
void setWireloadTree(WireloadTree tree);
|
||||
|
|
@ -1029,7 +1029,7 @@ protected:
|
|||
class ScaleFactors
|
||||
{
|
||||
public:
|
||||
ScaleFactors(std::string name);
|
||||
ScaleFactors(std::string_view name);
|
||||
const std::string &name() const { return name_; }
|
||||
float scale(ScaleFactorType type,
|
||||
ScaleFactorPvt pvt,
|
||||
|
|
@ -1056,7 +1056,7 @@ protected:
|
|||
class BusDcl
|
||||
{
|
||||
public:
|
||||
BusDcl(std::string name,
|
||||
BusDcl(std::string_view name,
|
||||
int from,
|
||||
int to);
|
||||
const std::string &name() const { return name_; }
|
||||
|
|
@ -1073,9 +1073,9 @@ protected:
|
|||
class ModeDef
|
||||
{
|
||||
public:
|
||||
ModeDef(std::string name);
|
||||
ModeDef(std::string_view name);
|
||||
const std::string &name() const { return name_; }
|
||||
ModeValueDef *defineValue(std::string value);
|
||||
ModeValueDef *defineValue(std::string_view value);
|
||||
const ModeValueDef *findValueDef(std::string_view value) const;
|
||||
const ModeValueMap &values() const { return values_; }
|
||||
|
||||
|
|
@ -1090,15 +1090,15 @@ private:
|
|||
class TableTemplate
|
||||
{
|
||||
public:
|
||||
TableTemplate(std::string name);
|
||||
TableTemplate(std::string name,
|
||||
TableTemplate(std::string_view name);
|
||||
TableTemplate(std::string_view name,
|
||||
TableTemplateType type);
|
||||
TableTemplate(std::string name,
|
||||
TableTemplate(std::string_view name,
|
||||
TableAxisPtr axis1,
|
||||
TableAxisPtr axis2,
|
||||
TableAxisPtr axis3);
|
||||
const std::string &name() const { return name_; }
|
||||
void setName(std::string name);
|
||||
void setName(std::string_view name);
|
||||
TableTemplateType type() const { return type_; }
|
||||
const TableAxis *axis1() const { return axis1_.get(); }
|
||||
TableAxisPtr axis1ptr() const { return axis1_; }
|
||||
|
|
@ -1122,8 +1122,8 @@ class TestCell : public LibertyCell
|
|||
{
|
||||
public:
|
||||
TestCell(LibertyLibrary *library,
|
||||
std::string name,
|
||||
std::string filename);
|
||||
std::string_view name,
|
||||
std::string_view filename);
|
||||
|
||||
protected:
|
||||
};
|
||||
|
|
@ -1131,7 +1131,7 @@ protected:
|
|||
class OcvDerate
|
||||
{
|
||||
public:
|
||||
OcvDerate(std::string name);
|
||||
OcvDerate(std::string_view name);
|
||||
~OcvDerate();
|
||||
const std::string &name() const { return name_; }
|
||||
const Table *derateTable(const RiseFall *rf,
|
||||
|
|
|
|||
|
|
@ -307,18 +307,18 @@ public:
|
|||
[[nodiscard]] bool isHierarchical(const Pin *pin) const;
|
||||
[[nodiscard]] bool isTopLevelPort(const Pin *pin) const;
|
||||
// Is pin inside the instance hier_pin is attached to?
|
||||
bool isInside(const Pin *pin,
|
||||
const Pin *hier_pin) const;
|
||||
[[nodiscard]] bool isInside(const Pin *pin,
|
||||
const Pin *hier_pin) const;
|
||||
// Is pin inside of hier_inst?
|
||||
bool isInside(const Pin *pin,
|
||||
const Instance *hier_inst) const;
|
||||
bool isDriver(const Pin *pin) const;
|
||||
bool isLoad(const Pin *pin) const;
|
||||
[[nodiscard]] bool isInside(const Pin *pin,
|
||||
const Instance *hier_inst) const;
|
||||
[[nodiscard]] bool isDriver(const Pin *pin) const;
|
||||
[[nodiscard]] bool isLoad(const Pin *pin) const;
|
||||
// Has register/latch rise/fall edges from pin.
|
||||
bool isRegClkPin(const Pin *pin) const;
|
||||
[[nodiscard]] bool isRegClkPin(const Pin *pin) const;
|
||||
// Pin clocks a timing check.
|
||||
bool isCheckClk(const Pin *pin) const;
|
||||
bool isLatchData(const Pin *pin) const;
|
||||
[[nodiscard]] bool isCheckClk(const Pin *pin) const;
|
||||
[[nodiscard]] bool isLatchData(const Pin *pin) const;
|
||||
|
||||
// Iterate over all of the pins connected to a pin and the parent
|
||||
// and child nets it is hierarchically connected to (port, leaf and
|
||||
|
|
|
|||
|
|
@ -62,9 +62,9 @@ deleteLiberty()
|
|||
TimingArcSet::destroy();
|
||||
}
|
||||
|
||||
LibertyLibrary::LibertyLibrary(std::string name,
|
||||
std::string filename) :
|
||||
ConcreteLibrary(std::move(name), std::move(filename), true),
|
||||
LibertyLibrary::LibertyLibrary(std::string_view name,
|
||||
std::string_view filename) :
|
||||
ConcreteLibrary(name, filename, true),
|
||||
units_(new Units()),
|
||||
delay_model_type_(DelayModelType::table), // default
|
||||
nominal_process_(0.0),
|
||||
|
|
@ -178,12 +178,12 @@ LibertyLibrary::setDelayModelType(DelayModelType type)
|
|||
}
|
||||
|
||||
BusDcl *
|
||||
LibertyLibrary::makeBusDcl(std::string name,
|
||||
LibertyLibrary::makeBusDcl(std::string_view name,
|
||||
int from,
|
||||
int to)
|
||||
{
|
||||
std::string key = name;
|
||||
auto [it, inserted] = bus_dcls_.try_emplace(std::move(key), std::move(name), from, to);
|
||||
std::string key(name);
|
||||
auto [it, inserted] = bus_dcls_.try_emplace(std::move(key), std::string(name), from, to);
|
||||
return &it->second;
|
||||
}
|
||||
|
||||
|
|
@ -203,13 +203,13 @@ LibertyLibrary::busDcls() const
|
|||
}
|
||||
|
||||
TableTemplate *
|
||||
LibertyLibrary::makeTableTemplate(std::string name,
|
||||
TableTemplateType type)
|
||||
LibertyLibrary::makeTableTemplate(std::string_view name,
|
||||
TableTemplateType type)
|
||||
{
|
||||
std::string key = name;
|
||||
std::string key(name);
|
||||
auto [it, inserted] = template_maps_[int(type)].try_emplace(std::move(key),
|
||||
std::move(name),
|
||||
type);
|
||||
std::string(name),
|
||||
type);
|
||||
return &it->second;
|
||||
}
|
||||
|
||||
|
|
@ -265,10 +265,10 @@ LibertyLibrary::setScaleFactors(ScaleFactors *scales)
|
|||
}
|
||||
|
||||
ScaleFactors *
|
||||
LibertyLibrary::makeScaleFactors(std::string name)
|
||||
LibertyLibrary::makeScaleFactors(std::string_view name)
|
||||
{
|
||||
std::string key = name;
|
||||
auto [it, inserted] = scale_factors_map_.emplace(std::move(key), std::move(name));
|
||||
std::string key(name);
|
||||
auto [it, inserted] = scale_factors_map_.emplace(std::move(key), std::string(name));
|
||||
return &it->second;
|
||||
}
|
||||
|
||||
|
|
@ -565,9 +565,10 @@ LibertyLibrary::setDefaultOutputPinRes(const RiseFall *rf,
|
|||
}
|
||||
|
||||
Wireload *
|
||||
LibertyLibrary::makeWireload(std::string name)
|
||||
LibertyLibrary::makeWireload(std::string_view name)
|
||||
{
|
||||
auto [it, inserted] = wireloads_.try_emplace(name, name, this);
|
||||
std::string key(name);
|
||||
auto [it, inserted] = wireloads_.try_emplace(std::move(key), std::string(name), this);
|
||||
return &it->second;
|
||||
}
|
||||
|
||||
|
|
@ -590,11 +591,11 @@ LibertyLibrary::defaultWireload() const
|
|||
}
|
||||
|
||||
WireloadSelection *
|
||||
LibertyLibrary::makeWireloadSelection(std::string name)
|
||||
LibertyLibrary::makeWireloadSelection(std::string_view name)
|
||||
{
|
||||
std::string key = name;
|
||||
std::string key(name);
|
||||
auto [it, inserted] = wire_load_selections_.try_emplace(std::move(key),
|
||||
std::move(name));
|
||||
std::string(name));
|
||||
return &it->second;
|
||||
}
|
||||
|
||||
|
|
@ -629,10 +630,10 @@ LibertyLibrary::setDefaultWireloadMode(WireloadMode mode)
|
|||
}
|
||||
|
||||
OperatingConditions *
|
||||
LibertyLibrary::makeOperatingConditions(std::string name)
|
||||
LibertyLibrary::makeOperatingConditions(std::string_view name)
|
||||
{
|
||||
std::string key = name;
|
||||
auto [it, inserted] = operating_conditions_.try_emplace(std::move(key), std::move(name));
|
||||
std::string key(name);
|
||||
auto [it, inserted] = operating_conditions_.try_emplace(std::move(key), std::string(name));
|
||||
return &it->second;
|
||||
}
|
||||
|
||||
|
|
@ -719,10 +720,10 @@ LibertyLibrary::setSlewDerateFromLibrary(float derate)
|
|||
}
|
||||
|
||||
LibertyCell *
|
||||
LibertyLibrary::makeScaledCell(std::string name,
|
||||
std::string filename)
|
||||
LibertyLibrary::makeScaledCell(std::string_view name,
|
||||
std::string_view filename)
|
||||
{
|
||||
return new LibertyCell(this, std::move(name), std::move(filename));
|
||||
return new LibertyCell(this, name, filename);
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////
|
||||
|
|
@ -853,10 +854,10 @@ LibertyLibrary::setDefaultOcvDerate(OcvDerate *derate)
|
|||
}
|
||||
|
||||
OcvDerate *
|
||||
LibertyLibrary::makeOcvDerate(std::string name)
|
||||
LibertyLibrary::makeOcvDerate(std::string_view name)
|
||||
{
|
||||
std::string key = name;
|
||||
auto [it, inserted] = ocv_derate_map_.try_emplace(std::move(key), std::move(name));
|
||||
std::string key(name);
|
||||
auto [it, inserted] = ocv_derate_map_.try_emplace(std::move(key), std::string(name));
|
||||
return &it->second;
|
||||
}
|
||||
|
||||
|
|
@ -867,10 +868,10 @@ LibertyLibrary::findOcvDerate(std::string_view derate_name)
|
|||
}
|
||||
|
||||
void
|
||||
LibertyLibrary::addSupplyVoltage(std::string supply_name,
|
||||
LibertyLibrary::addSupplyVoltage(std::string_view supply_name,
|
||||
float voltage)
|
||||
{
|
||||
supply_voltage_map_[std::move(supply_name)] = voltage;
|
||||
supply_voltage_map_[std::string(supply_name)] = voltage;
|
||||
}
|
||||
|
||||
void
|
||||
|
|
@ -903,13 +904,13 @@ LibertyLibrary::findDriverWaveform(std::string_view name)
|
|||
}
|
||||
|
||||
DriverWaveform *
|
||||
LibertyLibrary::makeDriverWaveform(std::string name,
|
||||
LibertyLibrary::makeDriverWaveform(std::string_view name,
|
||||
TablePtr waveforms)
|
||||
{
|
||||
std::string key = name;
|
||||
std::string key(name);
|
||||
auto [it, inserted] = driver_waveform_map_.try_emplace(std::move(key),
|
||||
std::move(name),
|
||||
waveforms);
|
||||
std::string(name),
|
||||
waveforms);
|
||||
return &it->second;
|
||||
}
|
||||
|
||||
|
|
@ -935,8 +936,8 @@ LibertyCellIterator::next()
|
|||
////////////////////////////////////////////////////////////////
|
||||
|
||||
LibertyCell::LibertyCell(LibertyLibrary *library,
|
||||
std::string name,
|
||||
std::string filename) :
|
||||
std::string_view name,
|
||||
std::string_view filename) :
|
||||
ConcreteCell(name, filename, true, library),
|
||||
liberty_library_(library),
|
||||
area_(0.0),
|
||||
|
|
@ -1019,10 +1020,10 @@ LibertyCell::setHasInternalPorts(bool has_internal)
|
|||
}
|
||||
|
||||
ModeDef *
|
||||
LibertyCell::makeModeDef(std::string name)
|
||||
LibertyCell::makeModeDef(std::string_view name)
|
||||
{
|
||||
std::string key = name;
|
||||
auto [it, inserted] = mode_defs_.try_emplace(std::move(key), std::move(name));
|
||||
std::string key(name);
|
||||
auto [it, inserted] = mode_defs_.try_emplace(std::move(key), std::string(name));
|
||||
return &it->second;
|
||||
}
|
||||
|
||||
|
|
@ -1039,12 +1040,12 @@ LibertyCell::setScaleFactors(ScaleFactors *scale_factors)
|
|||
}
|
||||
|
||||
BusDcl *
|
||||
LibertyCell::makeBusDcl(std::string name,
|
||||
LibertyCell::makeBusDcl(std::string_view name,
|
||||
int from,
|
||||
int to)
|
||||
{
|
||||
std::string key = name;
|
||||
auto [it, inserted] = bus_dcls_.try_emplace(std::move(key), std::move(name), from, to);
|
||||
std::string key(name);
|
||||
auto [it, inserted] = bus_dcls_.try_emplace(std::move(key), std::string(name), from, to);
|
||||
return &it->second;
|
||||
}
|
||||
|
||||
|
|
@ -1624,10 +1625,10 @@ LibertyCell::setOcvDerate(OcvDerate *derate)
|
|||
}
|
||||
|
||||
OcvDerate *
|
||||
LibertyCell::makeOcvDerate(std::string name)
|
||||
LibertyCell::makeOcvDerate(std::string_view name)
|
||||
{
|
||||
std::string key = name;
|
||||
auto [it, inserted] = ocv_derate_map_.try_emplace(std::move(key), std::move(name));
|
||||
std::string key(name);
|
||||
auto [it, inserted] = ocv_derate_map_.try_emplace(std::move(key), std::string(name));
|
||||
return &it->second;
|
||||
}
|
||||
|
||||
|
|
@ -1929,15 +1930,15 @@ LibertyCell::ensureVoltageWaveforms(const SceneSeq &scenes)
|
|||
}
|
||||
|
||||
void
|
||||
LibertyCell::setFootprint(std::string footprint)
|
||||
LibertyCell::setFootprint(std::string_view footprint)
|
||||
{
|
||||
footprint_ = std::move(footprint);
|
||||
footprint_ = footprint;
|
||||
}
|
||||
|
||||
void
|
||||
LibertyCell::setUserFunctionClass(std::string user_function_class)
|
||||
LibertyCell::setUserFunctionClass(std::string_view user_function_class)
|
||||
{
|
||||
user_function_class_ = std::move(user_function_class);
|
||||
user_function_class_ = user_function_class;
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////
|
||||
|
|
@ -1986,7 +1987,7 @@ LibertyCellPortBitIterator::next()
|
|||
////////////////////////////////////////////////////////////////
|
||||
|
||||
LibertyPort::LibertyPort(LibertyCell *cell,
|
||||
std::string name,
|
||||
std::string_view name,
|
||||
bool is_bus,
|
||||
BusDcl *bus_dcl,
|
||||
int from_index,
|
||||
|
|
@ -2079,9 +2080,9 @@ LibertyPort::setPwrGndType(PwrGndType type)
|
|||
}
|
||||
|
||||
void
|
||||
LibertyPort::setVoltageName(std::string voltage_name)
|
||||
LibertyPort::setVoltageName(std::string_view voltage_name)
|
||||
{
|
||||
voltage_name_ = std::move(voltage_name);
|
||||
voltage_name_ = voltage_name;
|
||||
}
|
||||
|
||||
static EnumNameMap<PwrGndType> pwr_gnd_type_map =
|
||||
|
|
@ -2840,10 +2841,10 @@ LibertyPortMemberIterator::next()
|
|||
|
||||
////////////////////////////////////////////////////////////////
|
||||
|
||||
BusDcl::BusDcl(std::string name,
|
||||
BusDcl::BusDcl(std::string_view name,
|
||||
int from,
|
||||
int to) :
|
||||
name_(std::move(name)),
|
||||
name_(name),
|
||||
from_(from),
|
||||
to_(to)
|
||||
{
|
||||
|
|
@ -2851,16 +2852,16 @@ BusDcl::BusDcl(std::string name,
|
|||
|
||||
////////////////////////////////////////////////////////////////
|
||||
|
||||
ModeDef::ModeDef(std::string name) :
|
||||
name_(std::move(name))
|
||||
ModeDef::ModeDef(std::string_view name) :
|
||||
name_(name)
|
||||
{
|
||||
}
|
||||
|
||||
ModeValueDef *
|
||||
ModeDef::defineValue(std::string value)
|
||||
ModeDef::defineValue(std::string_view value)
|
||||
{
|
||||
std::string key = value;
|
||||
auto [it, inserted] = values_.try_emplace(std::move(key), std::move(value));
|
||||
std::string key(value);
|
||||
auto [it, inserted] = values_.try_emplace(std::move(key), std::string(value));
|
||||
return &it->second;
|
||||
}
|
||||
|
||||
|
|
@ -2872,8 +2873,8 @@ ModeDef::findValueDef(std::string_view value) const
|
|||
|
||||
////////////////////////////////////////////////////////////////
|
||||
|
||||
ModeValueDef::ModeValueDef(std::string value) :
|
||||
value_(std::move(value)),
|
||||
ModeValueDef::ModeValueDef(std::string_view value) :
|
||||
value_(value),
|
||||
cond_(nullptr)
|
||||
{
|
||||
}
|
||||
|
|
@ -2905,8 +2906,8 @@ ModeValueDef::setSdfCond(std::string sdf_cond)
|
|||
|
||||
////////////////////////////////////////////////////////////////
|
||||
|
||||
TableTemplate::TableTemplate(std::string name) :
|
||||
name_(std::move(name)),
|
||||
TableTemplate::TableTemplate(std::string_view name) :
|
||||
name_(name),
|
||||
type_(TableTemplateType::delay),
|
||||
axis1_(nullptr),
|
||||
axis2_(nullptr),
|
||||
|
|
@ -2914,9 +2915,9 @@ TableTemplate::TableTemplate(std::string name) :
|
|||
{
|
||||
}
|
||||
|
||||
TableTemplate::TableTemplate(std::string name,
|
||||
TableTemplate::TableTemplate(std::string_view name,
|
||||
TableTemplateType type) :
|
||||
name_(std::move(name)),
|
||||
name_(name),
|
||||
type_(type),
|
||||
axis1_(nullptr),
|
||||
axis2_(nullptr),
|
||||
|
|
@ -2924,11 +2925,11 @@ TableTemplate::TableTemplate(std::string name,
|
|||
{
|
||||
}
|
||||
|
||||
TableTemplate::TableTemplate(std::string name,
|
||||
TableTemplate::TableTemplate(std::string_view name,
|
||||
TableAxisPtr axis1,
|
||||
TableAxisPtr axis2,
|
||||
TableAxisPtr axis3) :
|
||||
name_(std::move(name)),
|
||||
name_(name),
|
||||
type_(TableTemplateType::delay),
|
||||
axis1_(axis1),
|
||||
axis2_(axis2),
|
||||
|
|
@ -2937,9 +2938,9 @@ TableTemplate::TableTemplate(std::string name,
|
|||
}
|
||||
|
||||
void
|
||||
TableTemplate::setName(std::string name)
|
||||
TableTemplate::setName(std::string_view name)
|
||||
{
|
||||
name_ = std::move(name);
|
||||
name_ = name;
|
||||
}
|
||||
|
||||
void
|
||||
|
|
@ -2989,9 +2990,9 @@ Pvt::setTemperature(float temp)
|
|||
temperature_ = temp;
|
||||
}
|
||||
|
||||
OperatingConditions::OperatingConditions(std::string name) :
|
||||
OperatingConditions::OperatingConditions(std::string_view name) :
|
||||
Pvt(0.0, 0.0, 0.0),
|
||||
name_(std::move(name)),
|
||||
name_(name),
|
||||
// Default wireload tree.
|
||||
wire_load_tree_(WireloadTree::unknown)
|
||||
{
|
||||
|
|
@ -3085,8 +3086,8 @@ scaleFactorPvtName(ScaleFactorPvt pvt)
|
|||
|
||||
////////////////////////////////////////////////////////////////
|
||||
|
||||
ScaleFactors::ScaleFactors(std::string name) :
|
||||
name_(std::move(name))
|
||||
ScaleFactors::ScaleFactors(std::string_view name) :
|
||||
name_(name)
|
||||
{
|
||||
for (int type = 0; type < scale_factor_type_count; type++) {
|
||||
for (int pvt = 0; pvt < scale_factor_pvt_count; pvt++) {
|
||||
|
|
@ -3168,16 +3169,16 @@ ScaleFactors::report(Report *report)
|
|||
}
|
||||
|
||||
TestCell::TestCell(LibertyLibrary *library,
|
||||
std::string name,
|
||||
std::string filename) :
|
||||
std::string_view name,
|
||||
std::string_view filename) :
|
||||
LibertyCell(library, name, filename)
|
||||
{
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////
|
||||
|
||||
OcvDerate::OcvDerate(std::string name) :
|
||||
name_(std::move(name))
|
||||
OcvDerate::OcvDerate(std::string_view name) :
|
||||
name_(name)
|
||||
{
|
||||
for (auto el_index : EarlyLate::rangeIndex()) {
|
||||
for (auto rf_index : RiseFall::rangeIndex()) {
|
||||
|
|
|
|||
|
|
@ -124,7 +124,7 @@ LibertyBuilder::makePort(LibertyCell *cell,
|
|||
|
||||
LibertyPort *
|
||||
LibertyBuilder::makeBundlePort(LibertyCell *cell,
|
||||
const char *name,
|
||||
std::string_view name,
|
||||
ConcretePortSeq *members)
|
||||
{
|
||||
LibertyPort *port = new LibertyPort(cell, name, false, nullptr, -1, -1, true, members);
|
||||
|
|
|
|||
|
|
@ -54,7 +54,7 @@ public:
|
|||
int to_index,
|
||||
BusDcl *bus_dcl);
|
||||
LibertyPort *makeBundlePort(LibertyCell *cell,
|
||||
const char *name,
|
||||
std::string_view name,
|
||||
ConcretePortSeq *members);
|
||||
// Build timing arc sets and their arcs given a type and sense.
|
||||
// Port functions and cell latches are also used by this builder
|
||||
|
|
|
|||
|
|
@ -176,7 +176,7 @@ LibertyReader::endCell(const LibertyGroup *cell_group,
|
|||
if (cell_group->hasFirstParam()) {
|
||||
const std::string &name = cell_group->firstParam();
|
||||
debugPrint(debug_, "liberty", 1, "cell {}", name);
|
||||
LibertyCell *cell = builder_.makeCell(library_, name, std::string(filename_));
|
||||
LibertyCell *cell = builder_.makeCell(library_, name, filename_);
|
||||
readCell(cell, cell_group);
|
||||
}
|
||||
else
|
||||
|
|
@ -849,7 +849,7 @@ LibertyReader::readDefaultWireLoadSelection(const LibertyGroup *library_group)
|
|||
library_group->findAttrString("default_wire_load_selection");
|
||||
if (!selection_name.empty()) {
|
||||
const WireloadSelection *selection =
|
||||
library_->findWireloadSelection(selection_name.c_str());
|
||||
library_->findWireloadSelection(selection_name);
|
||||
if (selection)
|
||||
library_->setDefaultWireloadSelection(selection);
|
||||
else
|
||||
|
|
@ -1003,9 +1003,8 @@ LibertyReader::readScaledCell(const LibertyGroup *scaled_cell_group)
|
|||
OperatingConditions *op_cond = library_->findOperatingConditions(op_cond_name);
|
||||
if (op_cond) {
|
||||
debugPrint(debug_, "liberty", 1, "scaled cell {} {}",
|
||||
name.c_str(), op_cond_name.c_str());
|
||||
LibertyCell *scaled_cell = library_->makeScaledCell(name,
|
||||
std::string(filename_));
|
||||
name, op_cond_name);
|
||||
LibertyCell *scaled_cell = library_->makeScaledCell(name, filename_);
|
||||
readCell(scaled_cell, scaled_cell_group);
|
||||
checkScaledCell(scaled_cell, owner, scaled_cell_group, op_cond_name);
|
||||
// Add scaled cell AFTER ports and timing arcs are defined.
|
||||
|
|
@ -1163,8 +1162,7 @@ LibertyReader::makeBundlePort(LibertyCell *cell,
|
|||
members->push_back(member);
|
||||
}
|
||||
}
|
||||
LibertyPort *bundle_port = builder_.makeBundlePort(cell, bundle_name.c_str(),
|
||||
members);
|
||||
LibertyPort *bundle_port = builder_.makeBundlePort(cell, bundle_name, members);
|
||||
port_group_map[bundle_group].push_back(bundle_port);
|
||||
// Make ports for pin groups inside the bundle group.
|
||||
makeBundlePinPorts(cell, bundle_group, port_group_map);
|
||||
|
|
@ -1204,7 +1202,7 @@ LibertyReader::makePgPinPort(LibertyCell *cell,
|
|||
|
||||
const std::string &type_name = pg_pin_group->findAttrString("pg_type");
|
||||
if (!type_name.empty()) {
|
||||
PwrGndType type = findPwrGndType(type_name.c_str());
|
||||
PwrGndType type = findPwrGndType(type_name);
|
||||
PortDirection *dir = PortDirection::unknown();
|
||||
switch (type) {
|
||||
case PwrGndType::primary_ground:
|
||||
|
|
@ -1235,7 +1233,7 @@ LibertyReader::makePgPinPort(LibertyCell *cell,
|
|||
|
||||
const std::string &voltate_name = pg_pin_group->findAttrString("voltage_name");
|
||||
if (!voltate_name.empty())
|
||||
pg_port->setVoltageName(voltate_name.c_str());
|
||||
pg_port->setVoltageName(voltate_name);
|
||||
}
|
||||
else
|
||||
warn(1314, pg_pin_group, "pg_pin missing name.");
|
||||
|
|
@ -1295,7 +1293,7 @@ LibertyReader::readDriverWaveform(const LibertyPortSeq &ports,
|
|||
: "driver_waveform_fall";
|
||||
const std::string &name = port_group->findAttrString(attr_name);
|
||||
if (!name.empty()) {
|
||||
DriverWaveform *waveform = library_->findDriverWaveform(name.c_str());
|
||||
DriverWaveform *waveform = library_->findDriverWaveform(name);
|
||||
if (waveform) {
|
||||
for (LibertyPort *port : ports)
|
||||
port->setDriverWaveform(waveform, rf);
|
||||
|
|
@ -1830,9 +1828,9 @@ LibertyReader::readCellAttributes(LibertyCell *cell,
|
|||
const std::string &clock_gate_type =
|
||||
cell_group->findAttrString("clock_gating_integrated_cell");
|
||||
if (!clock_gate_type.empty()) {
|
||||
if (stringBeginEqual(clock_gate_type.c_str(), "latch_posedge"))
|
||||
if (stringBeginEqual(clock_gate_type, "latch_posedge"))
|
||||
cell->setClockGateType(ClockGateType::latch_posedge);
|
||||
else if (stringBeginEqual(clock_gate_type.c_str(), "latch_negedge"))
|
||||
else if (stringBeginEqual(clock_gate_type, "latch_negedge"))
|
||||
cell->setClockGateType(ClockGateType::latch_negedge);
|
||||
else
|
||||
cell->setClockGateType(ClockGateType::other);
|
||||
|
|
@ -1852,7 +1850,7 @@ LibertyReader::readScaleFactors(LibertyCell *cell,
|
|||
cell_group->findAttrString("scaling_factors");
|
||||
if (!scale_factors_name.empty()) {
|
||||
ScaleFactors *scale_factors =
|
||||
library_->findScaleFactors(scale_factors_name.c_str());
|
||||
library_->findScaleFactors(scale_factors_name);
|
||||
if (scale_factors)
|
||||
cell->setScaleFactors(scale_factors);
|
||||
else
|
||||
|
|
@ -1862,7 +1860,7 @@ LibertyReader::readScaleFactors(LibertyCell *cell,
|
|||
|
||||
void
|
||||
LibertyReader::readCellAttrString(std::string_view attr_name,
|
||||
void (LibertyCell::*set_func)(std::string value),
|
||||
void (LibertyCell::*set_func)(std::string_view value),
|
||||
LibertyCell *cell,
|
||||
const LibertyGroup *group)
|
||||
{
|
||||
|
|
@ -2943,9 +2941,9 @@ LibertyReader::readCellOcvDerateGroup(LibertyCell *cell,
|
|||
{
|
||||
const std::string &derate_name = cell_group->findAttrString("ocv_derate_group");
|
||||
if (!derate_name.empty()) {
|
||||
OcvDerate *derate = cell->findOcvDerate(derate_name.c_str());
|
||||
OcvDerate *derate = cell->findOcvDerate(derate_name);
|
||||
if (derate == nullptr)
|
||||
derate = library_->findOcvDerate(derate_name.c_str());
|
||||
derate = library_->findOcvDerate(derate_name);
|
||||
if (derate)
|
||||
cell->setOcvDerate(derate);
|
||||
else
|
||||
|
|
@ -3453,7 +3451,7 @@ LibertyReader::readDefaultOcvDerateGroup(const LibertyGroup *library_group)
|
|||
const std::string &derate_name =
|
||||
library_group->findAttrString("default_ocv_derate_group");
|
||||
if (!derate_name.empty()) {
|
||||
OcvDerate *derate = library_->findOcvDerate(derate_name.c_str());
|
||||
OcvDerate *derate = library_->findOcvDerate(derate_name);
|
||||
if (derate)
|
||||
library_->setDefaultOcvDerate(derate);
|
||||
else
|
||||
|
|
|
|||
|
|
@ -375,7 +375,7 @@ protected:
|
|||
void readScaleFactors(LibertyCell *cell,
|
||||
const LibertyGroup *cell_group);
|
||||
void readCellAttrString(std::string_view attr_name,
|
||||
void (LibertyCell::*set_func)(std::string value),
|
||||
void (LibertyCell::*set_func)(std::string_view value),
|
||||
LibertyCell *cell,
|
||||
const LibertyGroup *group);
|
||||
void readCellAttrFloat(std::string_view attr_name,
|
||||
|
|
|
|||
|
|
@ -38,12 +38,12 @@ namespace sta {
|
|||
|
||||
static constexpr char escape_ = '\\';
|
||||
|
||||
ConcreteLibrary::ConcreteLibrary(std::string name,
|
||||
std::string filename,
|
||||
ConcreteLibrary::ConcreteLibrary(std::string_view name,
|
||||
std::string_view filename,
|
||||
bool is_liberty) :
|
||||
name_(std::move(name)),
|
||||
name_(name),
|
||||
id_(ConcreteNetwork::nextObjectId()),
|
||||
filename_(std::move(filename)),
|
||||
filename_(filename),
|
||||
is_liberty_(is_liberty),
|
||||
bus_brkt_left_('['),
|
||||
bus_brkt_right_(']')
|
||||
|
|
|
|||
|
|
@ -73,9 +73,9 @@ public:
|
|||
FilterExpr(std::string_view expression,
|
||||
Report *report);
|
||||
|
||||
std::vector<std::unique_ptr<Token>> postfix(bool bool_props_as_int);
|
||||
std::vector<std::unique_ptr<Token>> postfix();
|
||||
private:
|
||||
std::vector<std::unique_ptr<Token>> lex(bool bool_props_as_int);
|
||||
std::vector<std::unique_ptr<Token>> lex();
|
||||
std::vector<std::unique_ptr<Token>> shuntingYard(std::vector<std::unique_ptr<Token>> &infix);
|
||||
|
||||
std::string raw_;
|
||||
|
|
@ -106,20 +106,21 @@ FilterExpr::FilterExpr(std::string_view expression,
|
|||
}
|
||||
|
||||
std::vector<std::unique_ptr<FilterExpr::Token>>
|
||||
FilterExpr::postfix(bool bool_props_as_int)
|
||||
FilterExpr::postfix()
|
||||
{
|
||||
auto infix = lex(bool_props_as_int);
|
||||
auto infix = lex();
|
||||
return shuntingYard(infix);
|
||||
}
|
||||
|
||||
std::vector<std::unique_ptr<FilterExpr::Token>>
|
||||
FilterExpr::lex(bool bool_props_as_int)
|
||||
FilterExpr::lex()
|
||||
{
|
||||
std::vector<std::pair<std::regex, Token::Kind>> token_regexes = {
|
||||
{std::regex("^\\s+"), Token::Kind::skip},
|
||||
{std::regex("^defined\\(([a-zA-Z_]+)\\)"), Token::Kind::defined},
|
||||
{std::regex("^undefined\\(([a-zA-Z_]+)\\)"), Token::Kind::undefined},
|
||||
{std::regex("^@?([a-zA-Z_]+) *((==|!=|=~|!~) *([0-9a-zA-Z_\\/$\\[\\]*?.]+))?"), Token::Kind::predicate},
|
||||
{std::regex("^@?([a-zA-Z_]+) *((==|!=|=~|!~) *([0-9a-zA-Z_\\/$\\[\\]*?.]+))?"),
|
||||
Token::Kind::predicate},
|
||||
{std::regex("^(&&)"), Token::Kind::op_and},
|
||||
{std::regex("^(\\|\\|)"), Token::Kind::op_or},
|
||||
{std::regex("^(!)"), Token::Kind::op_inv},
|
||||
|
|
@ -139,9 +140,9 @@ FilterExpr::lex(bool bool_props_as_int)
|
|||
std::string property = token_match[1].str();
|
||||
|
||||
// The default operation on a predicate if an op and arg are
|
||||
// omitted is 'arg == 1' / 'arg == true'.
|
||||
// omitted is 'prop == 1 || true'.
|
||||
std::string op = "==";
|
||||
std::string arg = (bool_props_as_int ? "1" : "true");
|
||||
std::string arg = "1";
|
||||
|
||||
if (token_match[2].length() != 0) {
|
||||
op = token_match[3].str();
|
||||
|
|
@ -250,13 +251,18 @@ filterObjects(const char *property,
|
|||
bool not_pattern_match = stringEq(op, "!~");
|
||||
for (T *object : all) {
|
||||
PropertyValue value = properties.getProperty(object, property);
|
||||
std::string prop_str = value.to_string(network);
|
||||
const char *prop = prop_str.c_str();
|
||||
if (prop &&
|
||||
((exact_match && stringEq(prop, pattern))
|
||||
|| (not_match && !stringEq(prop, pattern))
|
||||
|| (pattern_match && patternMatch(pattern, prop))
|
||||
|| (not_pattern_match && !patternMatch(pattern, prop))))
|
||||
std::string prop = value.to_string(network);
|
||||
if (value.type() == PropertyValue::Type::bool_) {
|
||||
// Canonicalize bool true/false to 1/0.
|
||||
if (stringEqual(pattern, "true"))
|
||||
pattern = "1";
|
||||
else if (stringEqual(pattern, "false"))
|
||||
pattern = "0";
|
||||
}
|
||||
if ((exact_match && stringEq(prop.c_str(), pattern))
|
||||
|| (not_match && !stringEq(prop.c_str(), pattern))
|
||||
|| (pattern_match && patternMatch(pattern, prop))
|
||||
|| (not_pattern_match && !patternMatch(pattern, prop)))
|
||||
filtered_objects.insert(object);
|
||||
}
|
||||
return filtered_objects;
|
||||
|
|
@ -265,7 +271,6 @@ filterObjects(const char *property,
|
|||
template <typename T> std::vector<T*>
|
||||
filterObjects(std::string_view filter_expression,
|
||||
std::vector<T*> *objects,
|
||||
bool bool_props_as_int,
|
||||
Sta *sta)
|
||||
{
|
||||
Report *report = sta->report();
|
||||
|
|
@ -278,7 +283,7 @@ filterObjects(std::string_view filter_expression,
|
|||
all.insert(object);
|
||||
|
||||
FilterExpr filter(filter_expression, report);
|
||||
auto postfix = filter.postfix(bool_props_as_int);
|
||||
auto postfix = filter.postfix();
|
||||
std::stack<std::set<T*>> eval_stack;
|
||||
for (auto &token : postfix) {
|
||||
if (token->kind == FilterExpr::Token::Kind::op_or) {
|
||||
|
|
@ -405,100 +410,89 @@ filterObjects(std::string_view filter_expression,
|
|||
PortSeq
|
||||
filterPorts(std::string_view filter_expression,
|
||||
PortSeq *objects,
|
||||
bool bool_props_as_int,
|
||||
Sta *sta)
|
||||
{
|
||||
return filterObjects<const Port>(filter_expression, objects, bool_props_as_int, sta);
|
||||
return filterObjects<const Port>(filter_expression, objects, sta);
|
||||
}
|
||||
|
||||
InstanceSeq
|
||||
filterInstances(std::string_view filter_expression,
|
||||
InstanceSeq *objects,
|
||||
bool bool_props_as_int,
|
||||
Sta *sta)
|
||||
{
|
||||
return filterObjects<const Instance>(filter_expression, objects, bool_props_as_int, sta);
|
||||
return filterObjects<const Instance>(filter_expression, objects, sta);
|
||||
}
|
||||
|
||||
PinSeq
|
||||
filterPins(std::string_view filter_expression,
|
||||
PinSeq *objects,
|
||||
bool bool_props_as_int,
|
||||
Sta *sta)
|
||||
{
|
||||
return filterObjects<const Pin>(filter_expression, objects, bool_props_as_int, sta);
|
||||
return filterObjects<const Pin>(filter_expression, objects, sta);
|
||||
}
|
||||
|
||||
NetSeq
|
||||
filterNets(std::string_view filter_expression,
|
||||
NetSeq *objects,
|
||||
bool bool_props_as_int,
|
||||
Sta *sta)
|
||||
{
|
||||
return filterObjects<const Net>(filter_expression, objects, bool_props_as_int, sta);
|
||||
return filterObjects<const Net>(filter_expression, objects, sta);
|
||||
}
|
||||
|
||||
ClockSeq
|
||||
filterClocks(std::string_view filter_expression,
|
||||
ClockSeq *objects,
|
||||
bool bool_props_as_int,
|
||||
Sta *sta)
|
||||
{
|
||||
return filterObjects<Clock>(filter_expression, objects, bool_props_as_int, sta);
|
||||
return filterObjects<Clock>(filter_expression, objects, sta);
|
||||
}
|
||||
|
||||
LibertyCellSeq
|
||||
filterLibCells(std::string_view filter_expression,
|
||||
LibertyCellSeq *objects,
|
||||
bool bool_props_as_int,
|
||||
Sta *sta)
|
||||
{
|
||||
return filterObjects<LibertyCell>(filter_expression, objects, bool_props_as_int, sta);
|
||||
return filterObjects<LibertyCell>(filter_expression, objects, sta);
|
||||
}
|
||||
|
||||
LibertyPortSeq
|
||||
filterLibPins(std::string_view filter_expression,
|
||||
LibertyPortSeq *objects,
|
||||
bool bool_props_as_int,
|
||||
Sta *sta)
|
||||
{
|
||||
return filterObjects<LibertyPort>(filter_expression, objects, bool_props_as_int, sta);
|
||||
return filterObjects<LibertyPort>(filter_expression, objects, sta);
|
||||
}
|
||||
|
||||
LibertyLibrarySeq
|
||||
filterLibertyLibraries(std::string_view filter_expression,
|
||||
LibertyLibrarySeq *objects,
|
||||
bool bool_props_as_int,
|
||||
Sta *sta)
|
||||
{
|
||||
return filterObjects<LibertyLibrary>(filter_expression, objects, bool_props_as_int, sta);
|
||||
return filterObjects<LibertyLibrary>(filter_expression, objects, sta);
|
||||
}
|
||||
|
||||
EdgeSeq
|
||||
filterTimingArcs(std::string_view filter_expression,
|
||||
EdgeSeq *objects,
|
||||
bool bool_props_as_int,
|
||||
Sta *sta)
|
||||
{
|
||||
return filterObjects<Edge>(filter_expression, objects, bool_props_as_int, sta);
|
||||
return filterObjects<Edge>(filter_expression, objects, sta);
|
||||
}
|
||||
|
||||
PathEndSeq
|
||||
filterPathEnds(std::string_view filter_expression,
|
||||
PathEndSeq *objects,
|
||||
bool bool_props_as_int,
|
||||
Sta *sta)
|
||||
{
|
||||
return filterObjects<PathEnd>(filter_expression, objects, bool_props_as_int, sta);
|
||||
return filterObjects<PathEnd>(filter_expression, objects, sta);
|
||||
}
|
||||
|
||||
StringSeq
|
||||
filterExprToPostfix(std::string_view expr,
|
||||
bool bool_props_as_int,
|
||||
Report *report)
|
||||
{
|
||||
FilterExpr filter(expr, report);
|
||||
auto postfix = filter.postfix(bool_props_as_int);
|
||||
auto postfix = filter.postfix();
|
||||
StringSeq result;
|
||||
for (auto &token : postfix)
|
||||
result.push_back(token->text);
|
||||
|
|
|
|||
55
sdc/Sdc.i
55
sdc/Sdc.i
|
|
@ -1493,101 +1493,90 @@ find_register_output_pins(ClockSet *clks,
|
|||
|
||||
PortSeq
|
||||
filter_ports(const char *filter_expression,
|
||||
PortSeq *ports,
|
||||
bool bool_props_as_int)
|
||||
PortSeq *ports)
|
||||
{
|
||||
sta::Sta *sta = Sta::sta();
|
||||
return filterPorts(filter_expression, ports, bool_props_as_int, sta);
|
||||
return filterPorts(filter_expression, ports, sta);
|
||||
}
|
||||
|
||||
InstanceSeq
|
||||
filter_insts(const char *filter_expression,
|
||||
InstanceSeq *insts,
|
||||
bool bool_props_as_int)
|
||||
InstanceSeq *insts)
|
||||
{
|
||||
sta::Sta *sta = Sta::sta();
|
||||
return filterInstances(filter_expression, insts, bool_props_as_int, sta);
|
||||
return filterInstances(filter_expression, insts, sta);
|
||||
}
|
||||
|
||||
PinSeq
|
||||
filter_pins(const char *filter_expression,
|
||||
PinSeq *pins,
|
||||
bool bool_props_as_int)
|
||||
PinSeq *pins)
|
||||
{
|
||||
sta::Sta *sta = Sta::sta();
|
||||
return filterPins(filter_expression, pins, bool_props_as_int, sta);
|
||||
return filterPins(filter_expression, pins, sta);
|
||||
}
|
||||
|
||||
NetSeq
|
||||
filter_nets(const char *filter_expression,
|
||||
NetSeq *nets,
|
||||
bool bool_props_as_int)
|
||||
NetSeq *nets)
|
||||
{
|
||||
sta::Sta *sta = Sta::sta();
|
||||
return filterNets(filter_expression, nets, bool_props_as_int, sta);
|
||||
return filterNets(filter_expression, nets, sta);
|
||||
}
|
||||
|
||||
ClockSeq
|
||||
filter_clocks(const char *filter_expression,
|
||||
ClockSeq *clocks,
|
||||
bool bool_props_as_int)
|
||||
ClockSeq *clocks)
|
||||
{
|
||||
sta::Sta *sta = Sta::sta();
|
||||
return filterClocks(filter_expression, clocks, bool_props_as_int, sta);
|
||||
return filterClocks(filter_expression, clocks, sta);
|
||||
}
|
||||
|
||||
LibertyCellSeq
|
||||
filter_lib_cells(const char *filter_expression,
|
||||
LibertyCellSeq *cells,
|
||||
bool bool_props_as_int)
|
||||
LibertyCellSeq *cells)
|
||||
{
|
||||
sta::Sta *sta = Sta::sta();
|
||||
return filterLibCells(filter_expression, cells, bool_props_as_int, sta);
|
||||
return filterLibCells(filter_expression, cells, sta);
|
||||
}
|
||||
|
||||
LibertyPortSeq
|
||||
filter_lib_pins(const char *filter_expression,
|
||||
LibertyPortSeq *pins,
|
||||
bool bool_props_as_int)
|
||||
LibertyPortSeq *pins)
|
||||
{
|
||||
sta::Sta *sta = Sta::sta();
|
||||
return filterLibPins(filter_expression, pins, bool_props_as_int, sta);
|
||||
return filterLibPins(filter_expression, pins, sta);
|
||||
}
|
||||
|
||||
LibertyLibrarySeq
|
||||
filter_liberty_libraries(const char *filter_expression,
|
||||
LibertyLibrarySeq *libs,
|
||||
bool bool_props_as_int)
|
||||
LibertyLibrarySeq *libs)
|
||||
{
|
||||
sta::Sta *sta = Sta::sta();
|
||||
return filterLibertyLibraries(filter_expression, libs, bool_props_as_int, sta);
|
||||
return filterLibertyLibraries(filter_expression, libs, sta);
|
||||
}
|
||||
|
||||
EdgeSeq
|
||||
filter_timing_arcs(const char *filter_expression,
|
||||
EdgeSeq *edges,
|
||||
bool bool_props_as_int)
|
||||
EdgeSeq *edges)
|
||||
{
|
||||
sta::Sta *sta = Sta::sta();
|
||||
return filterTimingArcs(filter_expression, edges, bool_props_as_int, sta);
|
||||
return filterTimingArcs(filter_expression, edges, sta);
|
||||
}
|
||||
|
||||
PathEndSeq
|
||||
filter_path_ends(const char *filter_expression,
|
||||
PathEndSeq *path_ends,
|
||||
bool bool_props_as_int)
|
||||
PathEndSeq *path_ends)
|
||||
{
|
||||
sta::Sta *sta = Sta::sta();
|
||||
return filterPathEnds(filter_expression, path_ends, bool_props_as_int, sta);
|
||||
return filterPathEnds(filter_expression, path_ends, sta);
|
||||
}
|
||||
|
||||
// For FilterExpr unit tests.
|
||||
StringSeq
|
||||
filter_expr_to_postfix(const char* expr,
|
||||
bool bool_props_as_int)
|
||||
filter_expr_to_postfix(const char* expr)
|
||||
{
|
||||
Report *report = Sta::sta()->report();
|
||||
return filterExprToPostfix(expr, bool_props_as_int, report);
|
||||
return filterExprToPostfix(expr, report);
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////
|
||||
|
|
|
|||
16
sdc/Sdc.tcl
16
sdc/Sdc.tcl
|
|
@ -393,7 +393,7 @@ proc get_cells { args } {
|
|||
}
|
||||
}
|
||||
if [info exists keys(-filter)] {
|
||||
set insts [filter_insts $keys(-filter) $insts 1]
|
||||
set insts [filter_insts $keys(-filter) $insts]
|
||||
}
|
||||
return $insts
|
||||
}
|
||||
|
|
@ -436,7 +436,7 @@ proc get_clocks { args } {
|
|||
}
|
||||
}
|
||||
if [info exists keys(-filter)] {
|
||||
set clocks [filter_clocks $keys(-filter) $clocks 1]
|
||||
set clocks [filter_clocks $keys(-filter) $clocks]
|
||||
}
|
||||
return $clocks
|
||||
}
|
||||
|
|
@ -517,7 +517,7 @@ proc get_lib_cells { args } {
|
|||
}
|
||||
}
|
||||
if [info exists keys(-filter)] {
|
||||
set cells [filter_lib_cells $keys(-filter) $cells 1]
|
||||
set cells [filter_lib_cells $keys(-filter) $cells]
|
||||
}
|
||||
return $cells
|
||||
}
|
||||
|
|
@ -621,7 +621,7 @@ proc get_lib_pins { args } {
|
|||
}
|
||||
}
|
||||
if [info exists keys(-filter)] {
|
||||
set ports [filter_lib_pins $keys(-filter) $ports 1]
|
||||
set ports [filter_lib_pins $keys(-filter) $ports]
|
||||
}
|
||||
return $ports
|
||||
}
|
||||
|
|
@ -671,7 +671,7 @@ proc get_libs { args } {
|
|||
}
|
||||
}
|
||||
if [info exists keys(-filter)] {
|
||||
set libs [filter_liberty_libraries $keys(-filter) $libs 1]
|
||||
set libs [filter_liberty_libraries $keys(-filter) $libs]
|
||||
}
|
||||
return $libs
|
||||
}
|
||||
|
|
@ -772,7 +772,7 @@ proc get_nets { args } {
|
|||
}
|
||||
}
|
||||
if [info exists keys(-filter)] {
|
||||
set nets [filter_nets $keys(-filter) $nets 1]
|
||||
set nets [filter_nets $keys(-filter) $nets]
|
||||
}
|
||||
return $nets
|
||||
}
|
||||
|
|
@ -863,7 +863,7 @@ proc get_pins { args } {
|
|||
}
|
||||
}
|
||||
if [info exists keys(-filter)] {
|
||||
set pins [filter_pins $keys(-filter) $pins 1]
|
||||
set pins [filter_pins $keys(-filter) $pins]
|
||||
}
|
||||
return $pins
|
||||
}
|
||||
|
|
@ -919,7 +919,7 @@ proc get_ports { args } {
|
|||
}
|
||||
}
|
||||
if [info exists keys(-filter)] {
|
||||
set ports [filter_ports $keys(-filter) $ports 1]
|
||||
set ports [filter_ports $keys(-filter) $ports]
|
||||
}
|
||||
return $ports
|
||||
}
|
||||
|
|
|
|||
|
|
@ -564,7 +564,7 @@ PropertyValue::to_string(const Network *network) const
|
|||
case Type::float_:
|
||||
return unit_->asString(float_, 6);
|
||||
case Type::bool_:
|
||||
// true/false would be better but these are TCL true/false values.
|
||||
// These are TCL true/false values.
|
||||
if (bool_)
|
||||
return "1";
|
||||
else
|
||||
|
|
|
|||
|
|
@ -300,7 +300,7 @@ proc get_timing_edges_cmd { cmd cmd_args } {
|
|||
cmd_usage_error $cmd
|
||||
}
|
||||
if [info exists keys(-filter)] {
|
||||
set arcs [filter_timing_arcs $keys(-filter) $arcs 1]
|
||||
set arcs [filter_timing_arcs $keys(-filter) $arcs]
|
||||
}
|
||||
return $arcs
|
||||
}
|
||||
|
|
|
|||
|
|
@ -280,7 +280,7 @@ using namespace sta;
|
|||
}
|
||||
|
||||
%typemap(in) std::string_view {
|
||||
int length;
|
||||
Tcl_Size length;
|
||||
const char *str = Tcl_GetStringFromObj($input, &length);
|
||||
$1 = std::string_view(str, length);
|
||||
}
|
||||
|
|
@ -415,7 +415,7 @@ using namespace sta;
|
|||
}
|
||||
|
||||
%typemap(in) Transition* {
|
||||
int length;
|
||||
Tcl_Size length;
|
||||
const char *arg = Tcl_GetStringFromObj($input, &length);
|
||||
Transition *tr = Transition::find(std::string_view(arg, length));
|
||||
if (tr == nullptr) {
|
||||
|
|
@ -433,7 +433,7 @@ using namespace sta;
|
|||
}
|
||||
|
||||
%typemap(in) RiseFall* {
|
||||
int length;
|
||||
Tcl_Size length;
|
||||
const char *arg = Tcl_GetStringFromObj($input, &length);
|
||||
const RiseFall *rf = RiseFall::find(std::string_view(arg, length));
|
||||
if (rf == nullptr) {
|
||||
|
|
@ -451,7 +451,7 @@ using namespace sta;
|
|||
}
|
||||
|
||||
%typemap(in) RiseFallBoth* {
|
||||
int length;
|
||||
Tcl_Size length;
|
||||
const char *arg = Tcl_GetStringFromObj($input, &length);
|
||||
const RiseFallBoth *rf = RiseFallBoth::find(std::string_view(arg, length));
|
||||
if (rf == nullptr) {
|
||||
|
|
@ -469,7 +469,7 @@ using namespace sta;
|
|||
}
|
||||
|
||||
%typemap(in) PortDirection* {
|
||||
int length;
|
||||
Tcl_Size length;
|
||||
const char *arg = Tcl_GetStringFromObj($input, &length);
|
||||
PortDirection *dir = PortDirection::find(arg);
|
||||
if (dir == nullptr) {
|
||||
|
|
@ -481,7 +481,7 @@ using namespace sta;
|
|||
}
|
||||
|
||||
%typemap(in) TimingRole* {
|
||||
int length;
|
||||
Tcl_Size length;
|
||||
const char *arg = Tcl_GetStringFromObj($input, &length);
|
||||
const TimingRole *role = TimingRole::find(arg);
|
||||
if (role)
|
||||
|
|
@ -498,7 +498,7 @@ using namespace sta;
|
|||
}
|
||||
|
||||
%typemap(in) LogicValue {
|
||||
int length;
|
||||
Tcl_Size length;
|
||||
std::string arg = Tcl_GetStringFromObj($input, &length);
|
||||
if (arg == "0" || stringEqual(arg, "zero"))
|
||||
$1 = LogicValue::zero;
|
||||
|
|
@ -517,7 +517,7 @@ using namespace sta;
|
|||
}
|
||||
|
||||
%typemap(in) AnalysisType {
|
||||
int length;
|
||||
Tcl_Size length;
|
||||
const char *arg = Tcl_GetStringFromObj($input, &length);
|
||||
if (stringEqual(arg, "single"))
|
||||
$1 = AnalysisType::single;
|
||||
|
|
@ -831,7 +831,7 @@ using namespace sta;
|
|||
}
|
||||
|
||||
%typemap(in) MinMax* {
|
||||
int length;
|
||||
Tcl_Size length;
|
||||
char *arg = Tcl_GetStringFromObj($input, &length);
|
||||
// Swig is retarded and drops const on args.
|
||||
MinMax *min_max = const_cast<MinMax*>(MinMax::find(arg));
|
||||
|
|
@ -852,7 +852,7 @@ using namespace sta;
|
|||
}
|
||||
|
||||
%typemap(in) MinMaxAll* {
|
||||
int length;
|
||||
Tcl_Size length;
|
||||
char *arg = Tcl_GetStringFromObj($input, &length);
|
||||
// Swig is retarded and drops const on args.
|
||||
MinMaxAll *min_max = const_cast<MinMaxAll*>(MinMaxAll::find(arg));
|
||||
|
|
@ -865,7 +865,7 @@ using namespace sta;
|
|||
}
|
||||
|
||||
%typemap(in) MinMaxAllNull* {
|
||||
int length;
|
||||
Tcl_Size length;
|
||||
char *arg = Tcl_GetStringFromObj($input, &length);
|
||||
if (stringEqual(arg, "NULL"))
|
||||
$1 = nullptr;
|
||||
|
|
@ -887,7 +887,7 @@ using namespace sta;
|
|||
|
||||
// SetupHold is typedef'd to MinMax.
|
||||
%typemap(in) const SetupHold* {
|
||||
int length;
|
||||
Tcl_Size length;
|
||||
char *arg = Tcl_GetStringFromObj($input, &length);
|
||||
// Swig is retarded and drops const on args.
|
||||
if (stringEqual(arg, "hold")
|
||||
|
|
@ -904,7 +904,7 @@ using namespace sta;
|
|||
|
||||
// SetupHoldAll is typedef'd to MinMaxAll.
|
||||
%typemap(in) const SetupHoldAll* {
|
||||
int length;
|
||||
Tcl_Size length;
|
||||
char *arg = Tcl_GetStringFromObj($input, &length);
|
||||
// Swig is retarded and drops const on args.
|
||||
if (stringEqual(arg, "hold")
|
||||
|
|
@ -925,7 +925,7 @@ using namespace sta;
|
|||
|
||||
// EarlyLate is typedef'd to MinMax.
|
||||
%typemap(in) const EarlyLate* {
|
||||
int length;
|
||||
Tcl_Size length;
|
||||
char *arg = Tcl_GetStringFromObj($input, &length);
|
||||
// Swig is retarded and drops const on args.
|
||||
EarlyLate *early_late = const_cast<EarlyLate*>(EarlyLate::find(arg));
|
||||
|
|
@ -939,7 +939,7 @@ using namespace sta;
|
|||
|
||||
// EarlyLateAll is typedef'd to MinMaxAll.
|
||||
%typemap(in) const EarlyLateAll* {
|
||||
int length;
|
||||
Tcl_Size length;
|
||||
char *arg = Tcl_GetStringFromObj($input, &length);
|
||||
// Swig is retarded and drops const on args.
|
||||
EarlyLateAll *early_late = const_cast<EarlyLateAll*>(EarlyLateAll::find(arg));
|
||||
|
|
@ -952,7 +952,7 @@ using namespace sta;
|
|||
}
|
||||
|
||||
%typemap(in) TimingDerateType {
|
||||
int length;
|
||||
Tcl_Size length;
|
||||
char *arg = Tcl_GetStringFromObj($input, &length);
|
||||
if (stringEqual(arg, "net_delay"))
|
||||
$1 = TimingDerateType::net_delay;
|
||||
|
|
@ -967,7 +967,7 @@ using namespace sta;
|
|||
}
|
||||
|
||||
%typemap(in) TimingDerateCellType {
|
||||
int length;
|
||||
Tcl_Size length;
|
||||
char *arg = Tcl_GetStringFromObj($input, &length);
|
||||
if (stringEqual(arg, "cell_delay"))
|
||||
$1 = TimingDerateCellType::cell_delay;
|
||||
|
|
@ -980,7 +980,7 @@ using namespace sta;
|
|||
}
|
||||
|
||||
%typemap(in) PathClkOrData {
|
||||
int length;
|
||||
Tcl_Size length;
|
||||
std::string arg = Tcl_GetStringFromObj($input, &length);
|
||||
if (stringEqual(arg, "clk"))
|
||||
$1 = PathClkOrData::clk;
|
||||
|
|
@ -993,7 +993,7 @@ using namespace sta;
|
|||
}
|
||||
|
||||
%typemap(in) ReportSortBy {
|
||||
int length;
|
||||
Tcl_Size length;
|
||||
std::string arg = Tcl_GetStringFromObj($input, &length);
|
||||
if (stringEqual(arg, "group"))
|
||||
$1 = sort_by_group;
|
||||
|
|
@ -1006,7 +1006,7 @@ using namespace sta;
|
|||
}
|
||||
|
||||
%typemap(in) ReportPathFormat {
|
||||
int length;
|
||||
Tcl_Size length;
|
||||
std::string arg = Tcl_GetStringFromObj($input, &length);
|
||||
if (stringEqual(arg, "full"))
|
||||
$1 = ReportPathFormat::full;
|
||||
|
|
@ -1188,7 +1188,7 @@ using namespace sta;
|
|||
if (Tcl_ListObjGetElements(interp, $input, &argc, &argv) == TCL_OK
|
||||
&& argc > 0) {
|
||||
for (int i = 0; i < argc; i++) {
|
||||
int length;
|
||||
Tcl_Size length;
|
||||
const char *mode_name = Tcl_GetStringFromObj(argv[i], &length);
|
||||
Mode *mode = sta->findMode(mode_name);
|
||||
if (mode)
|
||||
|
|
@ -1215,7 +1215,7 @@ using namespace sta;
|
|||
|
||||
%typemap(in) Scene* {
|
||||
sta::Sta *sta = Sta::sta();
|
||||
int length;
|
||||
Tcl_Size length;
|
||||
std::string scene_name = Tcl_GetStringFromObj($input, &length);
|
||||
// parse_scene_or_all support depreated 11/21/2025
|
||||
if (scene_name == "NULL")
|
||||
|
|
@ -1248,7 +1248,7 @@ using namespace sta;
|
|||
if (Tcl_ListObjGetElements(interp, $input, &argc, &argv) == TCL_OK
|
||||
&& argc > 0) {
|
||||
for (int i = 0; i < argc; i++) {
|
||||
int length;
|
||||
Tcl_Size length;
|
||||
const char *scene_name = Tcl_GetStringFromObj(argv[i], &length);
|
||||
Scene *scene = sta->findScene(scene_name);
|
||||
if (scene)
|
||||
|
|
@ -1274,7 +1274,7 @@ using namespace sta;
|
|||
}
|
||||
|
||||
%typemap(in) PropertyValue {
|
||||
int length;
|
||||
Tcl_Size length;
|
||||
const char *arg = Tcl_GetStringFromObj($input, &length);
|
||||
$1 = PropertyValue(arg);
|
||||
}
|
||||
|
|
@ -1411,7 +1411,7 @@ using namespace sta;
|
|||
}
|
||||
|
||||
%typemap(in) CircuitSim {
|
||||
int length;
|
||||
Tcl_Size length;
|
||||
std::string arg = Tcl_GetStringFromObj($input, &length);
|
||||
if (stringEqual(arg, "hspice"))
|
||||
$1 = CircuitSim::hspice;
|
||||
|
|
|
|||
|
|
@ -40,7 +40,7 @@ tclListStringSeq(Tcl_Obj *const source,
|
|||
StringSeq seq;
|
||||
if (Tcl_ListObjGetElements(interp, source, &argc, &argv) == TCL_OK) {
|
||||
for (int i = 0; i < argc; i++) {
|
||||
int length;
|
||||
Tcl_Size length;
|
||||
const char *str = Tcl_GetStringFromObj(argv[i], &length);
|
||||
seq.push_back(str);
|
||||
}
|
||||
|
|
@ -58,7 +58,7 @@ tclListStringSeqPtr(Tcl_Obj *const source,
|
|||
if (Tcl_ListObjGetElements(interp, source, &argc, &argv) == TCL_OK) {
|
||||
StringSeq *seq = new StringSeq;
|
||||
for (int i = 0; i < argc; i++) {
|
||||
int length;
|
||||
Tcl_Size length;
|
||||
const char *str = Tcl_GetStringFromObj(argv[i], &length);
|
||||
seq->push_back(str);
|
||||
}
|
||||
|
|
@ -78,7 +78,7 @@ tclListStringSet(Tcl_Obj *const source,
|
|||
if (Tcl_ListObjGetElements(interp, source, &argc, &argv) == TCL_OK) {
|
||||
StringSet *set = new StringSet;
|
||||
for (int i = 0; i < argc; i++) {
|
||||
int length;
|
||||
Tcl_Size length;
|
||||
const char *str = Tcl_GetStringFromObj(argv[i], &length);
|
||||
set->insert(str);
|
||||
}
|
||||
|
|
@ -183,11 +183,11 @@ arcDcalcArgTcl(Tcl_Obj *obj,
|
|||
{
|
||||
Sta *sta = Sta::sta();
|
||||
sta->ensureGraph();
|
||||
int list_argc;
|
||||
Tcl_Size list_argc;
|
||||
Tcl_Obj **list_argv;
|
||||
if (Tcl_ListObjGetElements(interp, obj, &list_argc, &list_argv) == TCL_OK) {
|
||||
const char *input_delay = "0.0";
|
||||
int length;
|
||||
Tcl_Size length;
|
||||
if (list_argc == 6)
|
||||
input_delay = Tcl_GetStringFromObj(list_argv[5], &length);
|
||||
if (list_argc == 5 || list_argc == 6) {
|
||||
|
|
|
|||
|
|
@ -33,13 +33,13 @@ namespace eval sta {
|
|||
# Default digits to print after decimal point for reporting commands.
|
||||
set ::sta_report_default_digits 2
|
||||
|
||||
trace variable ::sta_report_default_digits "rw" \
|
||||
trace add variable ::sta_report_default_digits {read write} \
|
||||
sta::trace_report_default_digits
|
||||
|
||||
proc trace_report_default_digits { name1 name2 op } {
|
||||
global sta_report_default_digits
|
||||
|
||||
if { $op == "w" } {
|
||||
if { $op == "write" } {
|
||||
if { !([string is integer $sta_report_default_digits] \
|
||||
&& $sta_report_default_digits >= 0) } {
|
||||
sta_error 590 "sta_report_default_digits must be a positive integer."
|
||||
|
|
@ -47,7 +47,7 @@ proc trace_report_default_digits { name1 name2 op } {
|
|||
}
|
||||
}
|
||||
|
||||
trace variable ::sta_crpr_enabled "rw" \
|
||||
trace add variable ::sta_crpr_enabled {read write} \
|
||||
sta::trace_crpr_enabled
|
||||
|
||||
proc trace_crpr_enabled { name1 name2 op } {
|
||||
|
|
@ -55,15 +55,15 @@ proc trace_crpr_enabled { name1 name2 op } {
|
|||
crpr_enabled set_crpr_enabled
|
||||
}
|
||||
|
||||
trace variable ::sta_crpr_mode "rw" \
|
||||
trace add variable ::sta_crpr_mode {read write} \
|
||||
sta::trace_crpr_mode
|
||||
|
||||
proc trace_crpr_mode { name1 name2 op } {
|
||||
global sta_crpr_mode
|
||||
|
||||
if { $op == "r" } {
|
||||
if { $op == "read" } {
|
||||
set sta_crpr_mode [crpr_mode]
|
||||
} elseif { $op == "w" } {
|
||||
} elseif { $op == "write" } {
|
||||
if { $sta_crpr_mode == "same_pin" || $sta_crpr_mode == "same_transition" } {
|
||||
set_crpr_mode $sta_crpr_mode
|
||||
} else {
|
||||
|
|
@ -72,7 +72,7 @@ proc trace_crpr_mode { name1 name2 op } {
|
|||
}
|
||||
}
|
||||
|
||||
trace variable ::sta_cond_default_arcs_enabled "rw" \
|
||||
trace add variable ::sta_cond_default_arcs_enabled {read write} \
|
||||
sta::trace_cond_default_arcs_enabled
|
||||
|
||||
proc trace_cond_default_arcs_enabled { name1 name2 op } {
|
||||
|
|
@ -80,7 +80,7 @@ proc trace_cond_default_arcs_enabled { name1 name2 op } {
|
|||
cond_default_arcs_enabled set_cond_default_arcs_enabled
|
||||
}
|
||||
|
||||
trace variable ::sta_gated_clock_checks_enabled "rw" \
|
||||
trace add variable ::sta_gated_clock_checks_enabled {read write} \
|
||||
sta::trace_gated_clk_checks_enabled
|
||||
|
||||
proc trace_gated_clk_checks_enabled { name1 name2 op } {
|
||||
|
|
@ -88,7 +88,7 @@ proc trace_gated_clk_checks_enabled { name1 name2 op } {
|
|||
gated_clk_checks_enabled set_gated_clk_checks_enabled
|
||||
}
|
||||
|
||||
trace variable ::sta_internal_bidirect_instance_paths_enabled "rw" \
|
||||
trace add variable ::sta_internal_bidirect_instance_paths_enabled {read write} \
|
||||
sta::trace_internal_bidirect_instance_paths_enabled
|
||||
|
||||
proc trace_internal_bidirect_instance_paths_enabled { name1 name2 op } {
|
||||
|
|
@ -96,7 +96,7 @@ proc trace_internal_bidirect_instance_paths_enabled { name1 name2 op } {
|
|||
bidirect_inst_paths_enabled set_bidirect_inst_paths_enabled
|
||||
}
|
||||
|
||||
trace variable ::sta_clock_through_tristate_enabled "rw" \
|
||||
trace add variable ::sta_clock_through_tristate_enabled {read write} \
|
||||
sta::trace_clock_through_tristate_enabled
|
||||
|
||||
proc trace_clock_through_tristate_enabled { name1 name2 op } {
|
||||
|
|
@ -104,7 +104,7 @@ proc trace_clock_through_tristate_enabled { name1 name2 op } {
|
|||
clk_thru_tristate_enabled set_clk_thru_tristate_enabled
|
||||
}
|
||||
|
||||
trace variable ::sta_preset_clear_arcs_enabled "rw" \
|
||||
trace add variable ::sta_preset_clear_arcs_enabled {read write} \
|
||||
sta::trace_preset_clr_arcs_enabled
|
||||
|
||||
proc trace_preset_clr_arcs_enabled { name1 name2 op } {
|
||||
|
|
@ -112,7 +112,7 @@ proc trace_preset_clr_arcs_enabled { name1 name2 op } {
|
|||
preset_clr_arcs_enabled set_preset_clr_arcs_enabled
|
||||
}
|
||||
|
||||
trace variable ::sta_recovery_removal_checks_enabled "rw" \
|
||||
trace add variable ::sta_recovery_removal_checks_enabled {read write} \
|
||||
sta::trace_recovery_removal_checks_enabled
|
||||
|
||||
proc trace_recovery_removal_checks_enabled { name1 name2 op } {
|
||||
|
|
@ -120,7 +120,7 @@ proc trace_recovery_removal_checks_enabled { name1 name2 op } {
|
|||
recovery_removal_checks_enabled set_recovery_removal_checks_enabled
|
||||
}
|
||||
|
||||
trace variable ::sta_dynamic_loop_breaking "rw" \
|
||||
trace add variable ::sta_dynamic_loop_breaking {read write} \
|
||||
sta::trace_dynamic_loop_breaking
|
||||
|
||||
proc trace_dynamic_loop_breaking { name1 name2 op } {
|
||||
|
|
@ -128,7 +128,7 @@ proc trace_dynamic_loop_breaking { name1 name2 op } {
|
|||
dynamic_loop_breaking set_dynamic_loop_breaking
|
||||
}
|
||||
|
||||
trace variable ::sta_input_port_default_clock "rw" \
|
||||
trace add variable ::sta_input_port_default_clock {read write} \
|
||||
sta::trace_input_port_default_clock
|
||||
|
||||
proc trace_input_port_default_clock { name1 name2 op } {
|
||||
|
|
@ -136,7 +136,7 @@ proc trace_input_port_default_clock { name1 name2 op } {
|
|||
use_default_arrival_clock set_use_default_arrival_clock
|
||||
}
|
||||
|
||||
trace variable ::sta_propagate_all_clocks "rw" \
|
||||
trace add variable ::sta_propagate_all_clocks {read write} \
|
||||
sta::trace_propagate_all_clocks
|
||||
|
||||
proc trace_propagate_all_clocks { name1 name2 op } {
|
||||
|
|
@ -144,7 +144,7 @@ proc trace_propagate_all_clocks { name1 name2 op } {
|
|||
propagate_all_clocks set_propagate_all_clocks
|
||||
}
|
||||
|
||||
trace variable ::sta_propagate_gated_clock_enable "rw" \
|
||||
trace add variable ::sta_propagate_gated_clock_enable {read write} \
|
||||
sta::trace_propagate_gated_clock_enable
|
||||
|
||||
proc trace_propagate_gated_clock_enable { name1 name2 op } {
|
||||
|
|
@ -152,15 +152,15 @@ proc trace_propagate_gated_clock_enable { name1 name2 op } {
|
|||
propagate_gated_clock_enable set_propagate_gated_clock_enable
|
||||
}
|
||||
|
||||
trace variable ::sta_pocv_mode "rw" \
|
||||
trace add variable ::sta_pocv_mode {read write} \
|
||||
sta::trace_pocv_mode
|
||||
|
||||
proc trace_pocv_mode { name1 name2 op } {
|
||||
global sta_pocv_mode
|
||||
|
||||
if { $op == "r" } {
|
||||
if { $op == "read" } {
|
||||
set sta_pocv_mode [pocv_mode]
|
||||
} elseif { $op == "w" } {
|
||||
} elseif { $op == "write" } {
|
||||
if { $sta_pocv_mode == "scalar" \
|
||||
|| $sta_pocv_mode == "normal" \
|
||||
|| $sta_pocv_mode == "skew_normal" } {
|
||||
|
|
@ -171,15 +171,15 @@ proc trace_pocv_mode { name1 name2 op } {
|
|||
}
|
||||
}
|
||||
|
||||
trace variable ::sta_pocv_quantile "rw" \
|
||||
trace add variable ::sta_pocv_quantile {read write} \
|
||||
sta::trace_pocv_quantile
|
||||
|
||||
proc trace_pocv_quantile { name1 name2 op } {
|
||||
global sta_pocv_quantile
|
||||
|
||||
if { $op == "r" } {
|
||||
if { $op == "read" } {
|
||||
set sta_pocv_quantile [pocv_quantile]
|
||||
} elseif { $op == "w" } {
|
||||
} elseif { $op == "write" } {
|
||||
if { [string is double $sta_pocv_quantile] \
|
||||
&& $sta_pocv_quantile >= 0.0 } {
|
||||
set_pocv_quantile $sta_pocv_quantile
|
||||
|
|
@ -194,9 +194,9 @@ proc trace_pocv_quantile { name1 name2 op } {
|
|||
proc trace_boolean_var { op var_name get_proc set_proc } {
|
||||
upvar 1 $var_name var
|
||||
|
||||
if { $op == "r" } {
|
||||
if { $op == "read" } {
|
||||
set var [$get_proc]
|
||||
} elseif { $op == "w" } {
|
||||
} elseif { $op == "write" } {
|
||||
if { $var == 0 } {
|
||||
$set_proc 0
|
||||
} elseif { $var == 1 } {
|
||||
|
|
|
|||
Binary file not shown.
|
|
@ -1,24 +1,11 @@
|
|||
[get_cells -filter liberty_cell==BUFx2_ASAP7_75t_R *]
|
||||
u1
|
||||
[get_clocks -filter is_virtual==0 *]
|
||||
clk
|
||||
[get_clocks -filter is_virtual==1 *]
|
||||
vclk
|
||||
[get_clocks -filter is_virtual *]
|
||||
vclk
|
||||
[get_clocks -filter is_virtual&&is_generated *]
|
||||
[get_clocks -filter is_virtual&&is_generated==0 *]
|
||||
vclk
|
||||
[get_clocks -filter is_virtual||is_generated *]
|
||||
vclk
|
||||
[get_clocks -filter is_virtual==0||is_generated *]
|
||||
clk
|
||||
[get_lib_cells -filter is_buffer==1 *]
|
||||
[get_lib_cells -filter is_buffer *]
|
||||
asap7_small/BUFx2_ASAP7_75t_R
|
||||
[get_lib_cells -filter is_inverter==0 *]
|
||||
asap7_small/AND2x2_ASAP7_75t_R
|
||||
asap7_small/BUFx2_ASAP7_75t_R
|
||||
asap7_small/DFFHQx4_ASAP7_75t_R
|
||||
[get_lib_cells -filter is_inverter *]
|
||||
asap7_small/INVx2_ASAP7_75t_R
|
||||
[get_lib_pins -filter direction==input BUFx2_ASAP7_75t_R/*]
|
||||
A
|
||||
[get_lib_pins -filter direction==output BUFx2_ASAP7_75t_R/*]
|
||||
|
|
@ -54,9 +41,22 @@ in2
|
|||
out
|
||||
[get_cells -filter {name ~= *r1*} *]
|
||||
Error: 2600 -filter parsing failed at '~= *r1*'.
|
||||
direction == input && name =~ clk*
|
||||
clk1
|
||||
clk2
|
||||
clk3
|
||||
(direction == input) && (name =~ clk*)"
|
||||
clk1
|
||||
clk2
|
||||
clk3
|
||||
[get_clocks -filter is_virtual||is_generated *]
|
||||
vclk
|
||||
[get_clocks -filter is_virtual==0 *]
|
||||
clk
|
||||
[get_clocks -filter is_virtual==false *]
|
||||
clk
|
||||
[get_clocks -filter is_virtual==1 *]
|
||||
vclk
|
||||
[get_clocks -filter is_virtual==true *]
|
||||
vclk
|
||||
{direction == input} {name =~ clk*} {is_clock == 1} && &&
|
||||
|
|
|
|||
|
|
@ -5,29 +5,16 @@ link_design top
|
|||
create_clock -name clk -period 500 {clk1 clk2 clk3}
|
||||
create_clock -name vclk -period 1000
|
||||
|
||||
# Test filters for each SDC get_* command.
|
||||
puts {[get_cells -filter liberty_cell==BUFx2_ASAP7_75t_R *]}
|
||||
report_object_full_names [get_cells -filter liberty_cell==BUFx2_ASAP7_75t_R *]
|
||||
|
||||
puts {[get_clocks -filter is_virtual==0 *]}
|
||||
report_object_full_names [get_clocks -filter is_virtual==0 *]
|
||||
puts {[get_clocks -filter is_virtual==1 *]}
|
||||
report_object_full_names [get_clocks -filter is_virtual==1 *]
|
||||
puts {[get_clocks -filter is_virtual *]}
|
||||
report_object_full_names [get_clocks -filter is_virtual *]
|
||||
puts {[get_clocks -filter is_virtual&&is_generated *]}
|
||||
report_object_full_names [get_clocks -filter is_virtual&&is_generated *]
|
||||
puts {[get_clocks -filter is_virtual&&is_generated==0 *]}
|
||||
report_object_full_names [get_clocks -filter is_virtual&&is_generated==0 *]
|
||||
puts {[get_clocks -filter is_virtual||is_generated *]}
|
||||
report_object_full_names [get_clocks -filter is_virtual||is_generated *]
|
||||
puts {[get_clocks -filter is_virtual==0||is_generated *]}
|
||||
report_object_full_names [get_clocks -filter is_virtual==0||is_generated *]
|
||||
|
||||
puts {[get_lib_cells -filter is_buffer==1 *]}
|
||||
report_object_full_names [get_lib_cells -filter is_buffer==1 *]
|
||||
puts {[get_lib_cells -filter is_inverter==0 *]}
|
||||
report_object_full_names [get_lib_cells -filter is_inverter==0 *]
|
||||
puts {[get_lib_cells -filter is_buffer *]}
|
||||
report_object_full_names [get_lib_cells -filter is_buffer *]
|
||||
puts {[get_lib_cells -filter is_inverter *]}
|
||||
report_object_full_names [get_lib_cells -filter is_inverter *]
|
||||
|
||||
puts {[get_lib_pins -filter direction==input BUFx2_ASAP7_75t_R/*]}
|
||||
report_object_full_names [get_lib_pins -filter direction==input BUFx2_ASAP7_75t_R/*]
|
||||
|
|
@ -55,9 +42,32 @@ puts {[get_cells -filter {name ~= *r1*} *]}
|
|||
catch {get_cells -filter {name ~= *r1*} *} result
|
||||
puts $result
|
||||
|
||||
# AND pattern match expr
|
||||
# AND expr
|
||||
puts {direction == input && name =~ clk*}
|
||||
report_object_names [get_ports -filter "direction == input && name =~ clk*" *]
|
||||
# parens around sub-exprs
|
||||
puts {(direction == input) && (name =~ clk*)"}
|
||||
report_object_names [get_ports -filter "(direction == input) && (name =~ clk*)" *]
|
||||
|
||||
sta::filter_expr_to_postfix "direction == input && name =~ clk* && is_clock" 1
|
||||
# OR expr
|
||||
puts {[get_clocks -filter is_virtual||is_generated *]}
|
||||
report_object_full_names [get_clocks -filter is_virtual||is_generated *]
|
||||
|
||||
|
||||
# unary==0 / unary==false
|
||||
puts {[get_clocks -filter is_virtual==0 *]}
|
||||
report_object_full_names [get_clocks -filter is_virtual==0 *]
|
||||
puts {[get_clocks -filter is_virtual==false *]}
|
||||
report_object_full_names [get_clocks -filter is_virtual==false *]
|
||||
|
||||
# unary==1 / unary==true
|
||||
puts {[get_clocks -filter is_virtual==1 *]}
|
||||
report_object_full_names [get_clocks -filter is_virtual==1 *]
|
||||
puts {[get_clocks -filter is_virtual==true *]}
|
||||
report_object_full_names [get_clocks -filter is_virtual==true *]
|
||||
|
||||
# glob pattern with . (literal dot, no match symantics)
|
||||
report_object_full_names [get_cells -filter {name =~ .1} *]
|
||||
|
||||
puts [sta::filter_expr_to_postfix "direction == input && name =~ clk* && is_clock"]
|
||||
|
||||
|
|
|
|||
|
|
@ -5,6 +5,7 @@ Y
|
|||
[get_lib_pins -of_objects [get_lib_cells *]]
|
||||
A
|
||||
A
|
||||
A
|
||||
B
|
||||
CLK
|
||||
D
|
||||
|
|
@ -13,3 +14,4 @@ IQN
|
|||
Q
|
||||
Y
|
||||
Y
|
||||
Y
|
||||
|
|
|
|||
|
|
@ -11,9 +11,11 @@ vclk
|
|||
asap7_small/AND2x2_ASAP7_75t_R
|
||||
asap7_small/BUFx2_ASAP7_75t_R
|
||||
asap7_small/DFFHQx4_ASAP7_75t_R
|
||||
asap7_small/INVx2_ASAP7_75t_R
|
||||
[get_lib_pins]
|
||||
A
|
||||
A
|
||||
A
|
||||
B
|
||||
CLK
|
||||
D
|
||||
|
|
@ -22,6 +24,7 @@ IQN
|
|||
Q
|
||||
Y
|
||||
Y
|
||||
Y
|
||||
[get_libs]
|
||||
asap7_small
|
||||
[get_nets]
|
||||
|
|
|
|||
|
|
@ -9,9 +9,11 @@ vclk
|
|||
asap7_small/AND2x2_ASAP7_75t_R
|
||||
asap7_small/BUFx2_ASAP7_75t_R
|
||||
asap7_small/DFFHQx4_ASAP7_75t_R
|
||||
asap7_small/INVx2_ASAP7_75t_R
|
||||
[get_lib_pins [get_lib_pins]]
|
||||
A
|
||||
A
|
||||
A
|
||||
B
|
||||
CLK
|
||||
D
|
||||
|
|
@ -20,6 +22,7 @@ IQN
|
|||
Q
|
||||
Y
|
||||
Y
|
||||
Y
|
||||
[get_libs [get_libs]]
|
||||
asap7_small
|
||||
[get_nets [get_nets]]
|
||||
|
|
|
|||
|
|
@ -176,11 +176,10 @@ proc run_tests {} {
|
|||
run_test $test
|
||||
}
|
||||
}
|
||||
write_failure_file
|
||||
}
|
||||
|
||||
proc run_test { test } {
|
||||
global result_dir diff_file errors diff_options
|
||||
global result_dir diff_file errors diff_options failed_tests
|
||||
|
||||
puts -nonewline $test
|
||||
flush stdout
|
||||
|
|
@ -267,8 +266,6 @@ proc run_tests_parallel {} {
|
|||
vwait reg_parallel_job_done
|
||||
}
|
||||
}
|
||||
# update results/failures and results/diffs
|
||||
write_failure_file
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -432,26 +429,21 @@ proc test_failed { test reason } {
|
|||
}
|
||||
lappend failed_tests $test
|
||||
incr errors($reason)
|
||||
append_diff_file $test
|
||||
}
|
||||
|
||||
proc write_failure_file {} {
|
||||
global failure_file failed_tests failed_tests_summery
|
||||
proc append_diff_file { test } {
|
||||
global failure_file
|
||||
global diff_file diff_options
|
||||
|
||||
set fail_ch [open $failure_file "a"]
|
||||
foreach test $failed_tests {
|
||||
if { ![info exists failed_tests_summery($test)] } {
|
||||
puts $fail_ch $test
|
||||
|
||||
# Append diff to results/diffs
|
||||
set log_file [test_log_file $test]
|
||||
set ok_file [test_ok_file $test]
|
||||
catch [concat exec diff $diff_options $ok_file $log_file >> $diff_file]
|
||||
|
||||
set failed_tests_summery($test) 1
|
||||
}
|
||||
}
|
||||
puts $fail_ch $test
|
||||
close $fail_ch
|
||||
|
||||
# Append diff to results/diffs
|
||||
set log_file [test_log_file $test]
|
||||
set ok_file [test_ok_file $test]
|
||||
catch [concat exec diff $diff_options $ok_file $log_file >> $diff_file]
|
||||
}
|
||||
|
||||
# Error messages can be found in "valgrind/memcheck/mc_errcontext.c".
|
||||
|
|
@ -530,6 +522,10 @@ proc show_summary {} {
|
|||
global app_path app
|
||||
|
||||
puts "------------------------------------------------------"
|
||||
if { $valgrind_shared_lib_failure } {
|
||||
puts "WARNING: valgrind failed because the executable is not statically linked."
|
||||
}
|
||||
puts "See $result_dir for log files"
|
||||
set test_count [llength $tests]
|
||||
if { [found_errors] } {
|
||||
if { $errors(error) != 0 } {
|
||||
|
|
@ -556,10 +552,6 @@ proc show_summary {} {
|
|||
} else {
|
||||
puts "Passed $test_count"
|
||||
}
|
||||
if { $valgrind_shared_lib_failure } {
|
||||
puts "WARNING: valgrind failed because the executable is not statically linked."
|
||||
}
|
||||
puts "See $result_dir for log files"
|
||||
}
|
||||
|
||||
proc found_errors {} {
|
||||
|
|
@ -590,22 +582,27 @@ proc save_ok_main {} {
|
|||
}
|
||||
} else {
|
||||
foreach test $argv {
|
||||
save_ok $test
|
||||
if { [lsearch [group_tests "all"] $test] == -1 } {
|
||||
puts "Error: test $test not found."
|
||||
} else {
|
||||
save_ok $test
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
# hook for pvt/public sync.
|
||||
proc save_ok { test } {
|
||||
if { [lsearch [group_tests "all"] $test] == -1 } {
|
||||
puts "Error: test $test not found."
|
||||
save_ok_file $test
|
||||
}
|
||||
|
||||
proc save_ok_file { test } {
|
||||
set ok_file [test_ok_file $test]
|
||||
set log_file [test_log_file $test]
|
||||
if { ! [file exists $log_file] } {
|
||||
puts "Error: log file $log_file not found."
|
||||
} else {
|
||||
set ok_file [test_ok_file $test]
|
||||
set log_file [test_log_file $test]
|
||||
if { ! [file exists $log_file] } {
|
||||
puts "Error: log file $log_file not found."
|
||||
} else {
|
||||
file copy -force $log_file $ok_file
|
||||
}
|
||||
file copy -force $log_file $ok_file
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -72,6 +72,11 @@ encapGetHandleProc(ClientData instanceData,
|
|||
static int
|
||||
encapBlockModeProc(ClientData instanceData, int mode);
|
||||
|
||||
static int
|
||||
encapClose2Proc(ClientData instanceData,
|
||||
Tcl_Interp *interp,
|
||||
int flags);
|
||||
|
||||
#if TCL_MAJOR_VERSION < 9
|
||||
static int
|
||||
encapCloseProc(ClientData instanceData, Tcl_Interp *interp);
|
||||
|
|
@ -97,13 +102,13 @@ Tcl_ChannelType tcl_encap_type_stdout = {
|
|||
#if TCL_MAJOR_VERSION < 9
|
||||
encapSeekProc,
|
||||
#else
|
||||
nullptr, // close2Proc
|
||||
nullptr, // seekProc unused
|
||||
#endif
|
||||
encapSetOptionProc,
|
||||
encapGetOptionProc,
|
||||
encapWatchProc,
|
||||
encapGetHandleProc,
|
||||
nullptr, // close2Proc
|
||||
encapClose2Proc,
|
||||
encapBlockModeProc,
|
||||
nullptr, // flushProc
|
||||
nullptr, // handlerProc
|
||||
|
|
@ -290,17 +295,31 @@ encapBlockModeProc(ClientData,
|
|||
return 0;
|
||||
}
|
||||
|
||||
// Close channel implementing CloseProc() or Close2Proc()
|
||||
static int
|
||||
closeChannel(ReportTcl *report)
|
||||
{
|
||||
report->logEnd();
|
||||
report->redirectFileEnd();
|
||||
report->redirectStringEnd();
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int
|
||||
encapClose2Proc(ClientData instanceData,
|
||||
Tcl_Interp *,
|
||||
int)
|
||||
{
|
||||
return closeChannel(reinterpret_cast<ReportTcl *>(instanceData));
|
||||
}
|
||||
|
||||
#if TCL_MAJOR_VERSION < 9
|
||||
|
||||
static int
|
||||
encapCloseProc(ClientData instanceData,
|
||||
Tcl_Interp *)
|
||||
{
|
||||
ReportTcl *report = reinterpret_cast<ReportTcl *>(instanceData);
|
||||
report->logEnd();
|
||||
report->redirectFileEnd();
|
||||
report->redirectStringEnd();
|
||||
return 0;
|
||||
return closeChannel(reinterpret_cast<ReportTcl *>(instanceData));
|
||||
}
|
||||
|
||||
static int
|
||||
|
|
|
|||
|
|
@ -28,6 +28,7 @@
|
|||
#include <cctype>
|
||||
#include <charconv>
|
||||
#include <system_error>
|
||||
#include <version>
|
||||
|
||||
namespace sta {
|
||||
|
||||
|
|
@ -56,12 +57,22 @@ std::pair<float, bool>
|
|||
stringFloat(const std::string &str)
|
||||
{
|
||||
float value;
|
||||
// OsX 15.xx and earlier clang do not support std::from_chars.
|
||||
#if defined(__cpp_lib_to_chars) && __cpp_lib_to_chars >= 201611L
|
||||
auto [ptr, ec] = std::from_chars(str.data(), str.data() + str.size(), value);
|
||||
if (ec == std::errc()
|
||||
&& *ptr == '\0')
|
||||
return {value, true};
|
||||
else
|
||||
return {0.0, false};
|
||||
#else
|
||||
char *ptr;
|
||||
value = strtof(str.data(), &ptr);
|
||||
if (!errno || *ptr != '\0')
|
||||
return {0.0, false};
|
||||
else
|
||||
return {value, true};
|
||||
#endif
|
||||
}
|
||||
|
||||
void
|
||||
|
|
|
|||
Loading…
Reference in New Issue