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test: Apply review feedback - part2 

- Remove stale line-number coverage comments (# Targets: line NNN, hit=0)
- Remove useless file-existence checks from verilog/sdf tests
- Delete 21 orphaned dcalc Tcl tests (C++ tests already cover them)
- Rename liberty_ccsn_ecsm -> liberty_ccsn (no ECSM libs available)
- Fix liberty_sky130_corners to use define_corners/-corner for real multi-corner testing
- Add report_checks per wireload model in liberty_wireload
- Fix test/regression to work from test/ directory (label mismatch)
- Refactor all module CMakeLists.txt with sta_module_tests() macro

Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
This commit is contained in:
Jaehyun Kim 2026-02-20 01:13:42 +09:00
parent 6799b1909a
commit 547737f71e
95 changed files with 314 additions and 6552 deletions
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16
CMakeLists.txt
View File

@ -625,6 +625,22 @@ if(BUILD_TESTS)
enable_testing() enable_testing()
find_package(GTest REQUIRED) find_package(GTest REQUIRED)
include(GoogleTest) include(GoogleTest)
# Helper: register a list of Tcl tests for a module.
# Usage:
# sta_module_tests("search" TESTS timing analysis ...)
function(sta_module_tests module_name)
cmake_parse_arguments(ARG "" "" "TESTS" ${ARGN})
foreach(test_name ${ARG_TESTS})
add_test(
NAME tcl.${module_name}.${test_name}
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> ${module_name}_${test_name}
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.${module_name}.${test_name} PROPERTIES LABELS "tcl;module_${module_name}")
endforeach()
endfunction()
add_subdirectory(test) add_subdirectory(test)
# Per-module tests # Per-module tests
add_subdirectory(util/test) add_subdirectory(util/test)

147
dcalc/test/CMakeLists.txt
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@ -1,148 +1 @@
add_test(
NAME tcl.dcalc.report
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> dcalc_report
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.dcalc.report PROPERTIES LABELS "tcl;module_dcalc")
add_test(
NAME tcl.dcalc.engines
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> dcalc_engines
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.dcalc.engines PROPERTIES LABELS "tcl;module_dcalc")
add_test(
NAME tcl.dcalc.corners
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> dcalc_corners
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.dcalc.corners PROPERTIES LABELS "tcl;module_dcalc")
add_test(
NAME tcl.dcalc.spef
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> dcalc_spef
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.dcalc.spef PROPERTIES LABELS "tcl;module_dcalc")
add_test(
NAME tcl.dcalc.advanced
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> dcalc_advanced
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.dcalc.advanced PROPERTIES LABELS "tcl;module_dcalc")
add_test(
NAME tcl.dcalc.prima
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> dcalc_prima
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.dcalc.prima PROPERTIES LABELS "tcl;module_dcalc")
add_test(
NAME tcl.dcalc.ccs_incremental
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> dcalc_ccs_incremental
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.dcalc.ccs_incremental PROPERTIES LABELS "tcl;module_dcalc")
add_test(
NAME tcl.dcalc.ccs_parasitics
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> dcalc_ccs_parasitics
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.dcalc.ccs_parasitics PROPERTIES LABELS "tcl;module_dcalc")
add_test(
NAME tcl.dcalc.graph_delay
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> dcalc_graph_delay
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.dcalc.graph_delay PROPERTIES LABELS "tcl;module_dcalc")
add_test(
NAME tcl.dcalc.dmp_ceff
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> dcalc_dmp_ceff
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.dcalc.dmp_ceff PROPERTIES LABELS "tcl;module_dcalc")
add_test(
NAME tcl.dcalc.arnoldi_prima
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> dcalc_arnoldi_prima
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.dcalc.arnoldi_prima PROPERTIES LABELS "tcl;module_dcalc")
add_test(
NAME tcl.dcalc.annotated_incremental
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> dcalc_annotated_incremental
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.dcalc.annotated_incremental PROPERTIES LABELS "tcl;module_dcalc")
add_test(
NAME tcl.dcalc.dmp_edge_cases
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> dcalc_dmp_edge_cases
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.dcalc.dmp_edge_cases PROPERTIES LABELS "tcl;module_dcalc")
add_test(
NAME tcl.dcalc.incremental_tolerance
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> dcalc_incremental_tolerance
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.dcalc.incremental_tolerance PROPERTIES LABELS "tcl;module_dcalc")
add_test(
NAME tcl.dcalc.multi_engine_spef
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> dcalc_multi_engine_spef
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.dcalc.multi_engine_spef PROPERTIES LABELS "tcl;module_dcalc")
add_test(
NAME tcl.dcalc.annotate_slew
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> dcalc_annotate_slew
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.dcalc.annotate_slew PROPERTIES LABELS "tcl;module_dcalc")
add_test(
NAME tcl.dcalc.arnoldi_spef
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> dcalc_arnoldi_spef
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.dcalc.arnoldi_spef PROPERTIES LABELS "tcl;module_dcalc")
add_test(
NAME tcl.dcalc.dmp_convergence
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> dcalc_dmp_convergence
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.dcalc.dmp_convergence PROPERTIES LABELS "tcl;module_dcalc")
add_test(
NAME tcl.dcalc.prima_arnoldi_deep
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> dcalc_prima_arnoldi_deep
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.dcalc.prima_arnoldi_deep PROPERTIES LABELS "tcl;module_dcalc")
add_test(
NAME tcl.dcalc.dmp_pi_model_deep
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> dcalc_dmp_pi_model_deep
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.dcalc.dmp_pi_model_deep PROPERTIES LABELS "tcl;module_dcalc")
add_test(
NAME tcl.dcalc.gcd_arnoldi_prima
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> dcalc_gcd_arnoldi_prima
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.dcalc.gcd_arnoldi_prima PROPERTIES LABELS "tcl;module_dcalc")
add_subdirectory(cpp) add_subdirectory(cpp)

166
dcalc/test/dcalc_advanced.tcl
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@ -1,166 +0,0 @@
# Test advanced delay calculation scenarios for coverage improvement
# Targets: DmpDelayCalc.cc (dmp_ceff_two_pole paths, DmpCeff error paths)
# ArcDelayCalc.cc (additional arc types)
# GraphDelayCalc.cc (more paths through delay graph computation)
# NetCaps.cc (net capacitance queries)
# UnitDelayCalc.cc (more paths through unit delay calc)
# PrimaDelayCalc.cc (prima delay calculator)
# CcsCeffDelayCalc.cc (ccs_ceff calculator)
read_liberty ../../test/nangate45/Nangate45_typ.lib
read_verilog dcalc_test1.v
link_design dcalc_test1
create_clock -name clk -period 10 [get_ports clk]
set_input_delay -clock clk 0 [get_ports in1]
set_output_delay -clock clk 0 [get_ports out1]
#---------------------------------------------------------------
# Test with various set_load values to exercise NetCaps paths
#---------------------------------------------------------------
puts "--- set_load variations ---"
set_load 0.001 [get_ports out1]
report_checks
set_load 0.1 [get_ports out1]
report_checks
set_load 1.0 [get_ports out1]
report_checks
# Reset load
set_load 0 [get_ports out1]
#---------------------------------------------------------------
# Test set_input_transition with various values
#---------------------------------------------------------------
puts "--- set_input_transition ---"
set_input_transition 0.01 [get_ports in1]
report_checks
set_input_transition 0.5 [get_ports in1]
report_checks
set_input_transition 0.1 [get_ports in1]
#---------------------------------------------------------------
# Test report_dcalc for all arcs in the design
#---------------------------------------------------------------
puts "--- report_dcalc all arcs ---"
# BUF arcs
catch {report_dcalc -from [get_pins buf1/A] -to [get_pins buf1/Z] -max} msg
puts "dcalc buf1 A->Z max: $msg"
catch {report_dcalc -from [get_pins buf1/A] -to [get_pins buf1/Z] -min} msg
puts "dcalc buf1 A->Z min: $msg"
# INV arcs
catch {report_dcalc -from [get_pins inv1/A] -to [get_pins inv1/ZN] -max} msg
puts "dcalc inv1 A->ZN max: $msg"
catch {report_dcalc -from [get_pins inv1/A] -to [get_pins inv1/ZN] -min} msg
puts "dcalc inv1 A->ZN min: $msg"
# DFF clock-to-Q
catch {report_dcalc -from [get_pins reg1/CK] -to [get_pins reg1/Q] -max} msg
puts "dcalc reg1 CK->Q max: $msg"
catch {report_dcalc -from [get_pins reg1/CK] -to [get_pins reg1/Q] -min} msg
puts "dcalc reg1 CK->Q min: $msg"
# DFF setup/hold
catch {report_dcalc -from [get_pins reg1/CK] -to [get_pins reg1/D] -max} msg
puts "dcalc reg1 setup max: $msg"
catch {report_dcalc -from [get_pins reg1/CK] -to [get_pins reg1/D] -min} msg
puts "dcalc reg1 hold min: $msg"
# report_dcalc with digits
catch {report_dcalc -from [get_pins buf1/A] -to [get_pins buf1/Z] -digits 8} msg
puts "dcalc buf1 A->Z 8 digits: $msg"
#---------------------------------------------------------------
# Unit delay calculator
#---------------------------------------------------------------
puts "--- unit delay calculator ---"
set_delay_calculator unit
report_checks -from [get_ports in1] -to [get_ports out1]
report_checks -path_delay min
report_checks -path_delay max
catch {report_dcalc -from [get_pins buf1/A] -to [get_pins buf1/Z]} msg
puts "unit dcalc buf1: $msg"
catch {report_dcalc -from [get_pins inv1/A] -to [get_pins inv1/ZN]} msg
puts "unit dcalc inv1: $msg"
catch {report_dcalc -from [get_pins reg1/CK] -to [get_pins reg1/Q]} msg
puts "unit dcalc reg1 CK->Q: $msg"
catch {report_dcalc -from [get_pins reg1/CK] -to [get_pins reg1/D]} msg
puts "unit dcalc reg1 setup: $msg"
report_checks -fields {slew cap}
#---------------------------------------------------------------
# lumped_cap delay calculator
#---------------------------------------------------------------
puts "--- lumped_cap delay calculator ---"
set_delay_calculator lumped_cap
report_checks -from [get_ports in1] -to [get_ports out1]
catch {report_dcalc -from [get_pins buf1/A] -to [get_pins buf1/Z] -max} msg
puts "lumped_cap dcalc buf1: $msg"
catch {report_dcalc -from [get_pins inv1/A] -to [get_pins inv1/ZN] -max} msg
puts "lumped_cap dcalc inv1: $msg"
catch {report_dcalc -from [get_pins reg1/CK] -to [get_pins reg1/Q] -max} msg
puts "lumped_cap dcalc reg1: $msg"
report_checks -fields {slew cap input_pins}
#---------------------------------------------------------------
# dmp_ceff_elmore (default) delay calculator
#---------------------------------------------------------------
puts "--- dmp_ceff_elmore delay calculator ---"
set_delay_calculator dmp_ceff_elmore
report_checks -from [get_ports in1] -to [get_ports out1]
catch {report_dcalc -from [get_pins buf1/A] -to [get_pins buf1/Z]} msg
puts "dmp_ceff_elmore dcalc buf1: $msg"
#---------------------------------------------------------------
# dmp_ceff_two_pole delay calculator
#---------------------------------------------------------------
puts "--- dmp_ceff_two_pole delay calculator ---"
set_delay_calculator dmp_ceff_two_pole
report_checks -from [get_ports in1] -to [get_ports out1]
report_checks -path_delay min
report_checks -path_delay max
catch {report_dcalc -from [get_pins buf1/A] -to [get_pins buf1/Z] -max} msg
puts "dmp_ceff_two_pole dcalc buf1 max: $msg"
catch {report_dcalc -from [get_pins buf1/A] -to [get_pins buf1/Z] -min} msg
puts "dmp_ceff_two_pole dcalc buf1 min: $msg"
catch {report_dcalc -from [get_pins inv1/A] -to [get_pins inv1/ZN] -max} msg
puts "dmp_ceff_two_pole dcalc inv1: $msg"
catch {report_dcalc -from [get_pins reg1/CK] -to [get_pins reg1/Q] -max} msg
puts "dmp_ceff_two_pole dcalc reg1 CK->Q: $msg"
catch {report_dcalc -from [get_pins reg1/CK] -to [get_pins reg1/D] -max} msg
puts "dmp_ceff_two_pole dcalc reg1 setup: $msg"
report_checks -fields {slew cap input_pins}

199
dcalc/test/dcalc_annotate_slew.tcl
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@ -1,199 +0,0 @@
# Test delay calculation annotation, slew queries, and load capacitance
# calculations with SDF annotation and multiple delay engines.
# Targets:
# GraphDelayCalc.cc: findDelays, loadCap, loadDelay, gateDelay,
# annotateArcDelay, annotateSlew, incrementalDelaysValid,
# setObserver, delayCalcObserver, seedRootSlews,
# findVertexDelay, findCheckEdgeDelays, deleteVertexBefore,
# levelChangedBefore, levelsChangedBefore, delayInvalid (pin/vertex)
# DmpCeff.cc: dmpCeffElmore, dmpCeffTwoPole with annotated values,
# Ceff iteration with various effective capacitance conditions,
# dmpCeffDrvrPi, ceffPiElmore, dmpCeffIter convergence
# Graph.cc: arcDelayAnnotated, wireDelayAnnotated, slew and delay
# getters for all rise/fall combinations
source ../../test/helpers.tcl
read_liberty ../../test/nangate45/Nangate45_typ.lib
read_verilog ../test/dcalc_test1.v
link_design dcalc_test1
create_clock -name clk -period 10 [get_ports clk]
set_input_delay -clock clk 0 [get_ports in1]
set_output_delay -clock clk 0 [get_ports out1]
set_input_transition 0.1 [get_ports {in1 clk}]
#---------------------------------------------------------------
# Baseline timing with default calculator
#---------------------------------------------------------------
puts "--- baseline timing ---"
report_checks
report_checks -path_delay min
report_checks -path_delay max
#---------------------------------------------------------------
# report_dcalc for all arcs: exercises gateDelay, loadDelay paths
#---------------------------------------------------------------
puts "--- report_dcalc all arcs ---"
# BUF arc: rise and fall
report_dcalc -from [get_pins buf1/A] -to [get_pins buf1/Z] -max
puts "buf1 A->Z max: done"
report_dcalc -from [get_pins buf1/A] -to [get_pins buf1/Z] -min
puts "buf1 A->Z min: done"
# INV arc: rise and fall
report_dcalc -from [get_pins inv1/A] -to [get_pins inv1/ZN] -max
puts "inv1 A->ZN max: done"
report_dcalc -from [get_pins inv1/A] -to [get_pins inv1/ZN] -min
puts "inv1 A->ZN min: done"
# DFF CK->Q arc
report_dcalc -from [get_pins reg1/CK] -to [get_pins reg1/Q] -max
puts "reg1 CK->Q max: done"
report_dcalc -from [get_pins reg1/CK] -to [get_pins reg1/Q] -min
puts "reg1 CK->Q min: done"
# DFF setup and hold check arcs
report_dcalc -from [get_pins reg1/CK] -to [get_pins reg1/D] -max
puts "reg1 setup max: done"
report_dcalc -from [get_pins reg1/CK] -to [get_pins reg1/D] -min
puts "reg1 hold min: done"
#---------------------------------------------------------------
# Exercise different delay calculators and check delay values
# Targets: all delay calculator engines, copy/reinit paths
#---------------------------------------------------------------
puts "--- delay calculator engines ---"
# Unit delay calculator
set_delay_calculator unit
report_checks
report_dcalc -from [get_pins buf1/A] -to [get_pins buf1/Z]
puts "unit buf1: done"
# Lumped capacitance calculator
set_delay_calculator lumped_cap
report_checks
report_dcalc -from [get_pins buf1/A] -to [get_pins buf1/Z]
puts "lumped_cap buf1: done"
# DMP Ceff Elmore
set_delay_calculator dmp_ceff_elmore
report_checks
report_dcalc -from [get_pins buf1/A] -to [get_pins buf1/Z]
puts "dmp_elmore buf1: done"
# DMP Ceff Two Pole
set_delay_calculator dmp_ceff_two_pole
report_checks
report_dcalc -from [get_pins buf1/A] -to [get_pins buf1/Z]
puts "dmp_two_pole buf1: done"
# CCS Ceff
set_delay_calculator ccs_ceff
report_checks
# Switch back to default
set_delay_calculator dmp_ceff_elmore
#---------------------------------------------------------------
# Vary load capacitance to stress DmpCeff iteration
# Targets: DmpCeff convergence with different Ceff/Cload ratios
#---------------------------------------------------------------
puts "--- load variation ---"
foreach load_val {0.00001 0.0001 0.001 0.005 0.01 0.05 0.1 0.5 1.0 5.0} {
set_load $load_val [get_ports out1]
report_checks -from [get_ports in1] -to [get_ports out1]
puts "load=$load_val: done"
}
set_load 0 [get_ports out1]
#---------------------------------------------------------------
# Vary input transition to exercise table lookup paths
# Targets: DmpCeff table lookup, findRange, dmpCeffTableLookup
#---------------------------------------------------------------
puts "--- slew variation ---"
foreach slew_val {0.001 0.005 0.01 0.05 0.1 0.2 0.5 1.0 2.0} {
set_input_transition $slew_val [get_ports in1]
report_checks -from [get_ports in1] -to [get_ports out1]
puts "slew=$slew_val: done"
}
set_input_transition 0.1 [get_ports in1]
#---------------------------------------------------------------
# Incremental delay recalculation
# Targets: incrementalDelaysValid, seedInvalidDelays, delayInvalid
#---------------------------------------------------------------
puts "--- incremental delay calc ---"
# Change clock period
create_clock -name clk -period 5 [get_ports clk]
report_checks
# Change input delay
set_input_delay -clock clk 2.0 [get_ports in1]
report_checks
# Change output delay
set_output_delay -clock clk 3.0 [get_ports out1]
report_checks
# Reset and recheck
create_clock -name clk -period 10 [get_ports clk]
set_input_delay -clock clk 0 [get_ports in1]
set_output_delay -clock clk 0 [get_ports out1]
report_checks
#---------------------------------------------------------------
# Report checks with various formatting to exercise reporting paths
#---------------------------------------------------------------
puts "--- report formatting ---"
report_checks -fields {slew cap input_pins nets fanout}
report_checks -format full_clock
report_checks -format full_clock_expanded
report_checks -endpoint_count 3
report_checks -unconstrained
report_checks -sort_by_slack
#---------------------------------------------------------------
# report_check_types exercises check edge delay queries
#---------------------------------------------------------------
puts "--- report_check_types ---"
report_check_types -max_delay -verbose
report_check_types -min_delay -verbose
#---------------------------------------------------------------
# report_slews for all pins: exercises slew getters
# (rise/fall, min/max combinations in Graph.cc)
#---------------------------------------------------------------
puts "--- report_slews ---"
report_slews [get_ports in1]
report_slews [get_ports out1]
report_slews [get_pins buf1/A]
report_slews [get_pins buf1/Z]
report_slews [get_pins inv1/A]
report_slews [get_pins inv1/ZN]
report_slews [get_pins reg1/D]
report_slews [get_pins reg1/CK]
report_slews [get_pins reg1/Q]

189
dcalc/test/dcalc_annotated_incremental.tcl
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@ -1,189 +0,0 @@
# Test annotated delays/slews, incremental delay recalculation,
# delay tolerance, capacitance queries, report_net.
# Targets: GraphDelayCalc.cc findDelays incremental, seedInvalidDelays,
# findCheckEdgeDelays, delayInvalid(pin/vertex),
# setIncrementalDelayTolerance, incrementalDelayTolerance,
# loadDelay, netCaps, findVertexDelay,
# Sta.cc setArcDelay, arcDelay, arcDelayAnnotated,
# setAnnotatedSlew, vertexSlew, connectedCap,
# removeDelaySlewAnnotations, delaysInvalidFrom,
# delaysInvalidFromFanin, findDelays,
# DmpCeff.cc various convergence paths with edge-case loads
read_liberty ../../test/nangate45/Nangate45_typ.lib
read_verilog dcalc_multidriver_test.v
link_design dcalc_multidriver_test
create_clock -name clk -period 10 [get_ports clk]
set_input_delay -clock clk 0 [get_ports {in1 in2 in3 in4 sel}]
set_output_delay -clock clk 0 [get_ports {out1 out2 out3}]
set_input_transition 0.1 [get_ports {in1 in2 in3 in4 sel clk}]
# Baseline
report_checks -path_delay max > /dev/null
############################################################
# Incremental delay tolerance
############################################################
puts "--- setIncrementalDelayTolerance ---"
sta::set_incremental_delay_tolerance 0.01
report_checks -path_delay max
sta::set_incremental_delay_tolerance 0.0
report_checks -path_delay max
sta::set_incremental_delay_tolerance 0.1
report_checks -path_delay max
# Reset
sta::set_incremental_delay_tolerance 0.0
############################################################
# report_net for capacitance queries
############################################################
puts "--- report_net for various nets ---"
report_net n1
report_net n2
report_net n3
report_net n4
report_net n5
report_net n6
report_net n7
report_net n8
############################################################
# report_net with loads
############################################################
puts "--- report_net with loads ---"
set_load 0.05 [get_ports out1]
set_load 0.03 [get_ports out2]
set_load 0.02 [get_ports out3]
report_net n6
report_net n7
report_net n8
############################################################
# report_net with digits
############################################################
puts "--- report_net with digits ---"
report_net -digits 6 n1
report_net -digits 2 n6
############################################################
# Incremental: add wire caps and recompute
############################################################
puts "--- incremental with wire caps ---"
set_load 0.005 [get_nets n1]
report_checks -path_delay max
set_load 0.01 [get_nets n6]
report_checks -path_delay max
############################################################
# Rapid constraint changes for incremental recalculation
############################################################
puts "--- rapid constraint changes ---"
set_load 0.001 [get_ports out1]
report_checks -from [get_ports in1] -to [get_ports out1]
set_load 0.01 [get_ports out1]
report_checks -from [get_ports in1] -to [get_ports out1]
set_load 0.05 [get_ports out1]
report_checks -from [get_ports in1] -to [get_ports out1]
set_load 0.1 [get_ports out1]
report_checks -from [get_ports in1] -to [get_ports out1]
set_load 0.5 [get_ports out1]
report_checks -from [get_ports in1] -to [get_ports out1]
set_load 1.0 [get_ports out1]
report_checks -from [get_ports in1] -to [get_ports out1]
set_load 0 [get_ports out1]
############################################################
# Input transition changes driving incremental
############################################################
puts "--- input transition incremental ---"
foreach slew {0.001 0.005 0.01 0.05 0.1 0.5 1.0 2.0} {
set_input_transition $slew [get_ports in1]
report_checks -from [get_ports in1] -to [get_ports out1]
}
set_input_transition 0.1 [get_ports in1]
############################################################
# Clock period changes
############################################################
puts "--- clock period incremental ---"
create_clock -name clk -period 5 [get_ports clk]
report_checks -path_delay max
create_clock -name clk -period 20 [get_ports clk]
report_checks -path_delay max
create_clock -name clk -period 2 [get_ports clk]
report_checks -path_delay max
create_clock -name clk -period 10 [get_ports clk]
report_checks -path_delay max
############################################################
# Delay calc after adding/removing constraints
############################################################
puts "--- delay calc after constraint changes ---"
set_input_delay -clock clk 2.0 [get_ports in1]
report_checks -from [get_ports in1] -to [get_ports out1]
set_output_delay -clock clk 3.0 [get_ports out1]
report_checks -from [get_ports in1] -to [get_ports out1]
set_input_delay -clock clk 0 [get_ports in1]
set_output_delay -clock clk 0 [get_ports out1]
report_checks -from [get_ports in1] -to [get_ports out1]
############################################################
# Driving cell changes
############################################################
puts "--- driving cell changes ---"
set_driving_cell -lib_cell BUF_X1 [get_ports in1]
report_checks -from [get_ports in1] -to [get_ports out1]
set_driving_cell -lib_cell BUF_X4 [get_ports in1]
report_checks -from [get_ports in1] -to [get_ports out1]
set_driving_cell -lib_cell INV_X1 -pin ZN [get_ports in1]
report_checks -from [get_ports in1] -to [get_ports out1]
############################################################
# read_sdf and annotated delay
############################################################
puts "--- write and read SDF ---"
set sdf_file [file join [pwd] results dcalc_annotated.sdf]
file mkdir results
write_sdf -no_timestamp -no_version $sdf_file
read_sdf $sdf_file
report_checks -path_delay max
report_annotated_delay -list_annotated
report_annotated_check -list_annotated -setup -hold
############################################################
# Remove annotations and recalculate
############################################################
puts "--- remove annotations ---"
sta::remove_delay_slew_annotations
report_checks -path_delay max
############################################################
# Multiple calculator with incremental
############################################################
puts "--- calculator switch incremental ---"
set_delay_calculator dmp_ceff_elmore
set_load 0.05 [get_ports out1]
report_checks -from [get_ports in1] -to [get_ports out1]
set_delay_calculator dmp_ceff_two_pole
report_checks -from [get_ports in1] -to [get_ports out1]
set_delay_calculator lumped_cap
report_checks -from [get_ports in1] -to [get_ports out1]
set_delay_calculator unit
report_checks -from [get_ports in1] -to [get_ports out1]
set_delay_calculator dmp_ceff_elmore
set_load 0 [get_ports out1]

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dcalc/test/dcalc_arnoldi_prima.tcl
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# Test Arnoldi and Prima delay calculators with SPEF parasitics and
# different load/slew conditions for improved coverage.
# Targets: PrimaDelayCalc.cc (prima delay paths, prima reduce RC,
# prima2, prima3, primaResStamp, primaCapStamp, primaPostReduction)
# ArnoldiDelayCalc.cc (arnoldi delay, arnoldi reduce RC,
# arnoldi2, arnoldi3, arnoldiExpand)
# ArnoldiReduce.cc (arnoldi reduce matrix, arnoldi iteration)
# GraphDelayCalc.cc (delay calc with parasitics for multiple calculators)
# DmpCeff.cc (ceff with Pi-model parasitics)
# FindRoot.cc (root finding with parasitic-loaded timing)
# Read ASAP7 libraries
read_liberty ../../test/asap7/asap7sc7p5t_SEQ_RVT_FF_nldm_220123.lib
read_liberty ../../test/asap7/asap7sc7p5t_INVBUF_RVT_FF_nldm_220122.lib.gz
read_liberty ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz
read_liberty ../../test/asap7/asap7sc7p5t_OA_RVT_FF_nldm_211120.lib.gz
read_liberty ../../test/asap7/asap7sc7p5t_AO_RVT_FF_nldm_211120.lib.gz
read_verilog ../../test/reg1_asap7.v
link_design top
create_clock -name clk -period 500 {clk1 clk2 clk3}
set_input_delay -clock clk 1 {in1 in2}
set_output_delay -clock clk 1 [get_ports out]
set_propagated_clock {clk1 clk2 clk3}
# Read SPEF parasitics
puts "--- Reading SPEF ---"
read_spef ../../test/reg1_asap7.spef
#---------------------------------------------------------------
# Prima delay calculator with various input transition values
# Exercises: primaDelay, primaReduceRc, prima2, prima3
#---------------------------------------------------------------
puts "--- prima with varying slews ---"
catch {set_delay_calculator prima} msg
puts "set_delay_calculator prima: $msg"
foreach slew_val {1 5 10 50 100} {
set_input_transition $slew_val {in1 in2 clk1 clk2 clk3}
report_checks
puts "prima slew=$slew_val: done"
}
set_input_transition 10 {in1 in2 clk1 clk2 clk3}
# Prima with various load values
puts "--- prima with varying loads ---"
foreach load_val {0.0001 0.001 0.01 0.1} {
set_load $load_val [get_ports out]
report_checks
puts "prima load=$load_val: done"
}
set_load 0 [get_ports out]
# Prima report_dcalc for all arcs
puts "--- prima report_dcalc all arcs ---"
catch {report_dcalc -from [get_pins u1/A] -to [get_pins u1/Y] -max} msg
puts "prima u1 A->Y max: $msg"
catch {report_dcalc -from [get_pins u1/A] -to [get_pins u1/Y] -min} msg
puts "prima u1 A->Y min: $msg"
catch {report_dcalc -from [get_pins u2/A] -to [get_pins u2/Y] -max} msg
puts "prima u2 A->Y max: $msg"
catch {report_dcalc -from [get_pins u2/A] -to [get_pins u2/Y] -min} msg
puts "prima u2 A->Y min: $msg"
catch {report_dcalc -from [get_pins u2/B] -to [get_pins u2/Y] -max} msg
puts "prima u2 B->Y max: $msg"
catch {report_dcalc -from [get_pins u2/B] -to [get_pins u2/Y] -min} msg
puts "prima u2 B->Y min: $msg"
# DFF arcs with prima
catch {report_dcalc -from [get_pins r1/CLK] -to [get_pins r1/Q] -max} msg
puts "prima r1 CLK->Q max: $msg"
catch {report_dcalc -from [get_pins r1/CLK] -to [get_pins r1/Q] -min} msg
puts "prima r1 CLK->Q min: $msg"
catch {report_dcalc -from [get_pins r2/CLK] -to [get_pins r2/Q] -max} msg
puts "prima r2 CLK->Q max: $msg"
catch {report_dcalc -from [get_pins r3/CLK] -to [get_pins r3/Q] -max} msg
puts "prima r3 CLK->Q max: $msg"
catch {report_dcalc -from [get_pins r3/CLK] -to [get_pins r3/Q] -min} msg
puts "prima r3 CLK->Q min: $msg"
# DFF check arcs with prima
catch {report_dcalc -from [get_pins r1/CLK] -to [get_pins r1/D] -max} msg
puts "prima r1 setup: $msg"
catch {report_dcalc -from [get_pins r1/CLK] -to [get_pins r1/D] -min} msg
puts "prima r1 hold: $msg"
catch {report_dcalc -from [get_pins r3/CLK] -to [get_pins r3/D] -max} msg
puts "prima r3 setup: $msg"
catch {report_dcalc -from [get_pins r3/CLK] -to [get_pins r3/D] -min} msg
puts "prima r3 hold: $msg"
# report_dcalc with digits
catch {report_dcalc -from [get_pins u1/A] -to [get_pins u1/Y] -digits 2} msg
puts "prima u1 2 digits: $msg"
catch {report_dcalc -from [get_pins u1/A] -to [get_pins u1/Y] -digits 8} msg
puts "prima u1 8 digits: $msg"
# Prima with fields
report_checks -fields {slew cap input_pins nets fanout}
report_checks -format full_clock
# Prima specific paths
report_checks -from [get_ports in1] -to [get_ports out]
report_checks -from [get_ports in2] -to [get_ports out]
report_checks -path_delay min
report_checks -path_delay max
#---------------------------------------------------------------
# Arnoldi delay calculator with same variations
# Exercises: arnoldiDelay, arnoldiReduceRc, arnoldiExpand
#---------------------------------------------------------------
puts "--- arnoldi with varying slews ---"
catch {set_delay_calculator arnoldi} msg
puts "set_delay_calculator arnoldi: $msg"
foreach slew_val {1 5 10 50 100} {
set_input_transition $slew_val {in1 in2 clk1 clk2 clk3}
report_checks
puts "arnoldi slew=$slew_val: done"
}
set_input_transition 10 {in1 in2 clk1 clk2 clk3}
# Arnoldi with varying loads
puts "--- arnoldi with varying loads ---"
foreach load_val {0.0001 0.001 0.01 0.1} {
set_load $load_val [get_ports out]
report_checks
puts "arnoldi load=$load_val: done"
}
set_load 0 [get_ports out]
# Arnoldi report_dcalc for all arcs
puts "--- arnoldi report_dcalc ---"
catch {report_dcalc -from [get_pins u1/A] -to [get_pins u1/Y] -max} msg
puts "arnoldi u1 A->Y max: $msg"
catch {report_dcalc -from [get_pins u1/A] -to [get_pins u1/Y] -min} msg
puts "arnoldi u1 A->Y min: $msg"
catch {report_dcalc -from [get_pins u2/A] -to [get_pins u2/Y] -max} msg
puts "arnoldi u2 A->Y max: $msg"
catch {report_dcalc -from [get_pins u2/B] -to [get_pins u2/Y] -max} msg
puts "arnoldi u2 B->Y max: $msg"
catch {report_dcalc -from [get_pins r1/CLK] -to [get_pins r1/Q] -max} msg
puts "arnoldi r1 CLK->Q max: $msg"
catch {report_dcalc -from [get_pins r1/CLK] -to [get_pins r1/Q] -min} msg
puts "arnoldi r1 CLK->Q min: $msg"
catch {report_dcalc -from [get_pins r2/CLK] -to [get_pins r2/Q] -max} msg
puts "arnoldi r2 CLK->Q max: $msg"
catch {report_dcalc -from [get_pins r3/CLK] -to [get_pins r3/Q] -max} msg
puts "arnoldi r3 CLK->Q max: $msg"
catch {report_dcalc -from [get_pins r1/CLK] -to [get_pins r1/D] -max} msg
puts "arnoldi r1 setup: $msg"
catch {report_dcalc -from [get_pins r1/CLK] -to [get_pins r1/D] -min} msg
puts "arnoldi r1 hold: $msg"
catch {report_dcalc -from [get_pins r3/CLK] -to [get_pins r3/D] -max} msg
puts "arnoldi r3 setup: $msg"
catch {report_dcalc -from [get_pins r3/CLK] -to [get_pins r3/D] -min} msg
puts "arnoldi r3 hold: $msg"
# Arnoldi with fields
report_checks -fields {slew cap input_pins nets fanout}
report_checks -format full_clock
#---------------------------------------------------------------
# Switching between parasitic calculators to exercise reinit paths
#---------------------------------------------------------------
puts "--- switching parasitic calculators ---"
set_delay_calculator dmp_ceff_elmore
report_checks
set_delay_calculator dmp_ceff_two_pole
report_checks
set_delay_calculator ccs_ceff
report_checks
set_delay_calculator lumped_cap
report_checks
set_delay_calculator prima
report_checks
set_delay_calculator arnoldi
report_checks
#---------------------------------------------------------------
# Incremental updates with parasitics
# Exercises: seedInvalidDelays with parasitic-loaded nets
#---------------------------------------------------------------
puts "--- incremental with parasitics ---"
set_delay_calculator dmp_ceff_elmore
set_load 0.001 [get_ports out]
report_checks
set_input_transition 50 {in1 in2}
report_checks
create_clock -name clk -period 200 {clk1 clk2 clk3}
report_checks
# Restore
set_load 0 [get_ports out]
set_input_transition 10 {in1 in2 clk1 clk2 clk3}
create_clock -name clk -period 500 {clk1 clk2 clk3}

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dcalc/test/dcalc_arnoldi_spef.tcl
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@ -1,153 +0,0 @@
# Test Arnoldi delay calculator with SPEF parasitics, various slew/load conditions,
# and report_dcalc for different pin combinations.
# Targets:
# ArnoldiDelayCalc.cc: arnoldiDelay, arnoldiReduceRc, arnoldi2, arnoldi3,
# arnoldiExpand, loadDelay, gateDelay, gateSlew
# ArnoldiReduce.cc: arnoldi reduce matrix iteration, arnoldi basis expansion
# GraphDelayCalc.cc: findVertexDelay with arnoldi parasitic reduction
# DmpCeff.cc: ceffPiElmore convergence edge cases with different slews
source ../../test/helpers.tcl
# Read ASAP7 libraries
read_liberty ../../test/asap7/asap7sc7p5t_SEQ_RVT_FF_nldm_220123.lib
read_liberty ../../test/asap7/asap7sc7p5t_INVBUF_RVT_FF_nldm_220122.lib.gz
read_liberty ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz
read_liberty ../../test/asap7/asap7sc7p5t_OA_RVT_FF_nldm_211120.lib.gz
read_liberty ../../test/asap7/asap7sc7p5t_AO_RVT_FF_nldm_211120.lib.gz
read_verilog ../../test/reg1_asap7.v
link_design top
create_clock -name clk -period 500 {clk1 clk2 clk3}
set_input_delay -clock clk 1 {in1 in2}
set_output_delay -clock clk 1 [get_ports out]
set_input_transition 10 {in1 in2 clk1 clk2 clk3}
set_propagated_clock {clk1 clk2 clk3}
#---------------------------------------------------------------
# Test 1: Read SPEF and set arnoldi
#---------------------------------------------------------------
puts "--- Test 1: arnoldi + SPEF ---"
read_spef ../../test/reg1_asap7.spef
set_delay_calculator arnoldi
report_checks
report_checks -path_delay min
report_checks -from [get_ports in1] -to [get_ports out]
report_checks -from [get_ports in2] -to [get_ports out]
report_checks -fields {slew cap input_pins nets fanout}
report_checks -format full_clock
#---------------------------------------------------------------
# Test 2: report_dcalc for all cell arcs
# Exercises: arnoldiDelay for each arc, loadDelay, gateDelay, gateSlew
#---------------------------------------------------------------
puts "--- Test 2: report_dcalc ---"
report_dcalc -from [get_pins u1/A] -to [get_pins u1/Y] -max
puts "dcalc u1 A->Y max: done"
report_dcalc -from [get_pins u1/A] -to [get_pins u1/Y] -min
puts "dcalc u1 A->Y min: done"
report_dcalc -from [get_pins u2/A] -to [get_pins u2/Y] -max
puts "dcalc u2 A->Y: done"
report_dcalc -from [get_pins u2/B] -to [get_pins u2/Y] -max
puts "dcalc u2 B->Y: done"
report_dcalc -from [get_pins u2/B] -to [get_pins u2/Y] -min
puts "dcalc u2 B->Y min: done"
report_dcalc -from [get_pins r1/CLK] -to [get_pins r1/Q] -max
puts "dcalc r1 CLK->Q max: done"
report_dcalc -from [get_pins r1/CLK] -to [get_pins r1/Q] -min
puts "dcalc r1 CLK->Q min: done"
report_dcalc -from [get_pins r2/CLK] -to [get_pins r2/Q] -max
puts "dcalc r2 CLK->Q: done"
report_dcalc -from [get_pins r3/CLK] -to [get_pins r3/Q] -max
puts "dcalc r3 CLK->Q: done"
# Setup/hold check arcs
report_dcalc -from [get_pins r1/CLK] -to [get_pins r1/D] -max
puts "dcalc r1 setup: done"
report_dcalc -from [get_pins r1/CLK] -to [get_pins r1/D] -min
puts "dcalc r1 hold: done"
report_dcalc -from [get_pins r3/CLK] -to [get_pins r3/D] -max
puts "dcalc r3 setup: done"
report_dcalc -from [get_pins r3/CLK] -to [get_pins r3/D] -min
puts "dcalc r3 hold: done"
#---------------------------------------------------------------
# Test 3: Vary input slew with arnoldi
# Exercises: arnoldi gate delay computation at different slew points
#---------------------------------------------------------------
puts "--- Test 3: varying slew ---"
foreach slew_val {0.1 1 5 10 25 50 100 200 500} {
set_input_transition $slew_val {in1 in2 clk1 clk2 clk3}
report_checks
puts "arnoldi slew=$slew_val: done"
}
set_input_transition 10 {in1 in2 clk1 clk2 clk3}
#---------------------------------------------------------------
# Test 4: Vary output load with arnoldi
# Exercises: arnoldi load delay at different capacitance values
#---------------------------------------------------------------
puts "--- Test 4: varying load ---"
foreach load_val {0.00001 0.0001 0.001 0.005 0.01 0.05 0.1} {
set_load $load_val [get_ports out]
report_checks
puts "arnoldi load=$load_val: done"
}
set_load 0 [get_ports out]
#---------------------------------------------------------------
# Test 5: Arnoldi after re-read SPEF
# Exercises: deleteReducedParasitics, re-initialization
#---------------------------------------------------------------
puts "--- Test 5: re-read SPEF ---"
read_spef ../../test/reg1_asap7.spef
report_checks
#---------------------------------------------------------------
# Test 6: Switch engines while arnoldi active
# Exercises: reinit paths in delay calculator switching
#---------------------------------------------------------------
puts "--- Test 6: engine switch from arnoldi ---"
set_delay_calculator dmp_ceff_elmore
report_checks
set_delay_calculator arnoldi
report_checks
set_delay_calculator lumped_cap
report_checks
set_delay_calculator arnoldi
report_checks
#---------------------------------------------------------------
# Test 7: Arnoldi with digits and endpoint count
#---------------------------------------------------------------
puts "--- Test 7: format options ---"
report_checks -digits 6
report_checks -endpoint_count 3
report_checks -group_count 2

134
dcalc/test/dcalc_ccs_incremental.tcl
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@ -1,134 +0,0 @@
# Test CCS effective capacitance delay calculator and incremental updates.
# Targets: CcsCeffDelayCalc.cc (0.0% -> all paths)
# GraphDelayCalc.cc (87.3% -> incremental update, arrival annotation)
# DmpDelayCalc.cc (51.8% -> ccs_ceff falls back to dmp when no CCS data)
# DelayCalcBase.cc (65.3% -> additional base class paths)
# ArcDelayCalc.cc (59.7% -> makeArcDcalcArg error paths)
# DmpCeff.cc (79.1% -> more DmpCeff computation paths)
read_liberty ../../test/nangate45/Nangate45_typ.lib
read_verilog dcalc_test1.v
link_design dcalc_test1
create_clock -name clk -period 10 [get_ports clk]
set_input_delay -clock clk 0 [get_ports in1]
set_output_delay -clock clk 0 [get_ports out1]
set_input_transition 0.1 [get_ports in1]
#---------------------------------------------------------------
# CCS effective capacitance delay calculator
# (Falls back to table-based for NLDM libraries but exercises
# constructor, copy, name, and fallback paths)
#---------------------------------------------------------------
puts "--- ccs_ceff delay calculator ---"
catch {set_delay_calculator ccs_ceff} msg
puts "set_delay_calculator ccs_ceff: $msg"
report_checks
report_checks -path_delay min
report_checks -path_delay max
# report_dcalc with ccs_ceff
catch {report_dcalc -from [get_pins buf1/A] -to [get_pins buf1/Z] -max} msg
puts "ccs_ceff dcalc buf1 max: $msg"
catch {report_dcalc -from [get_pins buf1/A] -to [get_pins buf1/Z] -min} msg
puts "ccs_ceff dcalc buf1 min: $msg"
catch {report_dcalc -from [get_pins inv1/A] -to [get_pins inv1/ZN] -max} msg
puts "ccs_ceff dcalc inv1 max: $msg"
catch {report_dcalc -from [get_pins inv1/A] -to [get_pins inv1/ZN] -min} msg
puts "ccs_ceff dcalc inv1 min: $msg"
catch {report_dcalc -from [get_pins reg1/CK] -to [get_pins reg1/Q] -max} msg
puts "ccs_ceff dcalc reg1 CK->Q max: $msg"
catch {report_dcalc -from [get_pins reg1/CK] -to [get_pins reg1/Q] -min} msg
puts "ccs_ceff dcalc reg1 CK->Q min: $msg"
# Setup/hold check arcs
catch {report_dcalc -from [get_pins reg1/CK] -to [get_pins reg1/D] -max} msg
puts "ccs_ceff dcalc reg1 setup: $msg"
catch {report_dcalc -from [get_pins reg1/CK] -to [get_pins reg1/D] -min} msg
puts "ccs_ceff dcalc reg1 hold: $msg"
# With fields
report_checks -fields {slew cap input_pins}
report_checks -format full_clock
#---------------------------------------------------------------
# Incremental delay update: change constraints and recompute
#---------------------------------------------------------------
puts "--- incremental delay update ---"
# Change load and recompute (exercises GraphDelayCalc incremental update)
set_load 0.01 [get_ports out1]
report_checks
set_load 0.05 [get_ports out1]
report_checks
set_load 0.1 [get_ports out1]
report_checks
# Change input transition and recompute
set_input_transition 0.01 [get_ports in1]
report_checks
set_input_transition 0.5 [get_ports in1]
report_checks
# Change clock period (triggers incremental update)
create_clock -name clk -period 5 [get_ports clk]
report_checks
# Change delays
set_input_delay -clock clk 1.0 [get_ports in1]
report_checks
set_output_delay -clock clk 2.0 [get_ports out1]
report_checks
#---------------------------------------------------------------
# Switch between calculators to exercise copy/init paths
#---------------------------------------------------------------
puts "--- calculator switching ---"
set_delay_calculator dmp_ceff_elmore
report_checks
set_delay_calculator ccs_ceff
report_checks
set_delay_calculator dmp_ceff_two_pole
report_checks
set_delay_calculator lumped_cap
report_checks
set_delay_calculator unit
report_checks
set_delay_calculator ccs_ceff
report_checks
#---------------------------------------------------------------
# report_dcalc with -digits (exercises formatting paths)
#---------------------------------------------------------------
puts "--- report_dcalc with various digits ---"
catch {report_dcalc -from [get_pins buf1/A] -to [get_pins buf1/Z] -digits 2} msg
puts "dcalc 2 digits: $msg"
catch {report_dcalc -from [get_pins buf1/A] -to [get_pins buf1/Z] -digits 4} msg
puts "dcalc 4 digits: $msg"
catch {report_dcalc -from [get_pins buf1/A] -to [get_pins buf1/Z] -digits 8} msg
puts "dcalc 8 digits: $msg"
catch {report_dcalc -from [get_pins buf1/A] -to [get_pins buf1/Z] -digits 12} msg
puts "dcalc 12 digits: $msg"

136
dcalc/test/dcalc_ccs_parasitics.tcl
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# Test CCS/DMP delay calc with SPEF parasitics and multi-corner.
# Targets: CcsCeffDelayCalc.cc (0.0% -> parasitic paths)
# GraphDelayCalc.cc (87.3% -> parasitic-driven delay calc)
# DmpCeff.cc (79.1% -> ceff computation with Pi-model)
# DmpDelayCalc.cc (51.8% -> Pi-model parasitic paths)
# ArcDcalcWaveforms.cc (0.0% -> waveform data access)
# NetCaps.cc (53.3% -> net cap with parasitics)
# DelayCalcBase.cc (65.3% -> parasitic delay base)
# FindRoot.cc (79.5% -> root finding edge cases)
# Read ASAP7 libraries
read_liberty ../../test/asap7/asap7sc7p5t_SEQ_RVT_FF_nldm_220123.lib
read_liberty ../../test/asap7/asap7sc7p5t_INVBUF_RVT_FF_nldm_220122.lib.gz
read_liberty ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz
read_liberty ../../test/asap7/asap7sc7p5t_OA_RVT_FF_nldm_211120.lib.gz
read_liberty ../../test/asap7/asap7sc7p5t_AO_RVT_FF_nldm_211120.lib.gz
read_verilog ../../test/reg1_asap7.v
link_design top
create_clock -name clk -period 500 {clk1 clk2 clk3}
set_input_delay -clock clk 1 {in1 in2}
set_output_delay -clock clk 1 [get_ports out]
set_input_transition 10 {in1 in2 clk1 clk2 clk3}
set_propagated_clock {clk1 clk2 clk3}
# Read SPEF parasitics
puts "--- Reading SPEF ---"
read_spef ../../test/reg1_asap7.spef
#---------------------------------------------------------------
# CCS delay calculator with parasitics
#---------------------------------------------------------------
puts "--- ccs_ceff delay calculator with parasitics ---"
catch {set_delay_calculator ccs_ceff} msg
puts "set_delay_calculator ccs_ceff: $msg"
report_checks
report_checks -path_delay min
report_checks -path_delay max
report_checks -fields {slew cap input_pins} -format full_clock
# report_dcalc exercises arc delay computation through parasitics
catch {report_dcalc -from [get_pins u1/A] -to [get_pins u1/Y]} msg
puts "ccs_ceff dcalc u1 A->Y: $msg"
catch {report_dcalc -from [get_pins u2/A] -to [get_pins u2/Y]} msg
puts "ccs_ceff dcalc u2 A->Y: $msg"
catch {report_dcalc -from [get_pins u2/B] -to [get_pins u2/Y]} msg
puts "ccs_ceff dcalc u2 B->Y: $msg"
catch {report_dcalc -from [get_pins r1/CLK] -to [get_pins r1/Q] -max} msg
puts "ccs_ceff dcalc r1 CLK->Q max: $msg"
catch {report_dcalc -from [get_pins r1/CLK] -to [get_pins r1/Q] -min} msg
puts "ccs_ceff dcalc r1 CLK->Q min: $msg"
# Setup/hold arcs with ccs_ceff
catch {report_dcalc -from [get_pins r3/CLK] -to [get_pins r3/D] -max} msg
puts "ccs_ceff dcalc r3 setup: $msg"
catch {report_dcalc -from [get_pins r3/CLK] -to [get_pins r3/D] -min} msg
puts "ccs_ceff dcalc r3 hold: $msg"
# Additional paths
report_checks -from [get_ports in1] -to [get_ports out]
report_checks -from [get_ports in2] -to [get_ports out]
#---------------------------------------------------------------
# DMP ceff two-pole with parasitics (incremental from ccs_ceff)
#---------------------------------------------------------------
puts "--- dmp_ceff_two_pole with parasitics ---"
set_delay_calculator dmp_ceff_two_pole
report_checks
report_checks -path_delay min
report_checks -path_delay max
catch {report_dcalc -from [get_pins u1/A] -to [get_pins u1/Y] -max} msg
puts "dmp_two_pole dcalc u1: $msg"
catch {report_dcalc -from [get_pins u2/A] -to [get_pins u2/Y] -max} msg
puts "dmp_two_pole dcalc u2: $msg"
catch {report_dcalc -from [get_pins r1/CLK] -to [get_pins r1/Q] -max} msg
puts "dmp_two_pole dcalc r1 CLK->Q: $msg"
report_checks -fields {slew cap input_pins nets}
#---------------------------------------------------------------
# Incremental changes with parasitics
#---------------------------------------------------------------
puts "--- incremental with parasitics ---"
# Change load
set_load 0.001 [get_ports out]
report_checks
# Change input transition
set_input_transition 50 {in1 in2}
report_checks
# Change clock period
create_clock -name clk -period 200 {clk1 clk2 clk3}
report_checks
#---------------------------------------------------------------
# Switch to ccs_ceff after constraint changes (exercises reinit)
#---------------------------------------------------------------
puts "--- ccs_ceff after constraint changes ---"
set_delay_calculator ccs_ceff
report_checks
# Switch rapidly between calculators
set_delay_calculator dmp_ceff_elmore
set_delay_calculator ccs_ceff
set_delay_calculator arnoldi
set_delay_calculator ccs_ceff
report_checks
#---------------------------------------------------------------
# Report checks with different endpoint counts
#---------------------------------------------------------------
puts "--- report_checks with endpoint_count ---"
report_checks -endpoint_count 2
report_checks -group_count 3
report_checks -path_delay min -endpoint_count 3

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dcalc/test/dcalc_corners.tcl
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# Test multi-corner delay calculation
# Exercises: define_corners, corner-specific liberty, report_checks -corner, report_dcalc -corner
define_corners fast slow
read_liberty -corner fast ../../test/nangate45/Nangate45_fast.lib
read_liberty -corner slow ../../test/nangate45/Nangate45_slow.lib
read_verilog dcalc_test1.v
link_design dcalc_test1
create_clock -name clk -period 10 [get_ports clk]
set_input_delay -clock clk 0 [get_ports in1]
set_output_delay -clock clk 0 [get_ports out1]
#---------------------------------------------------------------
# report_checks per corner
#---------------------------------------------------------------
puts "--- Fast corner timing ---"
report_checks -corner fast
report_checks -corner fast -path_delay min
report_checks -corner fast -path_delay max
puts "--- Slow corner timing ---"
report_checks -corner slow
report_checks -corner slow -path_delay min
report_checks -corner slow -path_delay max
#---------------------------------------------------------------
# report_dcalc per corner
#---------------------------------------------------------------
puts "--- report_dcalc per corner ---"
catch {report_dcalc -corner fast -from [get_pins buf1/A] -to [get_pins buf1/Z]} msg
puts $msg
catch {report_dcalc -corner slow -from [get_pins buf1/A] -to [get_pins buf1/Z]} msg
puts $msg
catch {report_dcalc -corner fast -from [get_pins inv1/A] -to [get_pins inv1/ZN]} msg
puts $msg
catch {report_dcalc -corner slow -from [get_pins inv1/A] -to [get_pins inv1/ZN]} msg
puts $msg
# DFF arcs per corner
catch {report_dcalc -corner fast -from [get_pins reg1/CK] -to [get_pins reg1/Q]} msg
puts $msg
catch {report_dcalc -corner slow -from [get_pins reg1/CK] -to [get_pins reg1/Q]} msg
puts $msg
# Setup/hold check arcs per corner
catch {report_dcalc -corner fast -from [get_pins reg1/CK] -to [get_pins reg1/D] -min} msg
puts $msg
catch {report_dcalc -corner slow -from [get_pins reg1/CK] -to [get_pins reg1/D] -max} msg
puts $msg
#---------------------------------------------------------------
# report_checks with -fields for more coverage
#---------------------------------------------------------------
puts "--- report_checks with fields ---"
report_checks -corner fast -fields {slew cap input_pins}
report_checks -corner slow -fields {slew cap input_pins}
#---------------------------------------------------------------
# set_load on output and recheck corners
#---------------------------------------------------------------
puts "--- set_load and recheck corners ---"
set_load 0.1 [get_ports out1]
report_checks -corner fast
report_checks -corner slow

189
dcalc/test/dcalc_dmp_ceff.tcl
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# Test DmpCeff and DmpDelayCalc with various load and slew conditions.
# Targets: DmpCeff.cc (dmpCeffElmore, dmpCeffTwoPole, dmpCeffDrvrPi,
# ceffPiElmore, ceffPiD, dmpCeffIter, dmpCeffStep, dmpCeffD,
# dmpCeffTableLookup, dmpCeffNear, dmpCeffBinaryCcs,
# findRange, addStep, evalDmpGateDelay, evalDmpSlew)
# DmpDelayCalc.cc (makeArcDcalcArg, gateDelay, gateSlew,
# reportDcalc, reportArcDcalcArg, loadDelay, reportLoadDelay,
# gateDelaySlew, delayCalcName, makeCopy)
# PrimaDelayCalc.cc (primaDelay, primaReduceRc, prima2, prima3,
# primaResStamp, primaCapStamp, primaPostReduction)
# ArnoldiDelayCalc.cc (arnoldiDelay, arnoldiReduceRc, arnoldi2, arnoldi3)
# ArnoldiReduce.cc (arnoldiReduce, arnoldiExpand)
# FindRoot.cc (findRoot, secantMethod, newtonMethod, bisectionMethod)
read_liberty ../../test/nangate45/Nangate45_typ.lib
read_verilog dcalc_multidriver_test.v
link_design dcalc_multidriver_test
create_clock -name clk -period 10 [get_ports clk]
set_input_delay -clock clk 0 [get_ports {in1 in2 in3 in4 sel}]
set_output_delay -clock clk 0 [get_ports {out1 out2 out3}]
#---------------------------------------------------------------
# DmpCeff Elmore with various load conditions
# Exercises: dmpCeffElmore iteration with different effective capacitance
#---------------------------------------------------------------
puts "--- dmp_ceff_elmore with varying loads ---"
set_delay_calculator dmp_ceff_elmore
# Very small load
set_load 0.0001 [get_ports out1]
set_input_transition 0.01 [get_ports in1]
report_checks -from [get_ports in1] -to [get_ports out1]
catch {report_dcalc -from [get_pins buf1/A] -to [get_pins buf1/Z] -max} msg
puts "tiny load dcalc: $msg"
# Small load
set_load 0.001 [get_ports out1]
set_input_transition 0.05 [get_ports in1]
report_checks -from [get_ports in1] -to [get_ports out1]
catch {report_dcalc -from [get_pins buf1/A] -to [get_pins buf1/Z] -max} msg
puts "small load dcalc: $msg"
# Medium load
set_load 0.01 [get_ports out1]
set_input_transition 0.1 [get_ports in1]
report_checks -from [get_ports in1] -to [get_ports out1]
catch {report_dcalc -from [get_pins buf1/A] -to [get_pins buf1/Z] -max} msg
puts "medium load dcalc: $msg"
# Large load
set_load 0.1 [get_ports out1]
set_input_transition 0.5 [get_ports in1]
report_checks -from [get_ports in1] -to [get_ports out1]
catch {report_dcalc -from [get_pins buf1/A] -to [get_pins buf1/Z] -max} msg
puts "large load dcalc: $msg"
# Very large load (stress dmp iteration convergence)
set_load 1.0 [get_ports out1]
set_input_transition 1.0 [get_ports in1]
report_checks -from [get_ports in1] -to [get_ports out1]
catch {report_dcalc -from [get_pins buf1/A] -to [get_pins buf1/Z] -max} msg
puts "very large load dcalc: $msg"
# Reset
set_load 0 [get_ports out1]
set_input_transition 0.1 [get_ports in1]
#---------------------------------------------------------------
# DmpCeff TwoPole with same load variations
# Exercises: dmpCeffTwoPole path, different convergence behavior
#---------------------------------------------------------------
puts "--- dmp_ceff_two_pole with varying loads ---"
set_delay_calculator dmp_ceff_two_pole
# Vary load and transition on multiple outputs
foreach out_port {out1 out2 out3} {
foreach load_val {0.001 0.01 0.05 0.1} {
set_load $load_val [get_ports $out_port]
report_checks -to [get_ports $out_port]
puts "dmp_two_pole $out_port load=$load_val: done"
}
set_load 0 [get_ports $out_port]
}
# report_dcalc for all gate types with dmp_two_pole
catch {report_dcalc -from [get_pins buf1/A] -to [get_pins buf1/Z] -max} msg
puts "dmp_two_pole buf1: $msg"
catch {report_dcalc -from [get_pins inv1/A] -to [get_pins inv1/ZN] -max} msg
puts "dmp_two_pole inv1: $msg"
catch {report_dcalc -from [get_pins and1/A1] -to [get_pins and1/ZN] -max} msg
puts "dmp_two_pole and1 A1: $msg"
catch {report_dcalc -from [get_pins or1/A1] -to [get_pins or1/ZN] -max} msg
puts "dmp_two_pole or1 A1: $msg"
catch {report_dcalc -from [get_pins nand1/A1] -to [get_pins nand1/ZN] -max} msg
puts "dmp_two_pole nand1 A1: $msg"
catch {report_dcalc -from [get_pins nor1/A1] -to [get_pins nor1/ZN] -max} msg
puts "dmp_two_pole nor1 A1: $msg"
catch {report_dcalc -from [get_pins reg1/CK] -to [get_pins reg1/Q] -max} msg
puts "dmp_two_pole reg1 CK->Q: $msg"
catch {report_dcalc -from [get_pins reg1/CK] -to [get_pins reg1/D] -max} msg
puts "dmp_two_pole reg1 setup: $msg"
catch {report_dcalc -from [get_pins reg1/CK] -to [get_pins reg1/D] -min} msg
puts "dmp_two_pole reg1 hold: $msg"
#---------------------------------------------------------------
# Multiple input transition values to exercise different table lookups
# Exercises: dmpCeffTableLookup, findRange
#---------------------------------------------------------------
puts "--- varying input transitions ---"
set_delay_calculator dmp_ceff_elmore
foreach slew_val {0.001 0.01 0.05 0.1 0.2 0.5 1.0} {
set_input_transition $slew_val [get_ports {in1 in2 in3 in4 sel}]
report_checks -from [get_ports in1] -to [get_ports out1]
puts "slew=$slew_val: done"
}
set_input_transition 0.1 [get_ports {in1 in2 in3 in4 sel}]
#---------------------------------------------------------------
# CCS effective capacitance calculator on large design
# Exercises: CcsCeffDelayCalc paths
#---------------------------------------------------------------
puts "--- ccs_ceff on larger design ---"
catch {set_delay_calculator ccs_ceff} msg
puts "set_delay_calculator ccs_ceff: $msg"
report_checks
# Various loads with ccs_ceff
foreach load_val {0.001 0.01 0.1} {
set_load $load_val [get_ports out1]
report_checks -from [get_ports in1] -to [get_ports out1]
puts "ccs_ceff load=$load_val: done"
}
set_load 0 [get_ports out1]
# report_dcalc with ccs_ceff
catch {report_dcalc -from [get_pins nand1/A1] -to [get_pins nand1/ZN] -max} msg
puts "ccs_ceff nand1 A1: $msg"
catch {report_dcalc -from [get_pins nor1/A1] -to [get_pins nor1/ZN] -max} msg
puts "ccs_ceff nor1 A1: $msg"
catch {report_dcalc -from [get_pins buf2/A] -to [get_pins buf2/Z] -max} msg
puts "ccs_ceff buf2 A->Z: $msg"
catch {report_dcalc -from [get_pins buf3/A] -to [get_pins buf3/Z] -max} msg
puts "ccs_ceff buf3 A->Z: $msg"
#---------------------------------------------------------------
# Rapid calculator switching to exercise copy/reinit paths
#---------------------------------------------------------------
puts "--- rapid calculator switching ---"
set_delay_calculator unit
report_checks -from [get_ports in1] -to [get_ports out3]
set_delay_calculator lumped_cap
report_checks -from [get_ports in1] -to [get_ports out3]
set_delay_calculator dmp_ceff_elmore
report_checks -from [get_ports in1] -to [get_ports out3]
set_delay_calculator dmp_ceff_two_pole
report_checks -from [get_ports in1] -to [get_ports out3]
set_delay_calculator ccs_ceff
report_checks -from [get_ports in1] -to [get_ports out3]
set_delay_calculator dmp_ceff_elmore
report_checks -from [get_ports in1] -to [get_ports out3]
#---------------------------------------------------------------
# report_checks with various reporting formats
#---------------------------------------------------------------
puts "--- report_checks formatting ---"
report_checks -fields {slew cap input_pins nets fanout}
report_checks -format full_clock
report_checks -format full_clock_expanded

182
dcalc/test/dcalc_dmp_convergence.tcl
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# Test DMP effective capacitance convergence edge cases with extreme
# slew/load conditions and manual pi model parasitics.
# Targets:
# DmpCeff.cc: dmpCeffIter convergence paths, ceffPiElmore edge cases,
# ceffPiPoleResidue, iteration count boundaries,
# very small/large slew handling, zero capacitance paths
# GraphDelayCalc.cc: findVertexDelay with manual parasitics
# ArnoldiDelayCalc.cc: arnoldi with manual pi model
source ../../test/helpers.tcl
# Read ASAP7 libraries
read_liberty ../../test/asap7/asap7sc7p5t_SEQ_RVT_FF_nldm_220123.lib
read_liberty ../../test/asap7/asap7sc7p5t_INVBUF_RVT_FF_nldm_220122.lib.gz
read_liberty ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz
read_liberty ../../test/asap7/asap7sc7p5t_OA_RVT_FF_nldm_211120.lib.gz
read_liberty ../../test/asap7/asap7sc7p5t_AO_RVT_FF_nldm_211120.lib.gz
read_verilog ../../test/reg1_asap7.v
link_design top
create_clock -name clk -period 500 {clk1 clk2 clk3}
set_input_delay -clock clk 1 {in1 in2}
set_output_delay -clock clk 1 [get_ports out]
set_input_transition 10 {in1 in2 clk1 clk2 clk3}
set_propagated_clock {clk1 clk2 clk3}
#---------------------------------------------------------------
# Test 1: Manual pi model + dmp_ceff_elmore
# Exercises: dmpCeffIter with manually set pi model
#---------------------------------------------------------------
puts "--- Test 1: manual pi + dmp_ceff_elmore ---"
set_delay_calculator dmp_ceff_elmore
# Set pi models on all driver pins
sta::set_pi_model u1/Y 0.005 10.0 0.003
sta::set_elmore u1/Y u2/B 0.005
sta::set_pi_model u2/Y 0.008 15.0 0.005
sta::set_elmore u2/Y r3/D 0.008
sta::set_pi_model r1/Q 0.002 5.0 0.001
sta::set_elmore r1/Q u2/A 0.003
sta::set_pi_model r2/Q 0.003 6.0 0.002
sta::set_elmore r2/Q u1/A 0.004
sta::set_pi_model r3/Q 0.001 2.0 0.001
sta::set_elmore r3/Q out 0.002
report_checks
report_checks -path_delay min
#---------------------------------------------------------------
# Test 2: dmp_ceff_two_pole with manual pi
# Exercises: ceffPiPoleResidue, two-pole iteration
#---------------------------------------------------------------
puts "--- Test 2: dmp_ceff_two_pole ---"
set_delay_calculator dmp_ceff_two_pole
report_checks
report_checks -from [get_ports in1] -to [get_ports out]
report_checks -from [get_ports in2] -to [get_ports out]
#---------------------------------------------------------------
# Test 3: Extreme slew values with DMP
# Exercises: dmpCeffIter convergence boundaries
#---------------------------------------------------------------
puts "--- Test 3: extreme slew ---"
set_delay_calculator dmp_ceff_elmore
# Very small slew
set_input_transition 0.01 {in1 in2 clk1 clk2 clk3}
report_checks
# Small slew
set_input_transition 0.1 {in1 in2 clk1 clk2 clk3}
report_checks
# Medium slew
set_input_transition 50 {in1 in2 clk1 clk2 clk3}
report_checks
# Large slew
set_input_transition 500 {in1 in2 clk1 clk2 clk3}
report_checks
# Very large slew
set_input_transition 2000 {in1 in2 clk1 clk2 clk3}
report_checks
set_input_transition 10 {in1 in2 clk1 clk2 clk3}
#---------------------------------------------------------------
# Test 4: Very small pi model values (near-zero)
# Exercises: DMP edge case with tiny parasitics
#---------------------------------------------------------------
puts "--- Test 4: tiny pi model ---"
sta::set_pi_model u1/Y 0.00001 0.1 0.00001
sta::set_elmore u1/Y u2/B 0.00001
report_checks
#---------------------------------------------------------------
# Test 5: Large pi model values
# Exercises: DMP with heavy parasitic loading
#---------------------------------------------------------------
puts "--- Test 5: large pi model ---"
sta::set_pi_model u1/Y 0.1 100.0 0.05
sta::set_elmore u1/Y u2/B 0.5
sta::set_pi_model u2/Y 0.15 150.0 0.08
sta::set_elmore u2/Y r3/D 0.8
report_checks
#---------------------------------------------------------------
# Test 6: report_dcalc with dmp calculators
# Exercises: DMP ceff iteration for specific arcs
#---------------------------------------------------------------
puts "--- Test 6: report_dcalc ---"
set_delay_calculator dmp_ceff_elmore
report_dcalc -from [get_pins u1/A] -to [get_pins u1/Y] -max -digits 6
puts "dmp_elmore u1: done"
report_dcalc -from [get_pins u2/A] -to [get_pins u2/Y] -max -digits 4
puts "dmp_elmore u2 A: done"
report_dcalc -from [get_pins u2/B] -to [get_pins u2/Y] -max
puts "dmp_elmore u2 B: done"
report_dcalc -from [get_pins r1/CLK] -to [get_pins r1/Q] -max
puts "dmp_elmore r1: done"
report_dcalc -from [get_pins r3/CLK] -to [get_pins r3/Q] -min
puts "dmp_elmore r3 min: done"
set_delay_calculator dmp_ceff_two_pole
report_dcalc -from [get_pins u1/A] -to [get_pins u1/Y] -max -digits 6
puts "dmp_two_pole u1: done"
report_dcalc -from [get_pins u2/A] -to [get_pins u2/Y] -max
puts "dmp_two_pole u2: done"
report_dcalc -from [get_pins r2/CLK] -to [get_pins r2/Q] -max
puts "dmp_two_pole r2: done"
#---------------------------------------------------------------
# Test 7: SPEF overriding manual, then DMP
# Exercises: deleteReducedParasitics from manual->SPEF transition
#---------------------------------------------------------------
puts "--- Test 7: SPEF override manual ---"
set_delay_calculator dmp_ceff_elmore
read_spef ../../test/reg1_asap7.spef
report_checks
set_delay_calculator dmp_ceff_two_pole
report_checks
#---------------------------------------------------------------
# Test 8: Load variation with DMP
# Exercises: loadPinCapacitanceChanged -> deleteReducedParasitics
#---------------------------------------------------------------
puts "--- Test 8: load variation ---"
set_delay_calculator dmp_ceff_elmore
foreach load_val {0.0001 0.001 0.01 0.05 0.1} {
set_load $load_val [get_ports out]
report_checks
puts "dmp load=$load_val: done"
}
set_load 0 [get_ports out]
#---------------------------------------------------------------
# Test 9: find_delays and invalidation
#---------------------------------------------------------------
puts "--- Test 9: find_delays ---"
sta::find_delays
sta::delays_invalid
sta::find_delays

212
dcalc/test/dcalc_dmp_edge_cases.tcl
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# Test DmpCeff edge cases: extreme loads, extreme slews, overflow handling,
# different convergence paths for dmpCeffElmore/TwoPole,
# report_dcalc with digits, unit delay calculator baseline.
# Targets: DmpCeff.cc dmpCeffElmore convergence edge cases,
# dmpCeffTwoPole convergence edge cases,
# dmpCeffDrvrPi, ceffPiElmore, ceffPiD,
# dmpCeffIter, dmpCeffStep, dmpCeffD,
# overflow handling paths, findRange edge cases,
# DmpDelayCalc.cc gateDelay/gateSlew with edge case inputs,
# GraphDelayCalc.cc findVertexDelay, findCheckEdgeDelays,
# report_dcalc, netCaps, loadDelay
read_liberty ../../test/nangate45/Nangate45_typ.lib
read_verilog dcalc_test1.v
link_design dcalc_test1
create_clock -name clk -period 10 [get_ports clk]
set_input_delay -clock clk 0 [get_ports in1]
set_output_delay -clock clk 0 [get_ports out1]
############################################################
# DmpCeff Elmore: extreme load conditions
############################################################
puts "--- dmp_ceff_elmore extreme loads ---"
set_delay_calculator dmp_ceff_elmore
# Zero load
set_load 0 [get_ports out1]
set_input_transition 0.1 [get_ports in1]
report_checks -from [get_ports in1] -to [get_ports out1]
catch {report_dcalc -from [get_pins buf1/A] -to [get_pins buf1/Z] -max} msg
puts "elmore zero load: $msg"
# Tiny load
set_load 0.00001 [get_ports out1]
report_checks -from [get_ports in1] -to [get_ports out1]
catch {report_dcalc -from [get_pins buf1/A] -to [get_pins buf1/Z] -max} msg
puts "elmore tiny load: $msg"
# Very large load (potential overflow path)
set_load 5.0 [get_ports out1]
set_input_transition 0.1 [get_ports in1]
report_checks -from [get_ports in1] -to [get_ports out1]
catch {report_dcalc -from [get_pins buf1/A] -to [get_pins buf1/Z] -max} msg
puts "elmore large load: $msg"
# Huge load
set_load 10.0 [get_ports out1]
report_checks -from [get_ports in1] -to [get_ports out1]
catch {report_dcalc -from [get_pins buf1/A] -to [get_pins buf1/Z] -max} msg
puts "elmore huge load: $msg"
set_load 0 [get_ports out1]
############################################################
# DmpCeff Elmore: extreme input transitions
############################################################
puts "--- dmp_ceff_elmore extreme transitions ---"
# Very fast transition
set_input_transition 0.0001 [get_ports in1]
report_checks -from [get_ports in1] -to [get_ports out1]
catch {report_dcalc -from [get_pins buf1/A] -to [get_pins buf1/Z] -max} msg
puts "elmore fast transition: $msg"
# Very slow transition
set_input_transition 5.0 [get_ports in1]
report_checks -from [get_ports in1] -to [get_ports out1]
catch {report_dcalc -from [get_pins buf1/A] -to [get_pins buf1/Z] -max} msg
puts "elmore slow transition: $msg"
# Extreme slow
set_input_transition 10.0 [get_ports in1]
report_checks -from [get_ports in1] -to [get_ports out1]
catch {report_dcalc -from [get_pins buf1/A] -to [get_pins buf1/Z] -max} msg
puts "elmore extreme slow: $msg"
set_input_transition 0.1 [get_ports in1]
############################################################
# DmpCeff Elmore: combined extreme load + transition
############################################################
puts "--- dmp_ceff_elmore combined extremes ---"
set_load 5.0 [get_ports out1]
set_input_transition 0.001 [get_ports in1]
report_checks -from [get_ports in1] -to [get_ports out1]
set_load 0.0001 [get_ports out1]
set_input_transition 5.0 [get_ports in1]
report_checks -from [get_ports in1] -to [get_ports out1]
set_load 5.0 [get_ports out1]
set_input_transition 5.0 [get_ports in1]
report_checks -from [get_ports in1] -to [get_ports out1]
set_load 0 [get_ports out1]
set_input_transition 0.1 [get_ports in1]
############################################################
# DmpCeff TwoPole: same extreme tests
############################################################
puts "--- dmp_ceff_two_pole extreme loads ---"
set_delay_calculator dmp_ceff_two_pole
set_load 0 [get_ports out1]
report_checks -from [get_ports in1] -to [get_ports out1]
set_load 0.00001 [get_ports out1]
report_checks -from [get_ports in1] -to [get_ports out1]
set_load 5.0 [get_ports out1]
report_checks -from [get_ports in1] -to [get_ports out1]
set_load 10.0 [get_ports out1]
report_checks -from [get_ports in1] -to [get_ports out1]
set_load 0 [get_ports out1]
puts "--- dmp_ceff_two_pole extreme transitions ---"
set_input_transition 0.0001 [get_ports in1]
report_checks -from [get_ports in1] -to [get_ports out1]
set_input_transition 5.0 [get_ports in1]
report_checks -from [get_ports in1] -to [get_ports out1]
set_input_transition 0.1 [get_ports in1]
############################################################
# report_dcalc for all arc types in design
############################################################
puts "--- report_dcalc all arcs ---"
set_delay_calculator dmp_ceff_elmore
set_load 0.01 [get_ports out1]
# BUF arcs (both rise and fall)
catch {report_dcalc -from [get_pins buf1/A] -to [get_pins buf1/Z] -max} msg
puts "dcalc buf1 max: $msg"
catch {report_dcalc -from [get_pins buf1/A] -to [get_pins buf1/Z] -min} msg
puts "dcalc buf1 min: $msg"
# INV arcs
catch {report_dcalc -from [get_pins inv1/A] -to [get_pins inv1/ZN] -max} msg
puts "dcalc inv1 max: $msg"
catch {report_dcalc -from [get_pins inv1/A] -to [get_pins inv1/ZN] -min} msg
puts "dcalc inv1 min: $msg"
# DFF CK->Q arcs
catch {report_dcalc -from [get_pins reg1/CK] -to [get_pins reg1/Q] -max} msg
puts "dcalc reg1 CK->Q max: $msg"
catch {report_dcalc -from [get_pins reg1/CK] -to [get_pins reg1/Q] -min} msg
puts "dcalc reg1 CK->Q min: $msg"
# DFF check arcs (setup/hold)
catch {report_dcalc -from [get_pins reg1/CK] -to [get_pins reg1/D] -max} msg
puts "dcalc reg1 setup: $msg"
catch {report_dcalc -from [get_pins reg1/CK] -to [get_pins reg1/D] -min} msg
puts "dcalc reg1 hold: $msg"
############################################################
# report_dcalc with various digit counts
############################################################
puts "--- report_dcalc digits ---"
catch {report_dcalc -from [get_pins buf1/A] -to [get_pins buf1/Z] -digits 1} msg
puts "1 digit: $msg"
catch {report_dcalc -from [get_pins buf1/A] -to [get_pins buf1/Z] -digits 3} msg
puts "3 digits: $msg"
catch {report_dcalc -from [get_pins buf1/A] -to [get_pins buf1/Z] -digits 6} msg
puts "6 digits: $msg"
catch {report_dcalc -from [get_pins buf1/A] -to [get_pins buf1/Z] -digits 10} msg
puts "10 digits: $msg"
############################################################
# Sweep load/slew matrix for convergence coverage
############################################################
puts "--- load/slew sweep ---"
foreach calc {dmp_ceff_elmore dmp_ceff_two_pole} {
set_delay_calculator $calc
foreach load {0.001 0.005 0.01 0.05 0.1 0.5 1.0 2.0} {
foreach slew {0.01 0.05 0.1 0.5 1.0} {
set_load $load [get_ports out1]
set_input_transition $slew [get_ports in1]
report_checks -from [get_ports in1] -to [get_ports out1] > /dev/null
}
}
}
set_load 0 [get_ports out1]
set_input_transition 0.1 [get_ports in1]
############################################################
# Unit delay calculator
############################################################
puts "--- unit calculator ---"
set_delay_calculator unit
report_checks -from [get_ports in1] -to [get_ports out1]
catch {report_dcalc -from [get_pins buf1/A] -to [get_pins buf1/Z] -max} msg
puts "unit dcalc buf1: $msg"
############################################################
# Lumped cap calculator
############################################################
puts "--- lumped_cap calculator ---"
set_delay_calculator lumped_cap
set_load 0.01 [get_ports out1]
report_checks -from [get_ports in1] -to [get_ports out1]
catch {report_dcalc -from [get_pins buf1/A] -to [get_pins buf1/Z] -max} msg
puts "lumped_cap dcalc buf1: $msg"
set_load 0 [get_ports out1]
# Restore default
set_delay_calculator dmp_ceff_elmore

204
dcalc/test/dcalc_dmp_pi_model_deep.tcl
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# Deep DMP effective capacitance testing with pi model parasitics,
# various cell types, extreme conditions, and incremental updates.
# Targets:
# DmpCeff.cc: dmpCeffIter convergence, ceffPiElmore boundary cases,
# ceffPiPoleResidue, iteration count limits, very small/large caps,
# loadDelay, gateDelay with pi model
# GraphDelayCalc.cc: findVertexDelay with manual parasitics,
# seedInvalidDelays, delayCalcIncrementalCond
# ArnoldiDelayCalc.cc: arnoldi with pi model parasitics
# FindRoot.cc: root finding edge cases
source ../../test/helpers.tcl
############################################################
# Read Nangate45 and setup search_test1 design
############################################################
read_liberty ../../test/nangate45/Nangate45_typ.lib
read_verilog ../../search/test/search_test1.v
link_design search_test1
create_clock -name clk -period 10 [get_ports clk]
set_input_delay -clock clk 1.0 [get_ports {in1 in2}]
set_output_delay -clock clk 2.0 [get_ports out1]
set_input_transition 0.1 [all_inputs]
############################################################
# Test 1: Manual pi model with dmp_ceff_elmore on all outputs
############################################################
puts "--- Test 1: pi models on all driver pins ---"
set_delay_calculator dmp_ceff_elmore
# Set pi models on representative driver pins
set all_cells [get_cells *]
foreach cell_obj $all_cells {
set cname [get_name $cell_obj]
set ref [get_property $cell_obj ref_name]
# Try to set pi model on output pins
set pins [get_pins $cname/*]
foreach pin $pins {
catch {
set dir [get_property $pin direction]
if {$dir == "output"} {
catch {sta::set_pi_model [get_name $pin] 0.003 8.0 0.002}
}
}
}
}
report_checks
report_checks -path_delay min
report_checks -path_delay max
############################################################
# Test 2: Extreme pi model values (very small)
############################################################
puts "--- Test 2: tiny pi model ---"
foreach cell_obj [lrange $all_cells 0 4] {
set cname [get_name $cell_obj]
set pins [get_pins $cname/*]
foreach pin $pins {
catch {
set dir [get_property $pin direction]
if {$dir == "output"} {
catch {sta::set_pi_model [get_name $pin] 0.00001 0.01 0.000005}
}
}
}
}
report_checks
############################################################
# Test 3: Large pi model values
############################################################
puts "--- Test 3: large pi model ---"
foreach cell_obj [lrange $all_cells 0 4] {
set cname [get_name $cell_obj]
set pins [get_pins $cname/*]
foreach pin $pins {
catch {
set dir [get_property $pin direction]
if {$dir == "output"} {
catch {sta::set_pi_model [get_name $pin] 0.1 200.0 0.05}
}
}
}
}
report_checks
############################################################
# Test 4: dmp_ceff_two_pole with manual pi models
############################################################
puts "--- Test 4: dmp_ceff_two_pole ---"
set_delay_calculator dmp_ceff_two_pole
report_checks
report_checks -path_delay min
# Vary slew
foreach slew_val {0.01 0.1 0.5 1.0 5.0} {
set_input_transition $slew_val [all_inputs]
report_checks
puts "two_pole slew=$slew_val: done"
}
set_input_transition 0.1 [all_inputs]
############################################################
# Test 5: SPEF then manual pi model override
############################################################
puts "--- Test 5: SPEF then pi override ---"
set_delay_calculator dmp_ceff_elmore
read_spef ../../search/test/search_test1.spef
report_checks
# Override with manual pi models
foreach cell_obj [lrange $all_cells 0 2] {
set cname [get_name $cell_obj]
set pins [get_pins $cname/*]
foreach pin $pins {
catch {
set dir [get_property $pin direction]
if {$dir == "output"} {
catch {sta::set_pi_model [get_name $pin] 0.005 10.0 0.003}
}
}
}
}
report_checks
############################################################
# Test 6: report_dcalc with dmp calculators and pi models
############################################################
puts "--- Test 6: report_dcalc ---"
set_delay_calculator dmp_ceff_elmore
foreach cell_obj [lrange $all_cells 0 5] {
set cname [get_name $cell_obj]
set pins [get_pins $cname/*]
if {[llength $pins] >= 2} {
set in_pin [lindex $pins 0]
set out_pin [lindex $pins end]
catch {report_dcalc -from $in_pin -to $out_pin -max}
catch {report_dcalc -from $in_pin -to $out_pin -min}
}
}
set_delay_calculator dmp_ceff_two_pole
foreach cell_obj [lrange $all_cells 0 5] {
set cname [get_name $cell_obj]
set pins [get_pins $cname/*]
if {[llength $pins] >= 2} {
set in_pin [lindex $pins 0]
set out_pin [lindex $pins end]
catch {report_dcalc -from $in_pin -to $out_pin -max -digits 6}
}
}
############################################################
# Test 7: Incremental updates with pi models
############################################################
puts "--- Test 7: incremental ---"
set_delay_calculator dmp_ceff_elmore
# Load change triggers incremental
set_load 0.001 [get_ports out1]
report_checks
set_load 0.005 [get_ports out1]
report_checks
# Slew change triggers incremental
set_input_transition 0.5 [all_inputs]
report_checks
set_input_transition 2.0 [all_inputs]
report_checks
# Clock change triggers incremental
create_clock -name clk -period 5 [get_ports clk]
report_checks
create_clock -name clk -period 2 [get_ports clk]
report_checks
############################################################
# Test 8: find_delays and invalidation
############################################################
puts "--- Test 8: find_delays ---"
sta::find_delays
sta::delays_invalid
sta::find_delays
# Multiple invalidation cycles
for {set i 0} {$i < 3} {incr i} {
sta::delays_invalid
sta::find_delays
}

103
dcalc/test/dcalc_engines.tcl
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# Test different delay calculator engines
# Exercises: set_delay_calculator, report_dcalc, set_load, set_input_transition
read_liberty ../../test/nangate45/Nangate45_typ.lib
read_verilog dcalc_test1.v
link_design dcalc_test1
create_clock -name clk -period 10 [get_ports clk]
set_input_delay -clock clk 0 [get_ports in1]
set_output_delay -clock clk 0 [get_ports out1]
#---------------------------------------------------------------
# Unit delay calculator
#---------------------------------------------------------------
puts "--- Testing unit delay calculator ---"
catch {set_delay_calculator unit} msg
puts $msg
report_checks -from [get_ports in1] -to [get_ports out1]
report_checks -path_delay min
report_checks -path_delay max
#---------------------------------------------------------------
# Lumped cap delay calculator
#---------------------------------------------------------------
puts "--- Testing lumped_cap delay calculator ---"
catch {set_delay_calculator lumped_cap} msg
puts $msg
report_checks -from [get_ports in1] -to [get_ports out1]
report_checks -path_delay min
report_checks -path_delay max
#---------------------------------------------------------------
# report_dcalc with various options
#---------------------------------------------------------------
puts "--- Testing report_dcalc ---"
# report_dcalc from/to
catch {report_dcalc -from [get_pins buf1/A] -to [get_pins buf1/Z]} msg
puts $msg
# report_dcalc -min
catch {report_dcalc -from [get_pins buf1/A] -to [get_pins buf1/Z] -min} msg
puts $msg
# report_dcalc -max
catch {report_dcalc -from [get_pins buf1/A] -to [get_pins buf1/Z] -max} msg
puts $msg
# report_dcalc with -digits
catch {report_dcalc -from [get_pins inv1/A] -to [get_pins inv1/ZN] -digits 6} msg
puts $msg
# report_dcalc from only
catch {report_dcalc -from [get_pins buf1/A]} msg
puts $msg
# report_dcalc to only
catch {report_dcalc -to [get_pins inv1/ZN]} msg
puts $msg
# report_dcalc for DFF setup/hold arcs
catch {report_dcalc -from [get_pins reg1/CK] -to [get_pins reg1/D]} msg
puts $msg
# report_dcalc for DFF clock->Q arc
catch {report_dcalc -from [get_pins reg1/CK] -to [get_pins reg1/Q]} msg
puts $msg
#---------------------------------------------------------------
# set_load on output ports and recompute
#---------------------------------------------------------------
puts "--- Testing set_load ---"
set_load 0.05 [get_ports out1]
# Switch back to dmp_ceff_elmore (default) for load testing
catch {set_delay_calculator dmp_ceff_elmore} msg
puts $msg
report_checks -from [get_ports in1] -to [get_ports out1]
report_dcalc -from [get_pins reg1/CK] -to [get_pins reg1/Q] -max
#---------------------------------------------------------------
# set_input_transition on inputs and recompute
#---------------------------------------------------------------
puts "--- Testing set_input_transition ---"
set_input_transition 0.2 [get_ports in1]
report_checks -from [get_ports in1] -to [get_ports out1]
report_dcalc -from [get_pins buf1/A] -to [get_pins buf1/Z] -max
#---------------------------------------------------------------
# Test dmp_ceff_two_pole calculator
#---------------------------------------------------------------
puts "--- Testing dmp_ceff_two_pole delay calculator ---"
catch {set_delay_calculator dmp_ceff_two_pole} msg
puts $msg
report_checks -from [get_ports in1] -to [get_ports out1]

188
dcalc/test/dcalc_gcd_arnoldi_prima.tcl
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@ -1,188 +0,0 @@
# Test Arnoldi and Prima delay calculators with a larger design (GCD sky130hd)
# having many more parasitic nodes, exercising deeper Arnoldi/Prima reduction
# paths, higher-order matrix operations, and multi-driver net handling.
# Targets:
# ArnoldiDelayCalc.cc: gateDelay, gateDelaySlew, ar1_ceff_delay,
# ra_rdelay_1, ra_get_r, ra_get_s, ra_solve_for_s, pr_solve1, pr_solve3,
# delay_work_set_thresholds, reportGateDelay, finishDrvrPin,
# reduceParasitic (arnoldi reduce from larger networks)
# PrimaDelayCalc.cc: gateDelay, inputPortDelay, reduceParasitic,
# primaReduceRc, stampR, stampC, prima matrix solve,
# setPrimaReduceOrder, buildNodeMap, findParasitic
# ArnoldiReduce.cc: arnoldi reduce matrix, arnoldi basis,
# arnoldi iteration (more iterations for larger networks)
# ReduceParasitics.cc: reduceToPiElmore, reduceToPiPoleResidue
# GraphDelayCalc.cc: findVertexDelay with arnoldi/prima
source ../../test/helpers.tcl
############################################################
# Read Sky130 library and GCD design
############################################################
read_liberty ../../test/sky130hd/sky130hd_tt.lib
read_verilog ../../examples/gcd_sky130hd.v
link_design gcd
source ../../examples/gcd_sky130hd.sdc
# Read SPEF parasitics (large: ~19k lines, many parasitic nodes)
read_spef ../../examples/gcd_sky130hd.spef
############################################################
# Baseline with default delay calculator (dmp_ceff_elmore)
############################################################
puts "--- baseline dmp_ceff_elmore ---"
report_checks -endpoint_count 3
report_checks -path_delay min -endpoint_count 3
############################################################
# Arnoldi with large GCD design
# More parasitic nodes => deeper arnoldi reduction
############################################################
puts "--- arnoldi with gcd ---"
set_delay_calculator arnoldi
report_checks -endpoint_count 3
report_checks -path_delay min -endpoint_count 3
report_checks -fields {slew cap input_pins nets fanout}
report_checks -format full_clock
# Arnoldi report_dcalc on various cells in the design
puts "--- arnoldi report_dcalc ---"
set cell_count 0
foreach cell_obj [get_cells *] {
set cname [get_name $cell_obj]
set pins [get_pins $cname/*]
set in_pins {}
set out_pins {}
foreach p $pins {
set dir [get_property $p direction]
if {$dir == "input"} {
lappend in_pins $p
} elseif {$dir == "output"} {
lappend out_pins $p
}
}
if {[llength $in_pins] > 0 && [llength $out_pins] > 0} {
catch {
report_dcalc -from [lindex $in_pins 0] -to [lindex $out_pins 0] -max
}
incr cell_count
if {$cell_count >= 30} break
}
}
# Arnoldi with varying input slews
puts "--- arnoldi varying slew ---"
foreach slew_val {0.01 0.05 0.1 0.5 1.0} {
set_input_transition $slew_val [all_inputs]
report_checks -endpoint_count 1
puts "arnoldi slew=$slew_val done"
}
set_input_transition 0.1 [all_inputs]
# Arnoldi with varying output loads
puts "--- arnoldi varying loads ---"
foreach load_val {0.0001 0.001 0.01 0.05} {
set_load $load_val [get_ports resp_msg*]
report_checks -endpoint_count 1
puts "arnoldi load=$load_val done"
}
set_load 0 [get_ports resp_msg*]
############################################################
# Prima with GCD design and varying reduce orders
############################################################
puts "--- prima with gcd ---"
catch {set_delay_calculator prima} msg
puts "set prima: $msg"
report_checks -endpoint_count 3
report_checks -path_delay min -endpoint_count 3
report_checks -fields {slew cap input_pins nets fanout}
# Prima with varying reduce orders
puts "--- prima reduce orders ---"
foreach order {1 2 3 4 5} {
sta::set_prima_reduce_order $order
report_checks -endpoint_count 1
puts "prima order=$order done"
}
# Reset to default
sta::set_prima_reduce_order 3
# Prima report_dcalc
puts "--- prima report_dcalc ---"
set cell_count 0
foreach cell_obj [get_cells *] {
set cname [get_name $cell_obj]
set pins [get_pins $cname/*]
set in_pins {}
set out_pins {}
foreach p $pins {
set dir [get_property $p direction]
if {$dir == "input"} {
lappend in_pins $p
} elseif {$dir == "output"} {
lappend out_pins $p
}
}
if {[llength $in_pins] > 0 && [llength $out_pins] > 0} {
catch {
report_dcalc -from [lindex $in_pins 0] -to [lindex $out_pins 0] -max
}
incr cell_count
if {$cell_count >= 30} break
}
}
# Prima varying slew
puts "--- prima varying slew ---"
foreach slew_val {0.01 0.1 0.5 2.0} {
set_input_transition $slew_val [all_inputs]
report_checks -endpoint_count 1
puts "prima slew=$slew_val done"
}
set_input_transition 0.1 [all_inputs]
############################################################
# Rapid switching between calculators
# Exercises reinit, cleanup, and cache invalidation paths
############################################################
puts "--- rapid switching ---"
set_delay_calculator dmp_ceff_elmore
report_checks -endpoint_count 1
set_delay_calculator dmp_ceff_two_pole
report_checks -endpoint_count 1
set_delay_calculator lumped_cap
report_checks -endpoint_count 1
set_delay_calculator arnoldi
report_checks -endpoint_count 1
set_delay_calculator prima
report_checks -endpoint_count 1
set_delay_calculator dmp_ceff_elmore
report_checks -endpoint_count 1
############################################################
# delay_calc_names and is_delay_calc_name
############################################################
puts "--- delay calc name queries ---"
set names [sta::delay_calc_names]
puts "delay calc names: $names"
foreach name {dmp_ceff_elmore dmp_ceff_two_pole lumped_cap arnoldi prima} {
set result [sta::is_delay_calc_name $name]
puts "is_delay_calc_name $name = $result"
}
set result [sta::is_delay_calc_name nonexistent_calc]
puts "is_delay_calc_name nonexistent_calc = $result"

234
dcalc/test/dcalc_graph_delay.tcl
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# Test GraphDelayCalc with a larger design for coverage improvement.
# Targets: GraphDelayCalc.cc (findDelays, seedRootSlews, seedInvalidDelays,
# findVertexDelay, findCheckEdgeDelays, findLatchEdgeDelays,
# findMultiDrvrNet, mergeMultiDrvrNets, loadDelay, netCaps,
# hasMultiDrvrNet, reportCheckMultiDrvrNet, deleteVertexBefore,
# levelChangedBefore, levelsChangedBefore, delayInvalid(pin/vertex),
# setIncrementalDelayTolerance, incrementalDelayTolerance)
# DmpCeff.cc (dmpCeffElmore, dmpCeffTwoPole paths with various loads)
# NetCaps.cc (net capacitance queries, pinCapacitance, wireCap)
# ArcDelayCalc.cc (arc delay for various gate types)
# DelayCalcBase.cc (base class paths)
read_liberty ../../test/nangate45/Nangate45_typ.lib
read_verilog dcalc_multidriver_test.v
link_design dcalc_multidriver_test
create_clock -name clk -period 10 [get_ports clk]
set_input_delay -clock clk 0 [get_ports {in1 in2 in3 in4 sel}]
set_output_delay -clock clk 0 [get_ports {out1 out2 out3}]
set_input_transition 0.1 [get_ports {in1 in2 in3 in4 sel clk}]
#---------------------------------------------------------------
# Baseline timing (exercises findDelays, seedRootSlews)
#---------------------------------------------------------------
puts "--- baseline timing ---"
report_checks
report_checks -path_delay min
report_checks -path_delay max
#---------------------------------------------------------------
# Multiple from/to path queries (exercises findVertexDelay for many paths)
#---------------------------------------------------------------
puts "--- multiple path queries ---"
report_checks -from [get_ports in1] -to [get_ports out1]
report_checks -from [get_ports in1] -to [get_ports out2]
report_checks -from [get_ports in1] -to [get_ports out3]
report_checks -from [get_ports in2] -to [get_ports out1]
report_checks -from [get_ports in2] -to [get_ports out2]
report_checks -from [get_ports in3] -to [get_ports out1]
report_checks -from [get_ports in4] -to [get_ports out2]
report_checks -from [get_ports sel] -to [get_ports out1]
#---------------------------------------------------------------
# Through pin queries (exercises more graph traversal)
#---------------------------------------------------------------
puts "--- through pin queries ---"
report_checks -through [get_pins or1/ZN]
report_checks -through [get_pins nand1/ZN]
report_checks -through [get_pins nor1/ZN]
report_checks -through [get_pins and1/ZN]
report_checks -through [get_pins inv1/ZN]
#---------------------------------------------------------------
# report_dcalc for all arc types in design
# Exercises: arc delay computation for BUF, INV, AND, OR, NAND, NOR
#---------------------------------------------------------------
puts "--- report_dcalc various gate types ---"
# BUF arcs
catch {report_dcalc -from [get_pins buf1/A] -to [get_pins buf1/Z] -max} msg
puts "dcalc buf1 max: $msg"
catch {report_dcalc -from [get_pins buf1/A] -to [get_pins buf1/Z] -min} msg
puts "dcalc buf1 min: $msg"
# INV arcs
catch {report_dcalc -from [get_pins inv1/A] -to [get_pins inv1/ZN] -max} msg
puts "dcalc inv1 max: $msg"
# AND arcs (both inputs)
catch {report_dcalc -from [get_pins and1/A1] -to [get_pins and1/ZN] -max} msg
puts "dcalc and1 A1->ZN max: $msg"
catch {report_dcalc -from [get_pins and1/A2] -to [get_pins and1/ZN] -max} msg
puts "dcalc and1 A2->ZN max: $msg"
# OR arcs
catch {report_dcalc -from [get_pins or1/A1] -to [get_pins or1/ZN] -max} msg
puts "dcalc or1 A1->ZN max: $msg"
catch {report_dcalc -from [get_pins or1/A2] -to [get_pins or1/ZN] -max} msg
puts "dcalc or1 A2->ZN max: $msg"
# NAND arcs
catch {report_dcalc -from [get_pins nand1/A1] -to [get_pins nand1/ZN] -max} msg
puts "dcalc nand1 A1->ZN max: $msg"
catch {report_dcalc -from [get_pins nand1/A2] -to [get_pins nand1/ZN] -max} msg
puts "dcalc nand1 A2->ZN max: $msg"
# NOR arcs
catch {report_dcalc -from [get_pins nor1/A1] -to [get_pins nor1/ZN] -max} msg
puts "dcalc nor1 A1->ZN max: $msg"
catch {report_dcalc -from [get_pins nor1/A2] -to [get_pins nor1/ZN] -max} msg
puts "dcalc nor1 A2->ZN max: $msg"
# DFF arcs
catch {report_dcalc -from [get_pins reg1/CK] -to [get_pins reg1/Q] -max} msg
puts "dcalc reg1 CK->Q max: $msg"
catch {report_dcalc -from [get_pins reg1/CK] -to [get_pins reg1/Q] -min} msg
puts "dcalc reg1 CK->Q min: $msg"
# DFF check arcs
catch {report_dcalc -from [get_pins reg1/CK] -to [get_pins reg1/D] -max} msg
puts "dcalc reg1 setup max: $msg"
catch {report_dcalc -from [get_pins reg1/CK] -to [get_pins reg1/D] -min} msg
puts "dcalc reg1 hold min: $msg"
catch {report_dcalc -from [get_pins reg2/CK] -to [get_pins reg2/Q] -max} msg
puts "dcalc reg2 CK->Q max: $msg"
catch {report_dcalc -from [get_pins reg2/CK] -to [get_pins reg2/D] -max} msg
puts "dcalc reg2 setup max: $msg"
# report_dcalc with -digits
catch {report_dcalc -from [get_pins buf1/A] -to [get_pins buf1/Z] -digits 2} msg
puts "dcalc buf1 2 digits: $msg"
catch {report_dcalc -from [get_pins buf1/A] -to [get_pins buf1/Z] -digits 6} msg
puts "dcalc buf1 6 digits: $msg"
catch {report_dcalc -from [get_pins buf1/A] -to [get_pins buf1/Z] -digits 10} msg
puts "dcalc buf1 10 digits: $msg"
#---------------------------------------------------------------
# Incremental delay calculation: change constraints, recompute
# Exercises: seedInvalidDelays, delayInvalid, incremental paths
#---------------------------------------------------------------
puts "--- incremental delay calculation ---"
# Change loads
set_load 0.001 [get_ports out1]
report_checks -from [get_ports in1] -to [get_ports out1]
set_load 0.01 [get_ports out1]
report_checks -from [get_ports in1] -to [get_ports out1]
set_load 0.1 [get_ports out1]
report_checks -from [get_ports in1] -to [get_ports out1]
set_load 0.05 [get_ports out2]
report_checks -from [get_ports in4] -to [get_ports out2]
# Reset loads
set_load 0 [get_ports out1]
set_load 0 [get_ports out2]
# Change input transitions
set_input_transition 0.01 [get_ports in1]
report_checks -from [get_ports in1] -to [get_ports out1]
set_input_transition 1.0 [get_ports in1]
report_checks -from [get_ports in1] -to [get_ports out1]
set_input_transition 0.1 [get_ports in1]
# Change clock period
create_clock -name clk -period 5 [get_ports clk]
report_checks
# Change input/output delays
set_input_delay -clock clk 1.0 [get_ports in1]
report_checks -from [get_ports in1] -to [get_ports out1]
set_output_delay -clock clk 2.0 [get_ports out1]
report_checks -from [get_ports in1] -to [get_ports out1]
#---------------------------------------------------------------
# Test various delay calculators on larger design
# Exercises: calculator switching, copy/init paths
#---------------------------------------------------------------
puts "--- calculator switching ---"
set_delay_calculator unit
report_checks
set_delay_calculator lumped_cap
report_checks
set_delay_calculator dmp_ceff_elmore
report_checks
set_delay_calculator dmp_ceff_two_pole
report_checks
set_delay_calculator ccs_ceff
report_checks
# Switch back to default
set_delay_calculator dmp_ceff_elmore
#---------------------------------------------------------------
# report_checks with various formatting options
#---------------------------------------------------------------
puts "--- report_checks formatting ---"
report_checks -fields {slew cap input_pins nets fanout}
report_checks -format full_clock
report_checks -format full_clock_expanded
report_checks -endpoint_count 3
report_checks -group_count 5
report_checks -unconstrained
report_checks -sort_by_slack
#---------------------------------------------------------------
# report_check_types
#---------------------------------------------------------------
puts "--- report_check_types ---"
report_check_types -max_delay -verbose
report_check_types -min_delay -verbose
report_check_types -max_delay -min_delay -verbose

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dcalc/test/dcalc_incremental_tolerance.tcl
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# Test GraphDelayCalc incremental delay tolerance and various invalidation paths.
# Targets:
# GraphDelayCalc.cc: setIncrementalDelayTolerance, incrementalDelayTolerance,
# seedInvalidDelays, delayInvalid(pin), delayInvalid(vertex),
# findDelays incremental paths, levelChangedBefore, levelsChangedBefore,
# deleteVertexBefore, findVertexDelay, findCheckEdgeDelays,
# findLatchEdgeDelays, netCaps, loadDelay, seedRootSlews
# DmpCeff.cc: incremental recalculation with tolerance changes
# NetCaps.cc: net capacitance recomputation after changes
# ArcDelayCalc.cc: arc delay recalculation paths
source ../../test/helpers.tcl
read_liberty ../../test/nangate45/Nangate45_typ.lib
read_verilog dcalc_multidriver_test.v
link_design dcalc_multidriver_test
create_clock -name clk -period 10 [get_ports clk]
set_input_delay -clock clk 0 [get_ports {in1 in2 in3 in4 sel}]
set_output_delay -clock clk 0 [get_ports {out1 out2 out3}]
set_input_transition 0.1 [get_ports {in1 in2 in3 in4 sel clk}]
#---------------------------------------------------------------
# Test 1: Baseline timing
#---------------------------------------------------------------
puts "--- Test 1: baseline timing ---"
report_checks
report_checks -path_delay min
#---------------------------------------------------------------
# Test 2: Set incremental delay tolerance
# Exercises: setIncrementalDelayTolerance, incrementalDelayTolerance
#---------------------------------------------------------------
puts "--- Test 2: incremental delay tolerance ---"
# Set large tolerance (will suppress many incremental updates)
sta::set_delay_calc_incremental_tolerance 0.5
# Change input transition - large tolerance means less recalc
set_input_transition 0.2 [get_ports in1]
report_checks -from [get_ports in1] -to [get_ports out1]
# Change back
set_input_transition 0.1 [get_ports in1]
report_checks -from [get_ports in1] -to [get_ports out1]
# Set small tolerance (will recompute more aggressively)
sta::set_delay_calc_incremental_tolerance 0.001
set_input_transition 0.2 [get_ports in1]
report_checks -from [get_ports in1] -to [get_ports out1]
set_input_transition 0.1 [get_ports in1]
report_checks -from [get_ports in1] -to [get_ports out1]
# Zero tolerance
sta::set_delay_calc_incremental_tolerance 0.0
#---------------------------------------------------------------
# Test 3: Incremental updates with load changes
# Exercises: seedInvalidDelays, delayInvalid, net cap recomputation
#---------------------------------------------------------------
puts "--- Test 3: incremental load changes ---"
# Successively larger loads on out1
foreach load_val {0.0001 0.001 0.005 0.01 0.05 0.1 0.5} {
set_load $load_val [get_ports out1]
report_checks -from [get_ports in1] -to [get_ports out1]
puts "load=$load_val: done"
}
set_load 0 [get_ports out1]
# Loads on multiple outputs simultaneously
set_load 0.01 [get_ports out1]
set_load 0.01 [get_ports out2]
set_load 0.01 [get_ports out3]
report_checks
set_load 0 [get_ports out1]
set_load 0 [get_ports out2]
set_load 0 [get_ports out3]
#---------------------------------------------------------------
# Test 4: Incremental updates with transition changes
# Exercises: seedRootSlews with varying slew values
#---------------------------------------------------------------
puts "--- Test 4: incremental slew changes ---"
# Very fast transitions
set_input_transition 0.001 [get_ports {in1 in2 in3 in4 sel}]
report_checks
# Medium transitions
set_input_transition 0.1 [get_ports {in1 in2 in3 in4 sel}]
report_checks
# Very slow transitions
set_input_transition 2.0 [get_ports {in1 in2 in3 in4 sel}]
report_checks
# Different slews on different inputs
set_input_transition 0.01 [get_ports in1]
set_input_transition 0.5 [get_ports in2]
set_input_transition 0.001 [get_ports in3]
set_input_transition 1.0 [get_ports in4]
set_input_transition 0.1 [get_ports sel]
report_checks
# Restore
set_input_transition 0.1 [get_ports {in1 in2 in3 in4 sel clk}]
#---------------------------------------------------------------
# Test 5: Incremental timing constraint changes
# Exercises: findDelays with constraint invalidation
#---------------------------------------------------------------
puts "--- Test 5: constraint changes ---"
# Change clock period
create_clock -name clk -period 5 [get_ports clk]
report_checks
create_clock -name clk -period 20 [get_ports clk]
report_checks
create_clock -name clk -period 10 [get_ports clk]
# Change input delays
set_input_delay -clock clk 2.0 [get_ports in1]
report_checks -from [get_ports in1] -to [get_ports out1]
set_input_delay -clock clk 0.0 [get_ports in1]
# Change output delays
set_output_delay -clock clk 3.0 [get_ports out1]
report_checks -to [get_ports out1]
set_output_delay -clock clk 0.0 [get_ports out1]
#---------------------------------------------------------------
# Test 6: Network modification triggers delay invalidation
# Exercises: makeInstance, connectPin, disconnectPin => delayInvalid
#---------------------------------------------------------------
puts "--- Test 6: network modification invalidation ---"
# Add new instance
set new_inst [make_instance extra_buf NangateOpenCellLibrary/BUF_X4]
set new_net [make_net extra_net]
connect_pin extra_net extra_buf/A
report_checks
# Disconnect and delete
disconnect_pin extra_net extra_buf/A
delete_instance extra_buf
delete_net extra_net
report_checks
#---------------------------------------------------------------
# Test 7: Replace cell triggers delay recalc
# Exercises: replaceCell => incremental delay update
#---------------------------------------------------------------
puts "--- Test 7: replace cell ---"
# Replace buf1 with larger buffer
replace_cell buf1 NangateOpenCellLibrary/BUF_X4
report_checks -from [get_ports in1] -to [get_ports out1]
replace_cell buf1 NangateOpenCellLibrary/BUF_X2
report_checks -from [get_ports in1] -to [get_ports out1]
replace_cell buf1 NangateOpenCellLibrary/BUF_X1
report_checks -from [get_ports in1] -to [get_ports out1]
# Replace multiple cells
replace_cell and1 NangateOpenCellLibrary/AND2_X2
replace_cell or1 NangateOpenCellLibrary/OR2_X2
report_checks
replace_cell and1 NangateOpenCellLibrary/AND2_X1
replace_cell or1 NangateOpenCellLibrary/OR2_X1
report_checks
#---------------------------------------------------------------
# Test 8: Tolerance with calculator switching
# Exercises: setIncrementalDelayTolerance persists across calc changes
#---------------------------------------------------------------
puts "--- Test 8: tolerance with calculator switching ---"
sta::set_delay_calc_incremental_tolerance 0.1
set_delay_calculator lumped_cap
report_checks
set_delay_calculator dmp_ceff_elmore
report_checks
set_delay_calculator dmp_ceff_two_pole
report_checks
set_delay_calculator unit
report_checks
# Restore
set_delay_calculator dmp_ceff_elmore
sta::set_delay_calc_incremental_tolerance 0.0
report_checks

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dcalc/test/dcalc_multi_engine_spef.tcl
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# Test multiple delay calc engines with SPEF parasitics and prima reduce order.
# Targets:
# PrimaDelayCalc.cc: setPrimaReduceOrder, primaDelay, primaReduceRc,
# prima2, prima3, primaResStamp, primaCapStamp, primaPostReduction
# ArnoldiDelayCalc.cc: arnoldiDelay, arnoldiReduceRc, arnoldi2, arnoldi3,
# arnoldiExpand, loadDelay, gateDelay, gateSlew
# ArnoldiReduce.cc: arnoldi reduce matrix, arnoldi iteration
# GraphDelayCalc.cc: findDelays with parasitic calc engine changes,
# findVertexDelay with different parasitic reduction
# DmpCeff.cc: ceffPiElmore, dmpCeffIter with SPEF parasitics
# DelayCalc.i: delay_calc_names, is_delay_calc_name, set_prima_reduce_order
source ../../test/helpers.tcl
# Read ASAP7 libraries
read_liberty ../../test/asap7/asap7sc7p5t_SEQ_RVT_FF_nldm_220123.lib
read_liberty ../../test/asap7/asap7sc7p5t_INVBUF_RVT_FF_nldm_220122.lib.gz
read_liberty ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz
read_liberty ../../test/asap7/asap7sc7p5t_OA_RVT_FF_nldm_211120.lib.gz
read_liberty ../../test/asap7/asap7sc7p5t_AO_RVT_FF_nldm_211120.lib.gz
read_verilog ../../test/reg1_asap7.v
link_design top
create_clock -name clk -period 500 {clk1 clk2 clk3}
set_input_delay -clock clk 1 {in1 in2}
set_output_delay -clock clk 1 [get_ports out]
set_input_transition 10 {in1 in2 clk1 clk2 clk3}
set_propagated_clock {clk1 clk2 clk3}
#---------------------------------------------------------------
# Test 1: Enumerate delay calculator names
# Exercises: delayCalcNames, isDelayCalcName
#---------------------------------------------------------------
puts "--- Test 1: delay calc names ---"
set calc_names [sta::delay_calc_names]
puts "delay calc names: $calc_names"
foreach name {lumped_cap dmp_ceff_elmore dmp_ceff_two_pole arnoldi prima unit} {
set valid [sta::is_delay_calc_name $name]
puts "is_delay_calc_name $name: $valid"
}
# Invalid name
set invalid [sta::is_delay_calc_name "nonexistent_calc"]
puts "is_delay_calc_name nonexistent: $invalid"
#---------------------------------------------------------------
# Test 2: Read SPEF and run with default calculator
#---------------------------------------------------------------
puts "--- Test 2: SPEF with default calc ---"
read_spef ../../test/reg1_asap7.spef
report_checks
report_checks -path_delay min
report_checks -from [get_ports in1] -to [get_ports out]
report_checks -from [get_ports in2] -to [get_ports out]
#---------------------------------------------------------------
# Test 3: Prima with varying reduce order
# Exercises: setPrimaReduceOrder, prima reduction order paths
#---------------------------------------------------------------
puts "--- Test 3: prima with reduce order ---"
catch {set_delay_calculator prima} msg
puts "set prima: $msg"
# Default prima
report_checks
# Prima reduce order 1 (minimal)
catch {sta::set_prima_reduce_order 1} msg
puts "set_prima_reduce_order 1: $msg"
report_checks
# Prima reduce order 2
catch {sta::set_prima_reduce_order 2} msg
puts "set_prima_reduce_order 2: $msg"
report_checks
# Prima reduce order 3
catch {sta::set_prima_reduce_order 3} msg
puts "set_prima_reduce_order 3: $msg"
report_checks
# Prima reduce order 5 (higher order)
catch {sta::set_prima_reduce_order 5} msg
puts "set_prima_reduce_order 5: $msg"
report_checks
# report_dcalc with different orders
report_dcalc -from [get_pins u1/A] -to [get_pins u1/Y] -max
puts "prima dcalc u1 order=5: done"
report_dcalc -from [get_pins u2/A] -to [get_pins u2/Y] -max
puts "prima dcalc u2 order=5: done"
report_dcalc -from [get_pins r1/CLK] -to [get_pins r1/Q] -max
puts "prima dcalc r1 order=5: done"
# Switch back to lower order
sta::set_prima_reduce_order 2
report_checks
# report_dcalc at order 2
report_dcalc -from [get_pins u1/A] -to [get_pins u1/Y] -max
puts "prima dcalc u1 order=2: done"
report_dcalc -from [get_pins r3/CLK] -to [get_pins r3/Q] -max
puts "prima dcalc r3 order=2: done"
# Various slew values with prima
foreach slew_val {1 10 50 100 200} {
set_input_transition $slew_val {in1 in2 clk1 clk2 clk3}
report_checks
puts "prima slew=$slew_val: done"
}
set_input_transition 10 {in1 in2 clk1 clk2 clk3}
#---------------------------------------------------------------
# Test 4: Arnoldi with SPEF
# Exercises: arnoldiDelay, arnoldiReduceRc, arnoldi expansion
#---------------------------------------------------------------
puts "--- Test 4: arnoldi with SPEF ---"
catch {set_delay_calculator arnoldi} msg
puts "set arnoldi: $msg"
report_checks
report_checks -path_delay min
# Various slew values with arnoldi
foreach slew_val {1 10 50 100} {
set_input_transition $slew_val {in1 in2 clk1 clk2 clk3}
report_checks
puts "arnoldi slew=$slew_val: done"
}
set_input_transition 10 {in1 in2 clk1 clk2 clk3}
# Various load values with arnoldi
foreach load_val {0.0001 0.001 0.01 0.05} {
set_load $load_val [get_ports out]
report_checks
puts "arnoldi load=$load_val: done"
}
set_load 0 [get_ports out]
# report_dcalc with arnoldi
report_dcalc -from [get_pins u1/A] -to [get_pins u1/Y] -max
puts "arnoldi dcalc u1: done"
report_dcalc -from [get_pins u2/A] -to [get_pins u2/Y] -max
puts "arnoldi dcalc u2 A: done"
report_dcalc -from [get_pins u2/B] -to [get_pins u2/Y] -max
puts "arnoldi dcalc u2 B: done"
report_dcalc -from [get_pins r1/CLK] -to [get_pins r1/Q] -max
puts "arnoldi dcalc r1: done"
report_dcalc -from [get_pins r2/CLK] -to [get_pins r2/Q] -min
puts "arnoldi dcalc r2 min: done"
report_dcalc -from [get_pins r3/CLK] -to [get_pins r3/Q] -max
puts "arnoldi dcalc r3: done"
# DFF check arcs
report_dcalc -from [get_pins r1/CLK] -to [get_pins r1/D] -max
puts "arnoldi r1 setup: done"
report_dcalc -from [get_pins r1/CLK] -to [get_pins r1/D] -min
puts "arnoldi r1 hold: done"
#---------------------------------------------------------------
# Test 5: Rapid engine switching with SPEF (reinit paths)
# Exercises: calculator copy/reinit during switching
#---------------------------------------------------------------
puts "--- Test 5: rapid engine switching ---"
set_delay_calculator lumped_cap
report_checks
set_delay_calculator dmp_ceff_elmore
report_checks
set_delay_calculator dmp_ceff_two_pole
report_checks
set_delay_calculator prima
report_checks
set_delay_calculator arnoldi
report_checks
set_delay_calculator unit
report_checks
set_delay_calculator dmp_ceff_elmore
report_checks
#---------------------------------------------------------------
# Test 6: find_delays explicit call
# Exercises: findDelays direct path
#---------------------------------------------------------------
puts "--- Test 6: find_delays ---"
sta::find_delays
sta::delays_invalid
sta::find_delays
#---------------------------------------------------------------
# Test 7: Detailed report_checks with various formats after SPEF
#---------------------------------------------------------------
puts "--- Test 7: report formats ---"
report_checks -fields {slew cap input_pins nets fanout}
report_checks -format full_clock
report_checks -format full_clock_expanded
report_checks -endpoint_count 3
report_checks -group_count 2
report_checks -digits 6

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dcalc/test/dcalc_prima.tcl
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# Test prima delay calculator with SPEF parasitics
# Targets: PrimaDelayCalc.cc (61.7% coverage, 603 lines)
# Also exercises ArnoldiReduce.cc and ArnoldiDelayCalc.cc paths
# Read ASAP7 libraries
read_liberty ../../test/asap7/asap7sc7p5t_SEQ_RVT_FF_nldm_220123.lib
read_liberty ../../test/asap7/asap7sc7p5t_INVBUF_RVT_FF_nldm_220122.lib.gz
read_liberty ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz
read_liberty ../../test/asap7/asap7sc7p5t_OA_RVT_FF_nldm_211120.lib.gz
read_liberty ../../test/asap7/asap7sc7p5t_AO_RVT_FF_nldm_211120.lib.gz
read_verilog ../../test/reg1_asap7.v
link_design top
create_clock -name clk -period 500 {clk1 clk2 clk3}
set_input_delay -clock clk 1 {in1 in2}
set_output_delay -clock clk 1 [get_ports out]
set_input_transition 10 {in1 in2 clk1 clk2 clk3}
set_propagated_clock {clk1 clk2 clk3}
# Read SPEF parasitics
puts "--- Reading SPEF ---"
read_spef ../../test/reg1_asap7.spef
#---------------------------------------------------------------
# Test prima delay calculator
#---------------------------------------------------------------
puts "--- prima delay calculator ---"
catch {set_delay_calculator prima} msg
puts "set_delay_calculator prima: $msg"
report_checks
report_checks -path_delay min
report_checks -path_delay max
report_checks -fields {slew cap input_pins}
report_checks -format full_clock
# report_dcalc with prima
catch {report_dcalc -from [get_pins u1/A] -to [get_pins u1/Y]} msg
puts "prima dcalc u1 A->Y: $msg"
catch {report_dcalc -from [get_pins u2/A] -to [get_pins u2/Y]} msg
puts "prima dcalc u2 A->Y: $msg"
catch {report_dcalc -from [get_pins u2/B] -to [get_pins u2/Y]} msg
puts "prima dcalc u2 B->Y: $msg"
catch {report_dcalc -from [get_pins r1/CLK] -to [get_pins r1/Q]} msg
puts "prima dcalc r1 CLK->Q: $msg"
catch {report_dcalc -from [get_pins r3/CLK] -to [get_pins r3/Q] -max} msg
puts "prima dcalc r3 CLK->Q max: $msg"
catch {report_dcalc -from [get_pins r3/CLK] -to [get_pins r3/D] -max} msg
puts "prima dcalc r3 setup: $msg"
catch {report_dcalc -from [get_pins r3/CLK] -to [get_pins r3/D] -min} msg
puts "prima dcalc r3 hold: $msg"
# Report from different paths
report_checks -from [get_ports in1] -to [get_ports out]
report_checks -from [get_ports in2] -to [get_ports out]
#---------------------------------------------------------------
# Now switch to arnoldi and compare
#---------------------------------------------------------------
puts "--- arnoldi delay calculator with same design ---"
catch {set_delay_calculator arnoldi} msg
puts "set_delay_calculator arnoldi: $msg"
report_checks
catch {report_dcalc -from [get_pins u1/A] -to [get_pins u1/Y] -max} msg
puts "arnoldi dcalc u1 A->Y max: $msg"
catch {report_dcalc -from [get_pins u2/A] -to [get_pins u2/Y] -max} msg
puts "arnoldi dcalc u2 A->Y max: $msg"
catch {report_dcalc -from [get_pins r1/CLK] -to [get_pins r1/Q] -max} msg
puts "arnoldi dcalc r1 CLK->Q max: $msg"
catch {report_dcalc -from [get_pins r1/CLK] -to [get_pins r1/Q] -min} msg
puts "arnoldi dcalc r1 CLK->Q min: $msg"
report_checks -fields {slew cap input_pins nets fanout}
#---------------------------------------------------------------
# Switch to lumped_cap with parasitics
#---------------------------------------------------------------
puts "--- lumped_cap with parasitics ---"
set_delay_calculator lumped_cap
report_checks
catch {report_dcalc -from [get_pins u1/A] -to [get_pins u1/Y] -max} msg
puts "lumped_cap dcalc u1: $msg"
#---------------------------------------------------------------
# Switch to dmp_ceff_two_pole with parasitics
#---------------------------------------------------------------
puts "--- dmp_ceff_two_pole with parasitics ---"
set_delay_calculator dmp_ceff_two_pole
report_checks
report_checks -path_delay min
report_checks -path_delay max
catch {report_dcalc -from [get_pins u1/A] -to [get_pins u1/Y] -max} msg
puts "dmp_ceff_two_pole dcalc u1: $msg"
catch {report_dcalc -from [get_pins u2/A] -to [get_pins u2/Y] -max} msg
puts "dmp_ceff_two_pole dcalc u2 A->Y: $msg"
catch {report_dcalc -from [get_pins u2/B] -to [get_pins u2/Y] -max} msg
puts "dmp_ceff_two_pole dcalc u2 B->Y: $msg"
catch {report_dcalc -from [get_pins r1/CLK] -to [get_pins r1/Q] -max} msg
puts "dmp_ceff_two_pole dcalc r1 CLK->Q: $msg"
report_checks -fields {slew cap}
#---------------------------------------------------------------
# Switch back to default
#---------------------------------------------------------------
puts "--- dmp_ceff_elmore (default) ---"
set_delay_calculator dmp_ceff_elmore
report_checks

224
dcalc/test/dcalc_prima_arnoldi_deep.tcl
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@ -1,224 +0,0 @@
# Deep Prima and Arnoldi delay calculator testing with different
# SPEF files, reduce orders, extreme conditions, and Nangate45 PDK.
# Targets:
# PrimaDelayCalc.cc: primaDelay, primaReduceRc, prima2, prima3,
# primaResStamp, primaCapStamp, primaPostReduction,
# gateDelay, gateSlew, loadDelay, reduceParasitics
# ArnoldiDelayCalc.cc: arnoldiDelay, arnoldiReduceRc, arnoldi2,
# arnoldi3, arnoldiExpand, loadDelay, gateDelay, gateSlew
# ArnoldiReduce.cc: arnoldi reduce matrix, arnoldi basis, arnoldi iteration
# GraphDelayCalc.cc: findVertexDelay with arnoldi/prima,
# seedInvalidDelays, loadPinCapacitanceChanged
# DmpCeff.cc: ceffPiElmore with arnoldi/prima parasitic models
# DelayCalc.i: delay_calc_names, is_delay_calc_name, set_prima_reduce_order
source ../../test/helpers.tcl
############################################################
# Read Nangate45 library and search_test1 design
############################################################
read_liberty ../../test/nangate45/Nangate45_typ.lib
read_verilog ../../search/test/search_test1.v
link_design search_test1
create_clock -name clk -period 10 [get_ports clk]
set_input_delay -clock clk 1.0 [get_ports {in1 in2}]
set_output_delay -clock clk 2.0 [get_ports out1]
set_input_transition 0.1 [all_inputs]
############################################################
# Read SPEF parasitics for example1
# This exercises SPEF parsing and parasitic model construction
############################################################
read_spef ../../search/test/search_test1.spef
############################################################
# Test Prima with Nangate45 + SPEF
############################################################
puts "--- prima with Nangate45 ---"
catch {set_delay_calculator prima} msg
puts "set prima: $msg"
report_checks
report_checks -path_delay min
report_checks -path_delay max
report_checks -fields {slew cap input_pins nets fanout}
report_checks -format full_clock
# Multiple endpoint paths
report_checks -endpoint_count 5
# From/to specific paths
report_checks -from [get_ports in1] -endpoint_count 3
report_checks -to [get_ports out1] -endpoint_count 3
report_checks -from [get_ports in2] -endpoint_count 3
############################################################
# Prima with varying reduce orders
############################################################
puts "--- prima reduce order ---"
catch {sta::set_prima_reduce_order 1} msg
puts "set_prima_reduce_order 1: $msg"
report_checks
catch {sta::set_prima_reduce_order 2} msg
puts "set_prima_reduce_order 2: $msg"
report_checks
catch {sta::set_prima_reduce_order 3} msg
puts "set_prima_reduce_order 3: $msg"
report_checks
catch {sta::set_prima_reduce_order 4} msg
puts "set_prima_reduce_order 4: $msg"
report_checks
catch {sta::set_prima_reduce_order 5} msg
puts "set_prima_reduce_order 5: $msg"
report_checks
# Reset to default
sta::set_prima_reduce_order 3
############################################################
# Prima with varying slew
############################################################
puts "--- prima varying slew ---"
set_input_transition 0.05 [all_inputs]
report_checks
set_input_transition 0.5 [all_inputs]
report_checks
set_input_transition 2.0 [all_inputs]
report_checks
set_input_transition 0.1 [all_inputs]
############################################################
# Prima with varying loads
############################################################
puts "--- prima varying loads ---"
foreach load_val {0.0001 0.001 0.005 0.01 0.05} {
set_load $load_val [get_ports out1]
set_load $load_val [get_ports out1]
report_checks
puts "prima load=$load_val: done"
}
set_load 0 [get_ports out1]
set_load 0 [get_ports out1]
############################################################
# Prima report_dcalc for specific arcs
############################################################
puts "--- prima report_dcalc ---"
# Find some pins in the design
set all_cells [get_cells *]
set first_cell [lindex $all_cells 0]
set cell_name [get_name $first_cell]
puts "first cell: $cell_name"
# Try dcalc on various cells
foreach cell_obj $all_cells {
set cname [get_name $cell_obj]
set ref [get_property $cell_obj ref_name]
set pins [get_pins $cname/*]
if {[llength $pins] >= 2} {
set in_pin [lindex $pins 0]
set out_pin [lindex $pins end]
catch {
report_dcalc -from $in_pin -to $out_pin -max
}
}
}
############################################################
# Switch to Arnoldi
############################################################
puts "--- arnoldi with Nangate45 ---"
catch {set_delay_calculator arnoldi} msg
puts "set arnoldi: $msg"
report_checks
report_checks -path_delay min
report_checks -path_delay max
report_checks -fields {slew cap input_pins nets fanout}
report_checks -endpoint_count 5
# Arnoldi with varying slew
puts "--- arnoldi varying slew ---"
foreach slew_val {0.01 0.05 0.1 0.5 1.0 5.0} {
set_input_transition $slew_val [all_inputs]
report_checks
puts "arnoldi slew=$slew_val: done"
}
set_input_transition 0.1 [all_inputs]
# Arnoldi with varying loads
puts "--- arnoldi varying loads ---"
foreach load_val {0.0001 0.001 0.01 0.05 0.1} {
set_load $load_val [get_ports out1]
report_checks
puts "arnoldi load=$load_val: done"
}
set_load 0 [get_ports out1]
############################################################
# Engine switching with SPEF
############################################################
puts "--- engine switching ---"
set_delay_calculator dmp_ceff_elmore
report_checks
set_delay_calculator dmp_ceff_two_pole
report_checks
set_delay_calculator lumped_cap
report_checks
set_delay_calculator prima
report_checks
set_delay_calculator arnoldi
report_checks
############################################################
# Re-read SPEF and re-compute
############################################################
puts "--- re-read SPEF ---"
read_spef ../../search/test/search_test1.spef
set_delay_calculator prima
report_checks
set_delay_calculator arnoldi
report_checks
############################################################
# Incremental updates
############################################################
puts "--- incremental updates ---"
set_load 0.005 [get_ports out1]
report_checks
create_clock -name clk -period 5 [get_ports clk]
report_checks
set_input_transition 1.0 [all_inputs]
report_checks

16
dcalc/test/dcalc_report.tcl
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@ -1,16 +0,0 @@
# Test delay calculation
read_liberty ../../test/nangate45/Nangate45_typ.lib
read_verilog dcalc_test1.v
link_design dcalc_test1
create_clock -name clk -period 10 [get_ports clk]
set_input_delay -clock clk 0 [get_ports in1]
set_output_delay -clock clk 0 [get_ports out1]
# Force delay calculation
report_checks -from [get_ports in1] -to [get_ports out1]
# Report arrival/required
report_checks -path_delay min
report_checks -path_delay max

116
dcalc/test/dcalc_spef.tcl
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@ -1,116 +0,0 @@
# Test delay calculation with SPEF parasitics
# Exercises: GraphDelayCalc with parasitics, arnoldi delay calculator
# Read ASAP7 libraries
read_liberty ../../test/asap7/asap7sc7p5t_SEQ_RVT_FF_nldm_220123.lib
read_liberty ../../test/asap7/asap7sc7p5t_INVBUF_RVT_FF_nldm_220122.lib.gz
read_liberty ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz
read_liberty ../../test/asap7/asap7sc7p5t_OA_RVT_FF_nldm_211120.lib.gz
read_liberty ../../test/asap7/asap7sc7p5t_AO_RVT_FF_nldm_211120.lib.gz
read_verilog ../../test/reg1_asap7.v
link_design top
create_clock -name clk -period 500 {clk1 clk2 clk3}
set_input_delay -clock clk 1 {in1 in2}
set_output_delay -clock clk 1 [get_ports out]
set_input_transition 10 {in1 in2 clk1 clk2 clk3}
set_propagated_clock {clk1 clk2 clk3}
#---------------------------------------------------------------
# Read SPEF parasitics
#---------------------------------------------------------------
puts "--- Reading SPEF ---"
read_spef ../../test/reg1_asap7.spef
#---------------------------------------------------------------
# Default delay calculator (dmp_ceff_elmore) with parasitics
#---------------------------------------------------------------
puts "--- report_checks with parasitics (default dcalc) ---"
report_checks
report_checks -path_delay min
report_checks -path_delay max
report_checks -from [get_ports in1] -to [get_ports out]
report_checks -from [get_ports in2] -to [get_ports out]
# With fields for more coverage
report_checks -fields {slew cap input_pins} -format full_clock
#---------------------------------------------------------------
# report_dcalc with parasitics
#---------------------------------------------------------------
puts "--- report_dcalc with parasitics ---"
# BUF gate arc
catch {report_dcalc -from [get_pins u1/A] -to [get_pins u1/Y]} msg
puts $msg
# AND gate arc
catch {report_dcalc -from [get_pins u2/A] -to [get_pins u2/Y]} msg
puts $msg
catch {report_dcalc -from [get_pins u2/B] -to [get_pins u2/Y]} msg
puts $msg
# DFF clock-to-Q arc
catch {report_dcalc -from [get_pins r1/CLK] -to [get_pins r1/Q]} msg
puts $msg
catch {report_dcalc -from [get_pins r3/CLK] -to [get_pins r3/Q] -max} msg
puts $msg
# DFF setup/hold check arcs
catch {report_dcalc -from [get_pins r3/CLK] -to [get_pins r3/D] -max} msg
puts $msg
catch {report_dcalc -from [get_pins r3/CLK] -to [get_pins r3/D] -min} msg
puts $msg
#---------------------------------------------------------------
# Arnoldi delay calculator with parasitics
#---------------------------------------------------------------
puts "--- Testing arnoldi delay calculator ---"
catch {set_delay_calculator arnoldi} msg
puts $msg
report_checks
report_checks -path_delay min
report_checks -path_delay max
report_checks -fields {slew cap input_pins} -format full_clock
catch {report_dcalc -from [get_pins u1/A] -to [get_pins u1/Y]} msg
puts $msg
catch {report_dcalc -from [get_pins u2/A] -to [get_pins u2/Y]} msg
puts $msg
#---------------------------------------------------------------
# Lumped cap delay calculator with parasitics
#---------------------------------------------------------------
puts "--- Testing lumped_cap with parasitics ---"
catch {set_delay_calculator lumped_cap} msg
puts $msg
report_checks
catch {report_dcalc -from [get_pins u1/A] -to [get_pins u1/Y]} msg
puts $msg
#---------------------------------------------------------------
# dmp_ceff_two_pole delay calculator with parasitics
#---------------------------------------------------------------
puts "--- Testing dmp_ceff_two_pole with parasitics ---"
catch {set_delay_calculator dmp_ceff_two_pole} msg
puts $msg
report_checks
catch {report_dcalc -from [get_pins u2/A] -to [get_pins u2/Y]} msg
puts $msg

88
graph/test/CMakeLists.txt
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@ -1,78 +1,16 @@
add_test( sta_module_tests("graph"
NAME tcl.graph.make_verify TESTS
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> graph_make_verify advanced
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR} bidirect
delay_corners
delete_modify
incremental
make_verify
modify
operations
timing_edges
vertex_edge_ops
wire_inst_edges
) )
set_tests_properties(tcl.graph.make_verify PROPERTIES LABELS "tcl;module_graph")
add_test(
NAME tcl.graph.timing_edges
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> graph_timing_edges
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.graph.timing_edges PROPERTIES LABELS "tcl;module_graph")
add_test(
NAME tcl.graph.advanced
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> graph_advanced
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.graph.advanced PROPERTIES LABELS "tcl;module_graph")
add_test(
NAME tcl.graph.incremental
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> graph_incremental
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.graph.incremental PROPERTIES LABELS "tcl;module_graph")
add_test(
NAME tcl.graph.delay_corners
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> graph_delay_corners
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.graph.delay_corners PROPERTIES LABELS "tcl;module_graph")
add_test(
NAME tcl.graph.operations
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> graph_operations
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.graph.operations PROPERTIES LABELS "tcl;module_graph")
add_test(
NAME tcl.graph.modify
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> graph_modify
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.graph.modify PROPERTIES LABELS "tcl;module_graph")
add_test(
NAME tcl.graph.bidirect
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> graph_bidirect
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.graph.bidirect PROPERTIES LABELS "tcl;module_graph")
add_test(
NAME tcl.graph.wire_inst_edges
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> graph_wire_inst_edges
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.graph.wire_inst_edges PROPERTIES LABELS "tcl;module_graph")
add_test(
NAME tcl.graph.delete_modify
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> graph_delete_modify
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.graph.delete_modify PROPERTIES LABELS "tcl;module_graph")
add_test(
NAME tcl.graph.vertex_edge_ops
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> graph_vertex_edge_ops
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.graph.vertex_edge_ops PROPERTIES LABELS "tcl;module_graph")
add_subdirectory(cpp) add_subdirectory(cpp)

12
graph/test/graph_bidirect.tcl
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@ -1,17 +1,5 @@
# Test graph construction with bidirectional pins, reconvergent paths, # Test graph construction with bidirectional pins, reconvergent paths,
# and various edge/vertex operations. # and various edge/vertex operations.
# Targets: Graph.cc uncovered paths:
# makePinVertices for bidirect pins
# pinVertices for bidirect direction
# pinDrvrVertex for bidirect
# makePortInstanceEdges: bidirect from_bidirect_drvr_vertex path
# makeWireEdgesFromPin with multiple drivers
# hasFaninOne
# gateEdgeArc
# deleteVertex via delete operations
# isIsolatedNet
# vertex/edge iterators
source ../../test/helpers.tcl source ../../test/helpers.tcl
read_liberty ../../test/nangate45/Nangate45_typ.lib read_liberty ../../test/nangate45/Nangate45_typ.lib

12
graph/test/graph_vertex_edge_ops.tcl
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@ -1,18 +1,6 @@
# Test graph vertex and edge operations in depth: makeVertex, deleteVertex, # Test graph vertex and edge operations in depth: makeVertex, deleteVertex,
# makeEdge, deleteEdge, edge arc queries, bidirectional pin handling, # makeEdge, deleteEdge, edge arc queries, bidirectional pin handling,
# hasFaninOne, vertex iteration, edge linking. # hasFaninOne, vertex iteration, edge linking.
# Targets: Graph.cc uncovered:
# deleteVertex: edge cleanup during vertex deletion
# deleteInEdge / deleteOutEdge: linked list manipulation for edges
# hasFaninOne: single fanin check
# pinDrvrVertex / pinLoadVertex: bidirect driver vertex lookup
# gateEdgeArc: arc lookup by rise/fall
# makePaths / paths / deletePaths: vertex path management
# slew / setSlew: slew value access
# makeWireEdgesToPin: create wire edges to a pin
# isIsolatedNet: isolated net detection
# arcDelay / setArcDelay: edge arc delay access
source ../../test/helpers.tcl source ../../test/helpers.tcl
read_liberty ../../test/nangate45/Nangate45_typ.lib read_liberty ../../test/nangate45/Nangate45_typ.lib

248
liberty/test/CMakeLists.txt
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@ -1,218 +1,36 @@
add_test( sta_module_tests("liberty"
NAME tcl.liberty.read_sky130 TESTS
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> liberty_read_sky130 arc_model_deep
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR} busport_mem_iter
ccsn
cell_classify_pgpin
cell_deep
clkgate_lvlshift
equiv_cells
equiv_cross_lib
equiv_deep
equiv_map_libs
func_expr
leakage_power_deep
multi_corner
multi_lib_equiv
opcond_scale
pgpin_voltage
power
properties
read_asap7
read_ihp
read_nangate
read_sky130
scan_signal_types
seq_scan_bus
sky130_corners
timing_models
timing_types_deep
wireload
write_roundtrip
writer
writer_roundtrip
) )
set_tests_properties(tcl.liberty.read_sky130 PROPERTIES LABELS "tcl;module_liberty")
add_test(
NAME tcl.liberty.read_nangate
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> liberty_read_nangate
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.liberty.read_nangate PROPERTIES LABELS "tcl;module_liberty")
add_test(
NAME tcl.liberty.multi_corner
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> liberty_multi_corner
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.liberty.multi_corner PROPERTIES LABELS "tcl;module_liberty")
add_test(
NAME tcl.liberty.read_asap7
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> liberty_read_asap7
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.liberty.read_asap7 PROPERTIES LABELS "tcl;module_liberty")
add_test(
NAME tcl.liberty.read_ihp
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> liberty_read_ihp
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.liberty.read_ihp PROPERTIES LABELS "tcl;module_liberty")
add_test(
NAME tcl.liberty.equiv_cells
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> liberty_equiv_cells
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.liberty.equiv_cells PROPERTIES LABELS "tcl;module_liberty")
add_test(
NAME tcl.liberty.properties
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> liberty_properties
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.liberty.properties PROPERTIES LABELS "tcl;module_liberty")
add_test(
NAME tcl.liberty.writer
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> liberty_writer
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.liberty.writer PROPERTIES LABELS "tcl;module_liberty")
add_test(
NAME tcl.liberty.power
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> liberty_power
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.liberty.power PROPERTIES LABELS "tcl;module_liberty")
add_test(
NAME tcl.liberty.wireload
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> liberty_wireload
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.liberty.wireload PROPERTIES LABELS "tcl;module_liberty")
add_test(
NAME tcl.liberty.timing_models
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> liberty_timing_models
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.liberty.timing_models PROPERTIES LABELS "tcl;module_liberty")
add_test(
NAME tcl.liberty.func_expr
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> liberty_func_expr
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.liberty.func_expr PROPERTIES LABELS "tcl;module_liberty")
add_test(
NAME tcl.liberty.multi_lib_equiv
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> liberty_multi_lib_equiv
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.liberty.multi_lib_equiv PROPERTIES LABELS "tcl;module_liberty")
add_test(
NAME tcl.liberty.write_roundtrip
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> liberty_write_roundtrip
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.liberty.write_roundtrip PROPERTIES LABELS "tcl;module_liberty")
add_test(
NAME tcl.liberty.opcond_scale
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> liberty_opcond_scale
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.liberty.opcond_scale PROPERTIES LABELS "tcl;module_liberty")
add_test(
NAME tcl.liberty.ccsn
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> liberty_ccsn
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.liberty.ccsn PROPERTIES LABELS "tcl;module_liberty")
add_test(
NAME tcl.liberty.cell_deep
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> liberty_cell_deep
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.liberty.cell_deep PROPERTIES LABELS "tcl;module_liberty")
add_test(
NAME tcl.liberty.sky130_corners
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> liberty_sky130_corners
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.liberty.sky130_corners PROPERTIES LABELS "tcl;module_liberty")
add_test(
NAME tcl.liberty.arc_model_deep
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> liberty_arc_model_deep
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.liberty.arc_model_deep PROPERTIES LABELS "tcl;module_liberty")
add_test(
NAME tcl.liberty.writer_roundtrip2
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> liberty_writer_roundtrip
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.liberty.writer_roundtrip2 PROPERTIES LABELS "tcl;module_liberty")
add_test(
NAME tcl.liberty.equiv_deep
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> liberty_equiv_deep
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.liberty.equiv_deep PROPERTIES LABELS "tcl;module_liberty")
add_test(
NAME tcl.liberty.seq_scan_bus
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> liberty_seq_scan_bus
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.liberty.seq_scan_bus PROPERTIES LABELS "tcl;module_liberty")
add_test(
NAME tcl.liberty.clkgate_lvlshift
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> liberty_clkgate_lvlshift
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.liberty.clkgate_lvlshift PROPERTIES LABELS "tcl;module_liberty")
add_test(
NAME tcl.liberty.scan_signal_types
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> liberty_scan_signal_types
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.liberty.scan_signal_types PROPERTIES LABELS "tcl;module_liberty")
add_test(
NAME tcl.liberty.leakage_power_deep
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> liberty_leakage_power_deep
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.liberty.leakage_power_deep PROPERTIES LABELS "tcl;module_liberty")
add_test(
NAME tcl.liberty.timing_types_deep
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> liberty_timing_types_deep
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.liberty.timing_types_deep PROPERTIES LABELS "tcl;module_liberty")
add_test(
NAME tcl.liberty.pgpin_voltage
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> liberty_pgpin_voltage
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.liberty.pgpin_voltage PROPERTIES LABELS "tcl;module_liberty")
add_test(
NAME tcl.liberty.equiv_cross_lib
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> liberty_equiv_cross_lib
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.liberty.equiv_cross_lib PROPERTIES LABELS "tcl;module_liberty")
add_test(
NAME tcl.liberty.busport_mem_iter
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> liberty_busport_mem_iter
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.liberty.busport_mem_iter PROPERTIES LABELS "tcl;module_liberty")
add_test(
NAME tcl.liberty.equiv_map_libs
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> liberty_equiv_map_libs
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.liberty.equiv_map_libs PROPERTIES LABELS "tcl;module_liberty")
add_test(
NAME tcl.liberty.cell_classify_pgpin
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> liberty_cell_classify_pgpin
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.liberty.cell_classify_pgpin PROPERTIES LABELS "tcl;module_liberty")
add_subdirectory(cpp) add_subdirectory(cpp)

13
liberty/test/liberty_busport_mem_iter.tcl
View File

@ -1,18 +1,5 @@
# Test bus port member iteration, bundle ports, port functions, # Test bus port member iteration, bundle ports, port functions,
# tristate enable, sequential queries, and diverse cell classification. # tristate enable, sequential queries, and diverse cell classification.
# Targets:
# Liberty.cc: LibertyPort::isBus, isBundle, isBusBit, isBundleMember,
# hasMembers, bundlePort, findLibertyMember,
# LibertyPortMemberIterator iteration,
# LibertyCell::portCount, isBuffer, isInverter, isClockGate,
# isClockGateLatchPosedge, isMacro, isMemory, isPad, isLeaf,
# testCell, hasSequentials, timingArcSetCount, findTimingArcSet,
# area, footprint, dontUse, setDontUse,
# driveResistance, fanoutLoad, capacitanceIsOneValue
# LibertyReader.cc: bus port definitions, three_state enable parsing,
# test_cell/scan signal parsing, function/tristate_enable visitors,
# beginBusPort, endBusPort
# LibertyBuilder.cc: cell construction for bus/tristate/sequential
source ../../test/helpers.tcl source ../../test/helpers.tcl
############################################################ ############################################################

98
liberty/test/liberty_ccsn_ecsm.ok
View File

@ -1,98 +0,0 @@
Cell A2O1A1Ixp33_ASAP7_75t_L
Library asap7sc7p5t_AO_LVT_FF_ccsn_211120
File ../../test/asap7_ccsn.lib.gz
VDD power
VSS ground
Y output function=((!A1*!B)+(!A2*!B))+!C
A1 input 0.49-0.63
A2 input 0.53-0.63
B input 0.47-0.66
C input 0.36-0.63
Cell DFFHQNx1_ASAP7_75t_R
Library asap7sc7p5t_SEQ_RVT_FF_nldm_220123
File ../../test/asap7/asap7sc7p5t_SEQ_RVT_FF_nldm_220123.lib
VDD power
VSS ground
QN output function=IQN
CLK input 0.40-0.52
D input 0.55-0.62
IQN internal
IQNN internal
Cell DFFHQNx2_ASAP7_75t_R
Library asap7sc7p5t_SEQ_RVT_FF_nldm_220123
File ../../test/asap7/asap7sc7p5t_SEQ_RVT_FF_nldm_220123.lib
VDD power
VSS ground
QN output function=IQN
CLK input 0.40-0.52
D input 0.55-0.62
IQN internal
IQNN internal
Warning: liberty_ccsn_ecsm.tcl line 1, liberty cell 'asap7sc7p5t_SEQ_RVT_FF_nldm_220123/SDFHQNx1_ASAP7_75t_R' not found.
Warning: liberty_ccsn_ecsm.tcl line 1, liberty cell 'asap7sc7p5t_SEQ_RVT_FF_nldm_220123/SDFHQNx2_ASAP7_75t_R' not found.
Cell ICGx1_ASAP7_75t_R
Library asap7sc7p5t_SEQ_RVT_FF_nldm_220123
File ../../test/asap7/asap7sc7p5t_SEQ_RVT_FF_nldm_220123.lib
VDD power
VSS ground
IQ internal
GCLK output
CLK input 1.63-2.39
ENA input 0.33-0.47
SE input 0.39-0.47
Cell ICGx2_ASAP7_75t_R
Library asap7sc7p5t_SEQ_RVT_FF_nldm_220123
File ../../test/asap7/asap7sc7p5t_SEQ_RVT_FF_nldm_220123.lib
VDD power
VSS ground
IQ internal
GCLK output
CLK input 1.63-2.39
ENA input 0.33-0.47
SE input 0.39-0.47
Warning: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 13178, timing group from output port.
Warning: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 13211, timing group from output port.
Warning: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 13244, timing group from output port.
Warning: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 13277, timing group from output port.
Warning: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 13310, timing group from output port.
Warning: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 13343, timing group from output port.
Warning: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 13376, timing group from output port.
Warning: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 14772, timing group from output port.
Warning: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 14805, timing group from output port.
Warning: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 14838, timing group from output port.
Cell sg13g2_ebufn_2
Library sg13g2_stdcell_typ_1p20V_25C
File ../../test/ihp-sg13g2/sg13g2_stdcell_typ_1p20V_25C.lib
Z tristate enable=!TE_B function=A 4.51-7.42
A input 2.58-2.66
TE_B input 6.21-6.60
Cell sg13g2_sdfbbp_1
Library sg13g2_stdcell_typ_1p20V_25C
File ../../test/ihp-sg13g2/sg13g2_stdcell_typ_1p20V_25C.lib
Q output function=IQ
Q_N output function=IQN
CLK input 2.97-3.06
D input 1.95-2.01
RESET_B input 1.74
SCD input 1.96-2.00
SCE input 3.18-3.92
SET_B input 5.25
IQ internal
IQN internal
Cell sg13g2_dlhq_1
Library sg13g2_stdcell_typ_1p20V_25C
File ../../test/ihp-sg13g2/sg13g2_stdcell_typ_1p20V_25C.lib
Q output function=IQ
D input 2.26-2.31
GATE input 1.69-2.58
IQ internal
IQN internal
Cell sg13g2_mux2_1
Library sg13g2_stdcell_typ_1p20V_25C
File ../../test/ihp-sg13g2/sg13g2_stdcell_typ_1p20V_25C.lib
X output function=(!S*A0)+(S*A1)
A0 input 0.38-3.63
A1 input 0.52-3.70
S input 5.00-5.09
Warning: ../../test/liberty_arcs_one2one_1.lib line 48, timing port A and related port Y are different sizes.
Warning: ../../test/liberty_arcs_one2one_2.lib line 48, timing port A and related port Y are different sizes.

202
liberty/test/liberty_ccsn_ecsm.tcl
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@ -1,202 +0,0 @@
# Test CCSN (current source) models and various timing model types.
# Targets:
# LibertyReader.cc: beginCcs/endCcs, receiver_capacitance groups,
# ECSM waveform handling, timing_type combinations,
# beginOutputCurrentRise/Fall, visitReceiverCapacitance,
# polynomial model visitors, ccsn noise model visitors,
# leakage_power groups, internal_power groups,
# max_capacitance/max_transition on pins, min_pulse_width
# TableModel.cc: different table axis variables, GateTableModel,
# CheckTableModel, 3D tables, receiver model tables
# TimingArc.cc: timing arc type queries (removal, recovery,
# three_state_enable, rising_edge, min_pulse_width)
# Liberty.cc: timing arc set queries, hasTimingArcs, timingArcSets
source ../../test/helpers.tcl
############################################################
# Read ASAP7 CCSN library (CCS models with receiver_capacitance)
############################################################
read_liberty ../../test/asap7_ccsn.lib.gz
# Report cells from CCSN library to exercise CCS model paths
set ccsn_cells [get_lib_cells */*]
foreach cell_obj $ccsn_cells {
catch {
report_lib_cell [get_full_name $cell_obj]
}
}
############################################################
# Read ASAP7 SEQ library (has setup/hold/recovery/removal arcs)
############################################################
read_liberty ../../test/asap7/asap7sc7p5t_SEQ_RVT_FF_nldm_220123.lib
# Report sequential cells which have diverse timing_type values
# DFF cells have setup, hold timing checks
set lib_seq [sta::find_liberty asap7sc7p5t_SEQ_RVT_FF_nldm_220123]
catch {
set seq_cells [$lib_seq find_liberty_cells_matching "DFF*" 0 0]
}
# Report specific cells to exercise different timing types
catch {
report_lib_cell asap7sc7p5t_SEQ_RVT_FF_nldm_220123/DFFHQNx1_ASAP7_75t_R
}
catch {
report_lib_cell asap7sc7p5t_SEQ_RVT_FF_nldm_220123/DFFHQNx2_ASAP7_75t_R
}
# Scan DFF cells (scan_in, scan_enable timing arcs)
catch {
report_lib_cell asap7sc7p5t_SEQ_RVT_FF_nldm_220123/SDFHQNx1_ASAP7_75t_R
}
catch {
report_lib_cell asap7sc7p5t_SEQ_RVT_FF_nldm_220123/SDFHQNx2_ASAP7_75t_R
}
# ICG cells (clock gating - exercises clock gate timing types)
catch {
report_lib_cell asap7sc7p5t_SEQ_RVT_FF_nldm_220123/ICGx1_ASAP7_75t_R
}
catch {
report_lib_cell asap7sc7p5t_SEQ_RVT_FF_nldm_220123/ICGx2_ASAP7_75t_R
}
# Async set/reset cells (recovery/removal timing types)
catch {
set async_cells [$lib_seq find_liberty_cells_matching "*ASYNC*" 0 0]
}
# DFFR cells with reset (recovery/removal)
catch {
set dffr_cells [$lib_seq find_liberty_cells_matching "DFFR*" 0 0]
foreach cell_obj $dffr_cells {
report_lib_cell [get_object_name $cell_obj]
}
}
############################################################
# Read ASAP7 SEQ SS corner for different model values
############################################################
read_liberty ../../test/asap7/asap7sc7p5t_SEQ_RVT_SS_nldm_220123.lib
############################################################
# Read ASAP7 SIMPLE library (combinational cells)
############################################################
read_liberty ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz
catch {
set simple_lib [sta::find_liberty asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120]
set simple_cells [$simple_lib find_liberty_cells_matching "*" 0 0]
}
############################################################
# Read ASAP7 AO library (AND-OR complex cells)
############################################################
read_liberty ../../test/asap7/asap7sc7p5t_AO_RVT_FF_nldm_211120.lib.gz
catch {
set ao_lib [sta::find_liberty asap7sc7p5t_AO_RVT_FF_nldm_211120]
set ao_cells [$ao_lib find_liberty_cells_matching "AO*" 0 0]
foreach c $ao_cells {
catch {report_lib_cell [get_object_name $c]}
}
}
############################################################
# Read ASAP7 OA library (OR-AND complex cells)
############################################################
read_liberty ../../test/asap7/asap7sc7p5t_OA_RVT_FF_nldm_211120.lib.gz
catch {
set oa_lib [sta::find_liberty asap7sc7p5t_OA_RVT_FF_nldm_211120]
set oa_cells [$oa_lib find_liberty_cells_matching "OA*" 0 0]
foreach c $oa_cells {
catch {report_lib_cell [get_object_name $c]}
}
}
############################################################
# Read ASAP7 INVBUF library
############################################################
read_liberty ../../test/asap7/asap7sc7p5t_INVBUF_RVT_FF_nldm_220122.lib.gz
############################################################
# Read libraries from different process nodes
# Exercises different liberty features/syntax in each library
############################################################
# Read IHP SG13G2 library (has tristate, scan, different timing types)
read_liberty ../../test/ihp-sg13g2/sg13g2_stdcell_typ_1p20V_25C.lib
catch {
set ihp_lib [sta::find_liberty sg13g2_stdcell_typ_1p20V_25C]
# Report tristate buffer cell (exercises three_state_enable paths)
catch {report_lib_cell sg13g2_stdcell_typ_1p20V_25C/sg13g2_ebufn_2}
# Report scan flip-flop (exercises scan timing paths)
catch {report_lib_cell sg13g2_stdcell_typ_1p20V_25C/sg13g2_sdfbbp_1}
# Report latch cell
catch {report_lib_cell sg13g2_stdcell_typ_1p20V_25C/sg13g2_dlhq_1}
# MUX cell
catch {report_lib_cell sg13g2_stdcell_typ_1p20V_25C/sg13g2_mux2_1}
}
# Read IHP second PVT corner
read_liberty ../../test/ihp-sg13g2/sg13g2_stdcell_typ_1p50V_25C.lib
############################################################
# Read latch library to exercise latch-specific code
############################################################
read_liberty ../../test/liberty_latch3.lib
############################################################
# Read liberty with backslash-EOL continuation
############################################################
read_liberty ../../test/liberty_backslash_eol.lib
############################################################
# Read liberty with float-as-string values
############################################################
read_liberty ../../test/liberty_float_as_str.lib
############################################################
# Read liberty arcs one2one libraries
############################################################
read_liberty ../../test/liberty_arcs_one2one_1.lib
read_liberty ../../test/liberty_arcs_one2one_2.lib
############################################################
# Read SRAM macro library (exercises macro/memory cells)
############################################################
read_liberty ../../test/gf180mcu_sram.lib.gz
############################################################
# Read ASAP7 SEQ LVT/SLVT (different threshold voltages)
############################################################
read_liberty ../../test/asap7/asap7sc7p5t_SEQ_LVT_FF_nldm_220123.lib
read_liberty ../../test/asap7/asap7sc7p5t_SEQ_SLVT_FF_nldm_220123.lib
############################################################
# Read ASAP7 INVBUF different Vt flavors
############################################################
read_liberty ../../test/asap7/asap7sc7p5t_INVBUF_LVT_FF_nldm_220122.lib.gz
read_liberty ../../test/asap7/asap7sc7p5t_INVBUF_SLVT_FF_nldm_220122.lib.gz
############################################################
# Write liberty for ASAP7 SEQ
############################################################
set outfile [make_result_file liberty_ccsn_ecsm_write.lib]
sta::write_liberty asap7sc7p5t_SEQ_RVT_FF_nldm_220123 $outfile
set outfile2 [make_result_file liberty_ccsn_ecsm_write_ihp.lib]
sta::write_liberty sg13g2_stdcell_typ_1p20V_25C $outfile2

13
liberty/test/liberty_cell_classify_pgpin.tcl
View File

@ -1,19 +1,6 @@
# Test cell classification (isBuffer, isInverter, isClockGate, etc.), # Test cell classification (isBuffer, isInverter, isClockGate, etc.),
# pg_pin iteration, bus port member iteration, internal power queries, # pg_pin iteration, bus port member iteration, internal power queries,
# and port function queries across multiple PDKs. # and port function queries across multiple PDKs.
# Targets:
# Liberty.cc: LibertyCell isBuffer, isInverter, isClockGate,
# isClockGateLatchPosedge, isClockGateLatchNegedge, isMacro, isPad,
# isMemory, hasInternalPower, internalPowers, addInternalPower,
# leakagePower, leakagePowers, cellPortBitCount, busPorts,
# isDisabledConstraint, pgPins, testCell, setDontUse, dontUse,
# LibertyPort isBus, isBusBit, isBundle, hasMembers, bundlePort,
# LibertyPortMemberIterator, findLibertyMember,
# LibertyLibrary findOperatingConditions, defaultOperatingConditions,
# supplyExists, findWireload, findWireloadSelection
# FuncExpr.cc: to_string, portTimingSense
# InternalPower.cc: InternalPower accessors
# LeakagePower.cc: LeakagePower accessors
source ../../test/helpers.tcl source ../../test/helpers.tcl
############################################################ ############################################################

14
liberty/test/liberty_cell_deep.tcl
View File

@ -1,19 +1,5 @@
# Deep cell property queries: timing arc traversal, port capacitance, # Deep cell property queries: timing arc traversal, port capacitance,
# sequential elements, leakage/internal power, and cell classification. # sequential elements, leakage/internal power, and cell classification.
# Targets:
# Liberty.cc: hasTimingArcs, timingArcSets (from, to, from+to),
# outputPortSequential, hasSequentials, makeTimingArcMap,
# findDefaultCondArcs, translatePresetClrCheckRoles,
# addInternalPower, internalPowers, addLeakagePower, leakagePower,
# LibertyPort capacitance, driveResistance, fanoutLoad,
# minPulseWidth, setFunction, tristateEnable,
# isClockGate, isClockGateLatchPosedge, isMacro, isMemory, isPad,
# LibertyCell area, footprint, setDontUse, dontUse,
# LibertyPortMemberIterator, bundlePort, findLibertyMember
# TimingArc.cc: TimingArcSet role, sense, cond, timingType,
# fromEdge, toEdge, arcCount, TimingArc equiv, isRisingFallingEdge
# LibertyBuilder.cc: build different cell structures (tri-state, scan)
# FuncExpr.cc: portTimingSense, hasPort, equiv, bitSubExpr
source ../../test/helpers.tcl source ../../test/helpers.tcl
############################################################ ############################################################

11
liberty/test/liberty_clkgate_lvlshift.tcl
View File

@ -1,16 +1,5 @@
# Test clock gating cells, level shifter cells, pg_pin attributes, # Test clock gating cells, level shifter cells, pg_pin attributes,
# voltage_map/supply_voltage queries, and related cell classification. # voltage_map/supply_voltage queries, and related cell classification.
# Targets:
# LibertyReader.cc: visitClockGatingIntegratedCell (latch_posedge,
# latch_posedge_precontrol), visitIsLevelShifter, visitLevelShifterType,
# visitLevelShifterDataPin, beginPgPin, endPgPin, visitPgType,
# visitVoltageName, visitVoltageMap, visitRelatedBiasPin,
# visitClockGateClockPin, visitClockGateEnablePin, visitClockGateOutPin,
# visitInputVoltageRange, visitOutputVoltageRange
# Liberty.cc: isClockGate, isClockGateLatchPosedge, isClockGateLatchNegedge,
# isClockGateOther, isLevelShifter, addSupplyVoltage, supplyVoltage,
# supplyExists, LibertyPort::isPwrGnd
# LibertyBuilder.cc: clock gate cell construction
source ../../test/helpers.tcl source ../../test/helpers.tcl
############################################################ ############################################################

9
liberty/test/liberty_equiv_cross_lib.tcl
View File

@ -1,14 +1,5 @@
# Test equivalent cells across multiple libraries from different PDKs, # Test equivalent cells across multiple libraries from different PDKs,
# exercising mapEquivCells and cross-library equivalence hashing. # exercising mapEquivCells and cross-library equivalence hashing.
# Targets:
# EquivCells.cc: EquivCells constructor with map_libs (mapEquivCells),
# findEquivCells, hashCell, hashCellPorts, hashCellSequentials,
# hashSequential, hashFuncExpr, hashPort, hashStatetable,
# hashStatetableRow, equivCells, equivCellPorts, equivCellFuncs,
# equivCellSequentials, equivCellStatetables, equivCellTimingArcSets,
# equivCellsArcs, cellHasFuncs, cellDriveResistance,
# CellDriveResistanceGreater
# Liberty.cc: buffers(), portCount, findLibertyPort, driveResistance
source ../../test/helpers.tcl source ../../test/helpers.tcl
############################################################ ############################################################

12
liberty/test/liberty_leakage_power_deep.tcl
View File

@ -1,17 +1,5 @@
# Test deep leakage power groups with when conditions, internal power # Test deep leakage power groups with when conditions, internal power
# with related_pg_pin, and power attribute parsing across PDKs. # with related_pg_pin, and power attribute parsing across PDKs.
# Targets:
# LibertyReader.cc: beginLeakagePower, endLeakagePower, makeLeakagePowers,
# visitLeakagePowerValue, visitLeakagePowerWhen, visitRelatedPgPin,
# beginInternalPower, endInternalPower, visitCellLeakagePower,
# visitPowerUnit, beginPgPin, endPgPin, visitPgType, visitVoltageName,
# visitWhen (power context), visitRelatedBiasPin
# LeakagePower.cc: LeakagePower construction, LeakagePowerGroup,
# setRelatedPgPin, when condition parsing
# InternalPower.cc: InternalPowerAttrs, setRelatedPgPin,
# InternalPower construction
# Liberty.cc: addLeakagePower, leakagePower, addInternalPower,
# internalPowers, hasInternalPower
source ../../test/helpers.tcl source ../../test/helpers.tcl
############################################################ ############################################################

13
liberty/test/liberty_pgpin_voltage.tcl
View File

@ -1,17 +1,4 @@
# Test pg_pin, voltage_map, supply voltage, and power group parsing. # Test pg_pin, voltage_map, supply voltage, and power group parsing.
# Targets:
# LibertyReader.cc: beginPgPin, endPgPin, visitPgType, visitVoltageName,
# visitVoltageMap, visitRelatedPgPin, visitRelatedBiasPin,
# visitCellLeakagePower, beginLeakagePower, endLeakagePower,
# visitLeakagePowerValue, visitLeakagePowerWhen,
# beginInternalPower, endInternalPower (power with when conditions),
# visitPowerUnit, beginOperatingConditions, endOperatingConditions,
# visitProcessScaleFactor, visitVoltScaleFactor, visitTempScaleFactor,
# liberty_supply_exists
# Liberty.cc: LibertyCell::pgPorts, LibertyPort::isPwrGnd,
# addLeakagePower, leakagePower, internalPowers, hasInternalPower,
# supplyExists, supplyVoltage
# InternalPower.cc: InternalPowerAttrs, setRelatedPgPin
source ../../test/helpers.tcl source ../../test/helpers.tcl
############################################################ ############################################################

2
liberty/test/liberty_power.tcl
View File

@ -1,6 +1,4 @@
# Test internal power, leakage power, and power reporting for code coverage # Test internal power, leakage power, and power reporting for code coverage
# Targets: InternalPower.cc, LeakagePower.cc, Liberty.cc (power paths),
# LibertyReader.cc (power group parsing), LibertyWriter.cc (power writing)
source ../../test/helpers.tcl source ../../test/helpers.tcl
############################################################ ############################################################

9
liberty/test/liberty_scan_signal_types.tcl
View File

@ -1,14 +1,5 @@
# Test scan signal_type parsing, test_cell construction, and # Test scan signal_type parsing, test_cell construction, and
# scan-related port attributes across multiple PDKs. # scan-related port attributes across multiple PDKs.
# Targets:
# LibertyReader.cc: visitSignalType (test_scan_enable, test_scan_in,
# test_scan_out, test_scan_clock), beginTestCell, endTestCell,
# test_cell pin parsing, signal_type enumeration paths,
# scan-related sequential construction
# Liberty.cc: LibertyCell::testCell, LibertyPort::setScanSignalType,
# scanSignalType, scanSignalTypeName,
# LibertyPort::function, tristateEnable
# LibertyBuilder.cc: test_cell cell build
source ../../test/helpers.tcl source ../../test/helpers.tcl
############################################################ ############################################################

17
liberty/test/liberty_seq_scan_bus.tcl
View File

@ -1,23 +1,6 @@
# Test liberty reading and querying of sequential cells (latch, ff, statetable), # Test liberty reading and querying of sequential cells (latch, ff, statetable),
# test_cell/scan definitions, bus/bundle ports, tristate outputs, # test_cell/scan definitions, bus/bundle ports, tristate outputs,
# internal power, and scaled cells through multi-corner. # internal power, and scaled cells through multi-corner.
# Targets:
# Liberty.cc: makeScaledCell, makeCornerMap, scalePorts,
# LibertyCell::makeSequential (ff, latch), hasSequentials,
# outputPortSequential, setTestCell, testCell,
# addInternalPower, internalPowers, hasInternalPower,
# LibertyPort::tristateEnable, setTristateEnable,
# LibertyPort::bundlePort, findLibertyMember, isBus, isBundle,
# LibertyPort::capacitanceIsOneValue, driveResistance,
# LibertyPort::fanoutLoad, setFanoutLoad,
# LibertyCell::isBuffer, isInverter, isClockGate,
# LibertyCell::area, footprint, setDontUse, dontUse,
# makeTimingArcMap, findDefaultCondArcs
# LibertyReader.cc: sequential cell attributes (latch, ff, statetable),
# test_cell/scan signal parsing, bus port definitions,
# three_state enable parsing, internal_power group,
# operating conditions, scaling factors
# LibertyBuilder.cc: cell construction for scan/tristate/sequential
source ../../test/helpers.tcl source ../../test/helpers.tcl
############################################################ ############################################################

10
liberty/test/liberty_sky130_corners.tcl
View File

@ -1,14 +1,4 @@
# Test multi-corner library reading and Sky130HS features. # Test multi-corner library reading and Sky130HS features.
# Targets:
# LibertyReader.cc: different lib format features per PDK,
# define_cell_area, leakage_power parsing, internal_power parsing,
# max_capacitance/max_transition on pins, pg_pin groups,
# voltage_map parsing, various attribute visitors
# Liberty.cc: makeCornerMap, checkCorners, LibertyPort driveResistance,
# maxCapacitance, maxFanout, maxSlew on ports,
# bufferPorts, addSupplyVoltage, supplyVoltage
# LibertyWriter.cc: write different lib formats
# TableModel.cc: table lookup, axis variable handling
source ../../test/helpers.tcl source ../../test/helpers.tcl
############################################################ ############################################################

13
liberty/test/liberty_timing_types_deep.tcl
View File

@ -1,17 +1,4 @@
# Deep timing type and timing arc attribute testing across diverse PDKs. # Deep timing type and timing arc attribute testing across diverse PDKs.
# Targets:
# LibertyReader.cc: timing_type attribute handler (clear, preset,
# recovery_rising, recovery_falling, removal_rising, removal_falling,
# min_pulse_width, min_period, three_state_enable,
# three_state_disable, rising_edge, falling_edge, preset, clear,
# hold_rising, hold_falling, setup_rising, setup_falling,
# clock_gating_setup, clock_gating_hold),
# visitClear, visitPreset, visitClrPresetVar1, visitClrPresetVar2,
# visitMinPeriod, visitMinPulseWidthLow, visitMinPulseWidthHigh,
# beginPgPin, endPgPin, visitVoltageMap
# Liberty.cc: timingArcSets traversal, timing type query, hasSequentials,
# translatePresetClrCheckRoles
# TimingArc.cc: TimingArcSet::role, timingType, full_name
source ../../test/helpers.tcl source ../../test/helpers.tcl
############################################################ ############################################################

3
liberty/test/liberty_wireload.tcl
View File

@ -1,7 +1,4 @@
# Test wire load model handling for code coverage # Test wire load model handling for code coverage
# Targets: Wireload.cc (WireloadSelection, wireloadTreeString, wireloadModeString),
# LibertyReader.cc (wireload parsing), Liberty.cc (wireload queries),
# LibertyWriter.cc (wireload writing)
source ../../test/helpers.tcl source ../../test/helpers.tcl
############################################################ ############################################################

11
liberty/test/liberty_writer_roundtrip.tcl
View File

@ -1,13 +1,4 @@
# Deep write_liberty test exercising all LibertyWriter.cc paths: # Deep write_liberty test exercising all LibertyWriter.cc paths.
# writeHeader, writeTableTemplates, writeTableTemplate, writeBusDcls,
# writeCells, writeCell, writePort, writeBusPort, writePwrGndPort,
# writePortAttrs, writeTimingArcSet, writeTimingModels,
# writeTableModel (0/1/2 axis), writeTableAxis4/10,
# timingTypeString (combinational, rising_edge, falling_edge,
# setup_rising, setup_falling, hold_rising, hold_falling,
# three_state_enable, three_state_disable, preset, clear,
# min_pulse_width, min_clock_tree_path, max_clock_tree_path),
# asString for PortDirection, isAutoWidthArc
source ../../test/helpers.tcl source ../../test/helpers.tcl
############################################################ ############################################################

208
network/test/CMakeLists.txt
View File

@ -1,183 +1,31 @@
add_test( sta_module_tests("network"
NAME tcl.network.query TESTS
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> network_query advanced
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR} bus_parse
cell_match_merge
connect_liberty
connected_pins
deep_modify
escaped_names
fanin_fanout
find_cells_regex
gcd_traversal
hier_pin_query
hierarchy
leaf_iter
merge_bus_hier
modify
multi_lib
namespace_escape
net_cap_query
pattern_match
properties
query
sdc_adapt_deep
sdc_pattern_deep
sdc_query
sorting
traversal
) )
set_tests_properties(tcl.network.query PROPERTIES LABELS "tcl;module_network")
add_test(
NAME tcl.network.traversal
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> network_traversal
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.network.traversal PROPERTIES LABELS "tcl;module_network")
add_test(
NAME tcl.network.modify
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> network_modify
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.network.modify PROPERTIES LABELS "tcl;module_network")
add_test(
NAME tcl.network.advanced
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> network_advanced
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.network.advanced PROPERTIES LABELS "tcl;module_network")
add_test(
NAME tcl.network.properties
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> network_properties
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.network.properties PROPERTIES LABELS "tcl;module_network")
add_test(
NAME tcl.network.connect_liberty
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> network_connect_liberty
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.network.connect_liberty PROPERTIES LABELS "tcl;module_network")
add_test(
NAME tcl.network.bus_parse
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> network_bus_parse
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.network.bus_parse PROPERTIES LABELS "tcl;module_network")
add_test(
NAME tcl.network.pattern_match
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> network_pattern_match
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.network.pattern_match PROPERTIES LABELS "tcl;module_network")
add_test(
NAME tcl.network.sorting
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> network_sorting
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.network.sorting PROPERTIES LABELS "tcl;module_network")
add_test(
NAME tcl.network.hierarchy
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> network_hierarchy
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.network.hierarchy PROPERTIES LABELS "tcl;module_network")
add_test(
NAME tcl.network.sdc_query
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> network_sdc_query
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.network.sdc_query PROPERTIES LABELS "tcl;module_network")
add_test(
NAME tcl.network.deep_modify
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> network_deep_modify
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.network.deep_modify PROPERTIES LABELS "tcl;module_network")
add_test(
NAME tcl.network.leaf_iter
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> network_leaf_iter
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.network.leaf_iter PROPERTIES LABELS "tcl;module_network")
add_test(
NAME tcl.network.escaped_names
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> network_escaped_names
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.network.escaped_names PROPERTIES LABELS "tcl;module_network")
add_test(
NAME tcl.network.multi_lib
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> network_multi_lib
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.network.multi_lib PROPERTIES LABELS "tcl;module_network")
add_test(
NAME tcl.network.namespace_escape
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> network_namespace_escape
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.network.namespace_escape PROPERTIES LABELS "tcl;module_network")
add_test(
NAME tcl.network.net_cap_query
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> network_net_cap_query
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.network.net_cap_query PROPERTIES LABELS "tcl;module_network")
add_test(
NAME tcl.network.fanin_fanout
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> network_fanin_fanout
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.network.fanin_fanout PROPERTIES LABELS "tcl;module_network")
add_test(
NAME tcl.network.connected_pins
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> network_connected_pins
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.network.connected_pins PROPERTIES LABELS "tcl;module_network")
add_test(
NAME tcl.network.hier_pin_query
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> network_hier_pin_query
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.network.hier_pin_query PROPERTIES LABELS "tcl;module_network")
add_test(
NAME tcl.network.cell_match_merge
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> network_cell_match_merge
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.network.cell_match_merge PROPERTIES LABELS "tcl;module_network")
add_test(
NAME tcl.network.sdc_adapt_deep
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> network_sdc_adapt_deep
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.network.sdc_adapt_deep PROPERTIES LABELS "tcl;module_network")
add_test(
NAME tcl.network.merge_bus_hier
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> network_merge_bus_hier
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.network.merge_bus_hier PROPERTIES LABELS "tcl;module_network")
add_test(
NAME tcl.network.sdc_pattern_deep
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> network_sdc_pattern_deep
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.network.sdc_pattern_deep PROPERTIES LABELS "tcl;module_network")
add_test(
NAME tcl.network.gcd_traversal
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> network_gcd_traversal
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.network.gcd_traversal PROPERTIES LABELS "tcl;module_network")
add_test(
NAME tcl.network.find_cells_regex
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> network_find_cells_regex
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.network.find_cells_regex PROPERTIES LABELS "tcl;module_network")
add_subdirectory(cpp) add_subdirectory(cpp)

5
network/test/network_advanced.tcl
View File

@ -1,9 +1,4 @@
# Test advanced network operations for coverage improvement # Test advanced network operations for coverage improvement
# Targets: Network.cc uncovered functions (instanceCount, pinCount, netCount,
# leafInstanceCount, leafPinCount, leafInstances, setPathDivider, setPathEscape,
# findNet, findPin, pathNameTerm, checkLibertyCells, connectedNets, isInside, etc.)
# Also targets: NetworkCmp.cc (sortByPathName for instances/nets), PortDirection.cc
read_liberty ../../test/nangate45/Nangate45_typ.lib read_liberty ../../test/nangate45/Nangate45_typ.lib
read_verilog network_test1.v read_verilog network_test1.v
link_design network_test1 link_design network_test1

9
network/test/network_connect_liberty.tcl
View File

@ -1,13 +1,4 @@
# Test network modify operations using liberty cell references # Test network modify operations using liberty cell references
# Targets: ConcreteNetwork.cc uncovered functions:
# - connect(Instance, LibertyPort, Net) - line 1367 hit=0
# - mergeInto(Net, Net) - line 1203 hit=0
# - addConstantNet - line 1541 hit=0
# - clearConstantNets - line 1534 hit=0
# - clear - line 273 hit=0
# Also tests: Network.cc (findInstancesMatching, findNetsMatchingLinear,
# findPinsMatching, leafInstanceIterator(inst), etc.)
read_liberty ../../test/nangate45/Nangate45_typ.lib read_liberty ../../test/nangate45/Nangate45_typ.lib
read_verilog network_test1.v read_verilog network_test1.v
link_design network_test1 link_design network_test1

16
network/test/network_pattern_match.tcl
View File

@ -1,20 +1,4 @@
# Test pattern matching functions for coverage improvement # Test pattern matching functions for coverage improvement
# Targets: Network.cc uncovered functions:
# findNetsMatching (line 914, hit=0), findNetsMatchingLinear (line 977, hit=0),
# findPinsMatching (line 992, hit=0), findInstPinsMatching (line 1066, hit=0),
# findInstancesMatching (line 724, hit=0), findInstancesMatching1 (line 744, hit=0),
# findNetLinear (line 898, hit=0), findPinLinear (line 839, hit=0),
# connectedNets(Pin) (line 580, hit=0),
# pathNameLess(Instance) (line 287, hit=0), pathNameLess(Net) (line 486, hit=0),
# pathNameCmp(Net) (line 493, hit=0),
# isInside(Instance) (line 344, hit=0), isInside(Net) (line 416, hit=0),
# isInside(Pin, Instance) (line 448, hit=0), isInside(Pin, Pin) (line 441, hit=0),
# instanceCount (line 1098, 1111, hit=0), pinCount (line 1117, 1137, hit=0),
# netCount (line 1143, 1163, hit=0), leafInstanceCount (line 1169, hit=0),
# leafPinCount (line 1182, hit=0)
# Also targets: SdcNetwork.cc (findNet, busName)
# NetworkCmp.cc (InstancePathNameLess, NetPathNameLess, sortByPathName for Instances/Nets)
read_liberty ../../test/nangate45/Nangate45_typ.lib read_liberty ../../test/nangate45/Nangate45_typ.lib
read_verilog network_test1.v read_verilog network_test1.v
link_design network_test1 link_design network_test1

6
network/test/network_properties.tcl
View File

@ -1,10 +1,4 @@
# Test network property queries and edge cases for coverage improvement # Test network property queries and edge cases for coverage improvement
# Targets: ConcreteNetwork.cc (getAttribute, attributeMap, bus ports, cell properties,
# id, groupBusPorts, isBundle, portBitCount, fromIndex/toIndex, filename, setName, etc.)
# Targets: Network.cc (instanceCount, pinCount, netCount, leafInstanceCount,
# leafPinCount, connectedNets, isInside, pathNameNet, pathNameTerm, etc.)
# Targets: SdcNetwork.cc (findNet, busName, various uncovered adapter functions)
#--------------------------------------------------------------- #---------------------------------------------------------------
# Use ASAP7 design which has bus ports for bus coverage # Use ASAP7 design which has bus ports for bus coverage
#--------------------------------------------------------------- #---------------------------------------------------------------

13
network/test/network_sorting.tcl
View File

@ -1,17 +1,4 @@
# Test network comparison and sorting operations # Test network comparison and sorting operations
# Targets: NetworkCmp.cc uncovered functions:
# InstancePathNameLess (line 71-81, hit=0)
# NetPathNameLess::operator() (line 65-68, hit=0)
# PortNameLess::operator() (line 41-44, hit=0)
# sortByPathName(InstanceSet) (line 108-116, hit=0)
# sortByPathName(NetSet) (line 119-127, hit=0)
# Also targets: Network.cc
# pathNameLess(Instance) (line 287, hit=0), pathNameCmp(Instance) (line 294)
# pathNameLess(Net) (line 486, hit=0), pathNameCmp(Net) (line 493, hit=0)
# instanceCount, pinCount, netCount, leafInstanceCount, leafPinCount
# setPathDivider (line 1213, hit=0), setPathEscape (line 1219, hit=0)
# leafInstanceIterator(Instance) (line 1297, hit=0)
read_liberty ../../test/nangate45/Nangate45_typ.lib read_liberty ../../test/nangate45/Nangate45_typ.lib
read_verilog network_test1.v read_verilog network_test1.v
link_design network_test1 link_design network_test1

136
parasitics/test/CMakeLists.txt
View File

@ -1,120 +1,22 @@
add_test( sta_module_tests("parasitics"
NAME tcl.parasitics.spef TESTS
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> parasitics_spef annotation_query
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR} corners
coupling
coupling_reduce
delete_network
detailed
estimate_wirerc
gcd_reduce
gcd_spef
manual
pi_pole_residue
reduce
reduce_dcalc
spef
spef_formats
spef_namemap
wireload
) )
set_tests_properties(tcl.parasitics.spef PROPERTIES LABELS "tcl;module_parasitics")
add_test(
NAME tcl.parasitics.detailed
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> parasitics_detailed
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.parasitics.detailed PROPERTIES LABELS "tcl;module_parasitics")
add_test(
NAME tcl.parasitics.corners
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> parasitics_corners
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.parasitics.corners PROPERTIES LABELS "tcl;module_parasitics")
add_test(
NAME tcl.parasitics.manual
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> parasitics_manual
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.parasitics.manual PROPERTIES LABELS "tcl;module_parasitics")
add_test(
NAME tcl.parasitics.reduce
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> parasitics_reduce
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.parasitics.reduce PROPERTIES LABELS "tcl;module_parasitics")
add_test(
NAME tcl.parasitics.spef_namemap
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> parasitics_spef_namemap
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.parasitics.spef_namemap PROPERTIES LABELS "tcl;module_parasitics")
add_test(
NAME tcl.parasitics.coupling
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> parasitics_coupling
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.parasitics.coupling PROPERTIES LABELS "tcl;module_parasitics")
add_test(
NAME tcl.parasitics.reduce_dcalc
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> parasitics_reduce_dcalc
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.parasitics.reduce_dcalc PROPERTIES LABELS "tcl;module_parasitics")
add_test(
NAME tcl.parasitics.estimate_wirerc
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> parasitics_estimate_wirerc
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.parasitics.estimate_wirerc PROPERTIES LABELS "tcl;module_parasitics")
add_test(
NAME tcl.parasitics.gcd_spef
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> parasitics_gcd_spef
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.parasitics.gcd_spef PROPERTIES LABELS "tcl;module_parasitics")
add_test(
NAME tcl.parasitics.wireload
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> parasitics_wireload
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.parasitics.wireload PROPERTIES LABELS "tcl;module_parasitics")
add_test(
NAME tcl.parasitics.annotation_query
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> parasitics_annotation_query
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.parasitics.annotation_query PROPERTIES LABELS "tcl;module_parasitics")
add_test(
NAME tcl.parasitics.delete_network
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> parasitics_delete_network
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.parasitics.delete_network PROPERTIES LABELS "tcl;module_parasitics")
add_test(
NAME tcl.parasitics.coupling_reduce
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> parasitics_coupling_reduce
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.parasitics.coupling_reduce PROPERTIES LABELS "tcl;module_parasitics")
add_test(
NAME tcl.parasitics.pi_pole_residue
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> parasitics_pi_pole_residue
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.parasitics.pi_pole_residue PROPERTIES LABELS "tcl;module_parasitics")
add_test(
NAME tcl.parasitics.spef_formats
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> parasitics_spef_formats
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.parasitics.spef_formats PROPERTIES LABELS "tcl;module_parasitics")
add_test(
NAME tcl.parasitics.gcd_reduce
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> parasitics_gcd_reduce
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.parasitics.gcd_reduce PROPERTIES LABELS "tcl;module_parasitics")
add_subdirectory(cpp) add_subdirectory(cpp)

11
parasitics/test/parasitics_annotation_query.tcl
View File

@ -1,16 +1,5 @@
# Test parasitic annotation queries, find_pi_elmore, find_elmore, and # Test parasitic annotation queries, find_pi_elmore, find_elmore, and
# detailed SPEF operations for coverage improvement. # detailed SPEF operations for coverage improvement.
# Targets:
# ConcreteParasitics.cc: findPiElmore, findElmore, setPiModel, setElmore,
# makeParasiticPi, makeParasiticPiElmore, deleteParasitics(Pin),
# deleteParasitics(Net), isReduced, setIsReduced, capacitance,
# findParasitic, piModel, elmore, deletePinBefore
# ReduceParasitics.cc: parasitic reduction, reduceToPiElmore,
# reduceToPi, arnoldiPole
# SpefReader.cc: SPEF parsing detailed paths, name mapping,
# D_NET/R_NET parsing, *CONN/*CAP/*RES sections
# Parasitics.cc: find/make/delete parasitic operations
# ReportParasiticAnnotation.cc: report annotation with various flags
source ../../test/helpers.tcl source ../../test/helpers.tcl

18
parasitics/test/parasitics_coupling.tcl
View File

@ -1,22 +1,4 @@
# Test manual parasitic creation with coupling caps # Test manual parasitic creation with coupling caps
# Targets: ConcreteParasitics.cc uncovered functions:
# makeCapacitor (coupling cap, line 1389, hit=0)
# ConcretePi constructor (line 138, hit=0), setPiModel (line 155, hit=0)
# ConcretePiElmore constructor (line 182, hit=0)
# ConcreteParasitic::setPiModel (line 92, hit=0)
# ConcreteParasitic::setElmore (line 118, hit=0)
# ConcreteParasitic::setIsReduced (line 105, hit=0)
# ConcretePi::setIsReduced (line 175, hit=0)
# ConcreteParasitics::setPiModel (line 1050, hit=0)
# deleteParasitics(Pin) (line 824, hit=0)
# deleteParasitics(Pin, AnalysisPt) (line 810, hit=0)
# deleteParasitics(Net, AnalysisPt) (line 838, hit=0)
# deleteParasiticNetworks (line 1305, hit=0)
# deletePinBefore (line 897, hit=0)
# makePiPoleResidue (line 1112, hit=0)
# setPoleResidue (line 1160, hit=0)
# Also targets: Parasitics.cc, ReduceParasitics.cc
# ReportParasiticAnnotation.cc
# Read ASAP7 libraries # Read ASAP7 libraries
read_liberty ../../test/asap7/asap7sc7p5t_SEQ_RVT_FF_nldm_220123.lib read_liberty ../../test/asap7/asap7sc7p5t_SEQ_RVT_FF_nldm_220123.lib

9
parasitics/test/parasitics_delete_network.tcl
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@ -1,13 +1,4 @@
# Test parasitic deletion, network cleanup, and re-read flows. # Test parasitic deletion, network cleanup, and re-read flows.
# Targets: ConcreteParasitics.cc uncovered functions:
# deleteParasitics(Pin), deleteParasitics(Pin, AnalysisPt),
# deleteParasitics(Net, AnalysisPt), deleteReducedParasitics,
# deleteDrvrReducedParasitics, disconnectPinBefore,
# isPiElmore, isPiModel, isPiPoleResidue, isReducedParasiticNetwork,
# capacitance, hasParasiticNetwork, findParasiticNetwork,
# makeParasiticNetwork, deleteParasiticNetworks
# Also targets: Parasitics.cc, ReduceParasitics.cc
source ../../test/helpers.tcl source ../../test/helpers.tcl
# Read ASAP7 libraries # Read ASAP7 libraries

6
parasitics/test/parasitics_estimate_wirerc.tcl
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@ -1,10 +1,4 @@
# Test parasitic estimation with set_wire_rc and wireload models # Test parasitic estimation with set_wire_rc and wireload models
# Targets: EstimateParasitics.cc (estimatePiElmore, wireload-based estimation)
# ConcreteParasitics.cc (makeParasiticPi, makeParasiticPiElmore, setPiModel,
# setElmore, findPiElmore, findElmore, delete operations)
# ReduceParasitics.cc (parasitic reduction with estimated parasitics)
# Parasitics.cc (estimate operations, delete parasitics, find parasitics)
# SpefReader.cc (additional format coverage)
# Read ASAP7 libraries # Read ASAP7 libraries
read_liberty ../../test/asap7/asap7sc7p5t_SEQ_RVT_FF_nldm_220123.lib read_liberty ../../test/asap7/asap7sc7p5t_SEQ_RVT_FF_nldm_220123.lib

5
parasitics/test/parasitics_manual.tcl
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@ -1,9 +1,4 @@
# Test manual parasitic model setting and parasitic reduction # Test manual parasitic model setting and parasitic reduction
# Targets: ConcreteParasitics.cc (Pi/Elmore model creation, parasitic queries)
# Parasitics.cc (makePiElmore, setElmore, findPiElmore, findElmore)
# ReduceParasitics.cc (parasitic reduction paths)
# EstimateParasitics.cc (estimated parasitic paths)
# ReportParasiticAnnotation.cc
read_liberty ../../test/nangate45/Nangate45_typ.lib read_liberty ../../test/nangate45/Nangate45_typ.lib
read_verilog ../../test/reg1_asap7.v read_verilog ../../test/reg1_asap7.v

9
parasitics/test/parasitics_pi_pole_residue.tcl
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@ -1,13 +1,4 @@
# Test pi_pole_residue parasitic model creation and query. # Test pi_pole_residue parasitic model creation and query.
# Targets: ConcreteParasitics.cc uncovered:
# ConcretePiPoleResidue constructor (line 309), isPiPoleResidue,
# ConcretePiPoleResidue::piModel, setPiModel, capacitance,
# findPoleResidue, setPoleResidue, deleteLoad,
# ConcretePoleResidue constructor, poleResidue, poleResidueCount,
# unannotatedLoads
# Also targets: Parasitics.cc: makePiPoleResidue, setPoleResidue, findPiPoleResidue
# ReduceParasitics.cc: reduceToPiPoleResidue, arnoldi reduction with pole/residue
# ConcreteParasitics.cc: isPiModel vs isPiPoleResidue branching
source ../../test/helpers.tcl source ../../test/helpers.tcl

5
parasitics/test/parasitics_reduce.tcl
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@ -1,9 +1,4 @@
# Test parasitic reduction and various delay calculators with parasitics # Test parasitic reduction and various delay calculators with parasitics
# Targets: ReduceParasitics.cc (parasitic reduction - 43.5% coverage)
# ConcreteParasitics.cc (48.2% coverage, parasitic operations)
# Parasitics.cc (43.0% coverage)
# SpefReader.cc (68.6% coverage, more SPEF paths)
# EstimateParasitics.cc (68.7% coverage)
# Read ASAP7 libraries # Read ASAP7 libraries
read_liberty ../../test/asap7/asap7sc7p5t_SEQ_RVT_FF_nldm_220123.lib read_liberty ../../test/asap7/asap7sc7p5t_SEQ_RVT_FF_nldm_220123.lib

5
parasitics/test/parasitics_reduce_dcalc.tcl
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@ -1,9 +1,4 @@
# Test parasitic reduction with different delay calculators # Test parasitic reduction with different delay calculators
# Targets: ReduceParasitics.cc (parasitic reduction algorithms)
# ConcreteParasitics.cc (parasitic network operations, node/resistor/cap creation)
# Parasitics.cc (parasitic find/make/delete operations)
# SpefReader.cc (SPEF parsing with parasitic network)
# EstimateParasitics.cc (estimated parasitic paths)
# Read ASAP7 libraries # Read ASAP7 libraries
read_liberty ../../test/asap7/asap7sc7p5t_SEQ_RVT_FF_nldm_220123.lib read_liberty ../../test/asap7/asap7sc7p5t_SEQ_RVT_FF_nldm_220123.lib

8
parasitics/test/parasitics_spef_formats.tcl
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@ -1,13 +1,5 @@
# Test SPEF reader with different SPEF formats, port sections, design flow, # Test SPEF reader with different SPEF formats, port sections, design flow,
# RSPF sections, and varied scale factors. # RSPF sections, and varied scale factors.
# Targets: SpefReader.cc uncovered:
# portDirection (I, O, B variants), rspfBegin/rspfFinish/rspfDrvrBegin/rspfLoad,
# dspfBegin/dspfFinish, findParasiticNode (port path, net:subnode path),
# setDesignFlow, RSPF parsing vs DSPF, findPin (port-only name path),
# findNetRelative (sdc_network fallback), different scale factors
# Also targets: ConcreteParasitics.cc: makeParasiticNetwork, parasitic network
# node/resistor/capacitor creation, deleteParasiticNetworks on re-read
source ../../test/helpers.tcl source ../../test/helpers.tcl
#--------------------------------------------------------------- #---------------------------------------------------------------

12
parasitics/test/parasitics_spef_namemap.tcl
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@ -1,16 +1,4 @@
# Test SPEF reader with different name mapping styles and corner handling # Test SPEF reader with different name mapping styles and corner handling
# Targets: SpefReader.cc uncovered functions:
# findPinRelative (line 176, hit=0)
# findPortPinRelative (line 182, hit=0)
# findInstanceRelative (line 159, hit=0)
# setDesignFlow (line 300)
# setDivider, setDelimiter, setBusBrackets
# setCapScale, setResScale, setTimeScale, setInductScale
# Also targets: SpefParse.yy (more parser paths)
# SpefLex.ll (more lexer paths)
# ConcreteParasitics.cc (parasitic network creation/query paths)
# Parasitics.cc (findParasiticNetwork, makeParasiticNetwork)
# Read ASAP7 libraries # Read ASAP7 libraries
read_liberty ../../test/asap7/asap7sc7p5t_SEQ_RVT_FF_nldm_220123.lib read_liberty ../../test/asap7/asap7sc7p5t_SEQ_RVT_FF_nldm_220123.lib
read_liberty ../../test/asap7/asap7sc7p5t_INVBUF_RVT_FF_nldm_220122.lib.gz read_liberty ../../test/asap7/asap7sc7p5t_INVBUF_RVT_FF_nldm_220122.lib.gz

6
parasitics/test/parasitics_wireload.tcl
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@ -1,10 +1,4 @@
# Test parasitic estimation with pi model / elmore, deletion, and override paths. # Test parasitic estimation with pi model / elmore, deletion, and override paths.
# Targets: ConcreteParasitics.cc (makePiElmore, findElmore, deletePiElmore,
# isPiElmore, isPiModel, piModel, setPiModel, setElmore paths,
# delete operations, cap calculation)
# Targets: ReduceParasitics.cc (reduction with various pi models)
# Targets: Parasitics.cc (set/get/delete parasitic operations)
# Targets: EstimateParasitics.cc (estimatePiElmore tree cases)
source ../../test/helpers.tcl source ../../test/helpers.tcl

56
power/test/CMakeLists.txt
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@ -1,50 +1,12 @@
add_test( sta_module_tests("power"
NAME tcl.power.report TESTS
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> power_report detailed
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR} propagate
report
report_options
saif
saif_vcd
vcd_detailed
) )
set_tests_properties(tcl.power.report PROPERTIES LABELS "tcl;module_power")
add_test(
NAME tcl.power.detailed
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> power_detailed
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.power.detailed PROPERTIES LABELS "tcl;module_power")
add_test(
NAME tcl.power.report_options
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> power_report_options
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.power.report_options PROPERTIES LABELS "tcl;module_power")
add_test(
NAME tcl.power.saif
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> power_saif
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.power.saif PROPERTIES LABELS "tcl;module_power")
add_test(
NAME tcl.power.saif_vcd
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> power_saif_vcd
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.power.saif_vcd PROPERTIES LABELS "tcl;module_power")
add_test(
NAME tcl.power.vcd_detailed
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> power_vcd_detailed
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.power.vcd_detailed PROPERTIES LABELS "tcl;module_power")
add_test(
NAME tcl.power.propagate
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> power_propagate
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.power.propagate PROPERTIES LABELS "tcl;module_power")
add_subdirectory(cpp) add_subdirectory(cpp)

9
power/test/power_propagate.tcl
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@ -1,13 +1,4 @@
# Test power propagation, per-instance power breakdown, and activity querying. # Test power propagation, per-instance power breakdown, and activity querying.
# Targets: Power.cc uncovered functions:
# ensureActivities, propagateActivities, seedActivities,
# findActivityPeriod, annotateActivities,
# internalPower, switchingPower, leakagePower per-instance,
# power for different cell types (sequential, combinational, clock, macro),
# evalActivity, evalBddDuty, evalBddActivity, evalDiffDuty,
# findSeqActivity, clockGatePins, inClockNetwork,
# powerInside, highestPowerInstances, ensureInstPowers
source ../../test/helpers.tcl source ../../test/helpers.tcl
#--------------------------------------------------------------- #---------------------------------------------------------------

320
sdc/test/CMakeLists.txt
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@ -1,281 +1,45 @@
add_test( sta_module_tests("sdc"
NAME tcl.sdc.constraints TESTS
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> sdc_constraints advanced
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR} capacitance_propagated
clock_groups_sense
clock_operations
clock_removal_cascade
clocks
constraints
cycle_acct_clk_relationships
cycle_acct_genclk
delay_borrow_group
derate_disable_deep
design_rules_limits
disable_case
drive_input_pvt
environment
exception_advanced
exception_intersect
exception_match_filter
exception_merge_priority
exception_override_priority
exception_rise_fall_transitions
exception_thru_complex
exception_thru_net
exception_thru_override
exceptions
filter_query
genclk_advanced
leaf_pin_filter_removal
net_wire_voltage
port_delay_advanced
removal_reset
remove_clock_gating
sense_unset_override
variables
write_comprehensive
write_disabled_groups
write_options
write_read
write_roundtrip
write_roundtrip_full
) )
set_tests_properties(tcl.sdc.constraints PROPERTIES LABELS "tcl;module_sdc")
add_test(
NAME tcl.sdc.clocks
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> sdc_clocks
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.sdc.clocks PROPERTIES LABELS "tcl;module_sdc")
add_test(
NAME tcl.sdc.exceptions
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> sdc_exceptions
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.sdc.exceptions PROPERTIES LABELS "tcl;module_sdc")
add_test(
NAME tcl.sdc.environment
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> sdc_environment
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.sdc.environment PROPERTIES LABELS "tcl;module_sdc")
add_test(
NAME tcl.sdc.write_read
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> sdc_write_read
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.sdc.write_read PROPERTIES LABELS "tcl;module_sdc")
add_test(
NAME tcl.sdc.write_comprehensive
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> sdc_write_comprehensive
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.sdc.write_comprehensive PROPERTIES LABELS "tcl;module_sdc")
add_test(
NAME tcl.sdc.variables
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> sdc_variables
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.sdc.variables PROPERTIES LABELS "tcl;module_sdc")
add_test(
NAME tcl.sdc.advanced
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> sdc_advanced
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.sdc.advanced PROPERTIES LABELS "tcl;module_sdc")
add_test(
NAME tcl.sdc.write_options
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> sdc_write_options
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.sdc.write_options PROPERTIES LABELS "tcl;module_sdc")
add_test(
NAME tcl.sdc.genclk_advanced
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> sdc_genclk_advanced
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.sdc.genclk_advanced PROPERTIES LABELS "tcl;module_sdc")
add_test(
NAME tcl.sdc.exception_advanced
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> sdc_exception_advanced
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.sdc.exception_advanced PROPERTIES LABELS "tcl;module_sdc")
add_test(
NAME tcl.sdc.port_delay_advanced
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> sdc_port_delay_advanced
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.sdc.port_delay_advanced PROPERTIES LABELS "tcl;module_sdc")
add_test(
NAME tcl.sdc.clock_groups_sense
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> sdc_clock_groups_sense
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.sdc.clock_groups_sense PROPERTIES LABELS "tcl;module_sdc")
add_test(
NAME tcl.sdc.disable_case
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> sdc_disable_case
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.sdc.disable_case PROPERTIES LABELS "tcl;module_sdc")
add_test(
NAME tcl.sdc.removal_reset
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> sdc_removal_reset
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.sdc.removal_reset PROPERTIES LABELS "tcl;module_sdc")
add_test(
NAME tcl.sdc.write_roundtrip
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> sdc_write_roundtrip
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.sdc.write_roundtrip PROPERTIES LABELS "tcl;module_sdc")
add_test(
NAME tcl.sdc.net_wire_voltage
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> sdc_net_wire_voltage
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.sdc.net_wire_voltage PROPERTIES LABELS "tcl;module_sdc")
add_test(
NAME tcl.sdc.exception_merge_priority
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> sdc_exception_merge_priority
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.sdc.exception_merge_priority PROPERTIES LABELS "tcl;module_sdc")
add_test(
NAME tcl.sdc.clock_operations
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> sdc_clock_operations
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.sdc.clock_operations PROPERTIES LABELS "tcl;module_sdc")
add_test(
NAME tcl.sdc.design_rules_limits
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> sdc_design_rules_limits
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.sdc.design_rules_limits PROPERTIES LABELS "tcl;module_sdc")
add_test(
NAME tcl.sdc.drive_input_pvt
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> sdc_drive_input_pvt
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.sdc.drive_input_pvt PROPERTIES LABELS "tcl;module_sdc")
add_test(
NAME tcl.sdc.filter_query
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> sdc_filter_query
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.sdc.filter_query PROPERTIES LABELS "tcl;module_sdc")
add_test(
NAME tcl.sdc.derate_disable_deep
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> sdc_derate_disable_deep
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.sdc.derate_disable_deep PROPERTIES LABELS "tcl;module_sdc")
add_test(
NAME tcl.sdc.exception_thru_net
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> sdc_exception_thru_net
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.sdc.exception_thru_net PROPERTIES LABELS "tcl;module_sdc")
add_test(
NAME tcl.sdc.delay_borrow_group
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> sdc_delay_borrow_group
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.sdc.delay_borrow_group PROPERTIES LABELS "tcl;module_sdc")
add_test(
NAME tcl.sdc.sense_unset_override
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> sdc_sense_unset_override
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.sdc.sense_unset_override PROPERTIES LABELS "tcl;module_sdc")
add_test(
NAME tcl.sdc.exception_intersect
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> sdc_exception_intersect
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.sdc.exception_intersect PROPERTIES LABELS "tcl;module_sdc")
add_test(
NAME tcl.sdc.remove_clock_gating
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> sdc_remove_clock_gating
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.sdc.remove_clock_gating PROPERTIES LABELS "tcl;module_sdc")
add_test(
NAME tcl.sdc.exception_override_priority
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> sdc_exception_override_priority
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.sdc.exception_override_priority PROPERTIES LABELS "tcl;module_sdc")
add_test(
NAME tcl.sdc.write_disabled_groups
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> sdc_write_disabled_groups
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.sdc.write_disabled_groups PROPERTIES LABELS "tcl;module_sdc")
add_test(
NAME tcl.sdc.clock_removal_cascade
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> sdc_clock_removal_cascade
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.sdc.clock_removal_cascade PROPERTIES LABELS "tcl;module_sdc")
add_test(
NAME tcl.sdc.exception_thru_complex
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> sdc_exception_thru_complex
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.sdc.exception_thru_complex PROPERTIES LABELS "tcl;module_sdc")
add_test(
NAME tcl.sdc.capacitance_propagated
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> sdc_capacitance_propagated
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.sdc.capacitance_propagated PROPERTIES LABELS "tcl;module_sdc")
add_test(
NAME tcl.sdc.write_roundtrip_full
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> sdc_write_roundtrip_full
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.sdc.write_roundtrip_full PROPERTIES LABELS "tcl;module_sdc")
add_test(
NAME tcl.sdc.cycle_acct_clk_relationships
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> sdc_cycle_acct_clk_relationships
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.sdc.cycle_acct_clk_relationships PROPERTIES LABELS "tcl;module_sdc")
add_test(
NAME tcl.sdc.leaf_pin_filter_removal
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> sdc_leaf_pin_filter_removal
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.sdc.leaf_pin_filter_removal PROPERTIES LABELS "tcl;module_sdc")
add_test(
NAME tcl.sdc.exception_rise_fall_transitions
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> sdc_exception_rise_fall_transitions
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.sdc.exception_rise_fall_transitions PROPERTIES LABELS "tcl;module_sdc")
add_test(
NAME tcl.sdc.cycle_acct_genclk
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> sdc_cycle_acct_genclk
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.sdc.cycle_acct_genclk PROPERTIES LABELS "tcl;module_sdc")
add_test(
NAME tcl.sdc.exception_thru_override
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> sdc_exception_thru_override
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.sdc.exception_thru_override PROPERTIES LABELS "tcl;module_sdc")
add_test(
NAME tcl.sdc.exception_match_filter
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> sdc_exception_match_filter
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.sdc.exception_match_filter PROPERTIES LABELS "tcl;module_sdc")
add_subdirectory(cpp) add_subdirectory(cpp)

4
sdc/test/sdc_port_delay_advanced.tcl
View File

@ -1,8 +1,4 @@
# Test advanced port delay, derating, data check, and misc SDC features # Test advanced port delay, derating, data check, and misc SDC features
# Targets: PortDelay.cc, DeratingFactors.cc, DataCheck.cc, Clock.cc,
# ClockInsertion.cc, ClockLatency.cc, DisabledPorts.cc,
# WriteSdc.cc (writePortDelay, writeDeratingFactors, writeDataCheck,
# writeConstants, writeDisabled*, writeClockInsertion)
source ../../test/helpers.tcl source ../../test/helpers.tcl
read_liberty ../../test/nangate45/Nangate45_typ.lib read_liberty ../../test/nangate45/Nangate45_typ.lib

80
sdf/test/CMakeLists.txt
View File

@ -1,71 +1,15 @@
add_test( sta_module_tests("sdf"
NAME tcl.sdf.read_write TESTS
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> sdf_read_write advanced
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR} annotation
check_annotation
cond_pathpulse
device_cond
edge_write
read_write
reread_cond
timing_checks
write_interconnect
) )
set_tests_properties(tcl.sdf.read_write PROPERTIES LABELS "tcl;module_sdf")
add_test(
NAME tcl.sdf.annotation
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> sdf_annotation
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.sdf.annotation PROPERTIES LABELS "tcl;module_sdf")
add_test(
NAME tcl.sdf.advanced
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> sdf_advanced
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.sdf.advanced PROPERTIES LABELS "tcl;module_sdf")
add_test(
NAME tcl.sdf.edge_write
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> sdf_edge_write
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.sdf.edge_write PROPERTIES LABELS "tcl;module_sdf")
add_test(
NAME tcl.sdf.reread_cond
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> sdf_reread_cond
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.sdf.reread_cond PROPERTIES LABELS "tcl;module_sdf")
add_test(
NAME tcl.sdf.write_interconnect
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> sdf_write_interconnect
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.sdf.write_interconnect PROPERTIES LABELS "tcl;module_sdf")
add_test(
NAME tcl.sdf.check_annotation
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> sdf_check_annotation
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.sdf.check_annotation PROPERTIES LABELS "tcl;module_sdf")
add_test(
NAME tcl.sdf.timing_checks
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> sdf_timing_checks
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.sdf.timing_checks PROPERTIES LABELS "tcl;module_sdf")
add_test(
NAME tcl.sdf.device_cond
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> sdf_device_cond
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.sdf.device_cond PROPERTIES LABELS "tcl;module_sdf")
add_test(
NAME tcl.sdf.cond_pathpulse
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> sdf_cond_pathpulse
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.sdf.cond_pathpulse PROPERTIES LABELS "tcl;module_sdf")
add_subdirectory(cpp) add_subdirectory(cpp)

16
sdf/test/sdf_write_interconnect.tcl
View File

@ -35,8 +35,6 @@ report_checks
puts "--- write_sdf with interconnect ---" puts "--- write_sdf with interconnect ---"
set sdf_out1 [make_result_file "${test_name}_default.sdf"] set sdf_out1 [make_result_file "${test_name}_default.sdf"]
write_sdf $sdf_out1 write_sdf $sdf_out1
if { [file exists $sdf_out1] && [file size $sdf_out1] > 0 } {
}
#--------------------------------------------------------------- #---------------------------------------------------------------
# Write SDF with -include_typ (triple values) # Write SDF with -include_typ (triple values)
@ -44,8 +42,6 @@ if { [file exists $sdf_out1] && [file size $sdf_out1] > 0 } {
puts "--- write_sdf -include_typ ---" puts "--- write_sdf -include_typ ---"
set sdf_out2 [make_result_file "${test_name}_typ.sdf"] set sdf_out2 [make_result_file "${test_name}_typ.sdf"]
write_sdf -include_typ $sdf_out2 write_sdf -include_typ $sdf_out2
if { [file exists $sdf_out2] && [file size $sdf_out2] > 0 } {
}
#--------------------------------------------------------------- #---------------------------------------------------------------
# Write SDF with -divider . # Write SDF with -divider .
@ -53,8 +49,6 @@ if { [file exists $sdf_out2] && [file size $sdf_out2] > 0 } {
puts "--- write_sdf -divider . ---" puts "--- write_sdf -divider . ---"
set sdf_out3 [make_result_file "${test_name}_dot.sdf"] set sdf_out3 [make_result_file "${test_name}_dot.sdf"]
write_sdf -divider . $sdf_out3 write_sdf -divider . $sdf_out3
if { [file exists $sdf_out3] && [file size $sdf_out3] > 0 } {
}
#--------------------------------------------------------------- #---------------------------------------------------------------
# Write SDF with various digit counts # Write SDF with various digit counts
@ -63,8 +57,6 @@ puts "--- write_sdf -digits ---"
foreach digits {2 4 6 8} { foreach digits {2 4 6 8} {
set sdf_d [make_result_file "${test_name}_d${digits}.sdf"] set sdf_d [make_result_file "${test_name}_d${digits}.sdf"]
write_sdf -digits $digits $sdf_d write_sdf -digits $digits $sdf_d
if { [file exists $sdf_d] && [file size $sdf_d] > 0 } {
}
} }
#--------------------------------------------------------------- #---------------------------------------------------------------
@ -73,8 +65,6 @@ foreach digits {2 4 6 8} {
puts "--- write_sdf -no_timestamp -no_version ---" puts "--- write_sdf -no_timestamp -no_version ---"
set sdf_out4 [make_result_file "${test_name}_clean.sdf"] set sdf_out4 [make_result_file "${test_name}_clean.sdf"]
write_sdf -no_timestamp -no_version $sdf_out4 write_sdf -no_timestamp -no_version $sdf_out4
if { [file exists $sdf_out4] && [file size $sdf_out4] > 0 } {
}
#--------------------------------------------------------------- #---------------------------------------------------------------
# Write SDF gzip # Write SDF gzip
@ -82,8 +72,6 @@ if { [file exists $sdf_out4] && [file size $sdf_out4] > 0 } {
puts "--- write_sdf -gzip ---" puts "--- write_sdf -gzip ---"
set sdf_out5 [make_result_file "${test_name}_gz.sdf.gz"] set sdf_out5 [make_result_file "${test_name}_gz.sdf.gz"]
write_sdf -gzip $sdf_out5 write_sdf -gzip $sdf_out5
if { [file exists $sdf_out5] && [file size $sdf_out5] > 0 } {
}
#--------------------------------------------------------------- #---------------------------------------------------------------
# Write SDF with all options combined # Write SDF with all options combined
@ -91,8 +79,6 @@ if { [file exists $sdf_out5] && [file size $sdf_out5] > 0 } {
puts "--- write_sdf all options ---" puts "--- write_sdf all options ---"
set sdf_out6 [make_result_file "${test_name}_all.sdf"] set sdf_out6 [make_result_file "${test_name}_all.sdf"]
write_sdf -digits 4 -include_typ -no_timestamp -no_version -divider . $sdf_out6 write_sdf -digits 4 -include_typ -no_timestamp -no_version -divider . $sdf_out6
if { [file exists $sdf_out6] && [file size $sdf_out6] > 0 } {
}
#--------------------------------------------------------------- #---------------------------------------------------------------
# Read SDF back and annotate (roundtrip test) # Read SDF back and annotate (roundtrip test)
@ -158,5 +144,3 @@ report_annotated_check -setup -hold
puts "--- write SDF after SDF annotation ---" puts "--- write SDF after SDF annotation ---"
set sdf_out7 [make_result_file "${test_name}_annotated.sdf"] set sdf_out7 [make_result_file "${test_name}_annotated.sdf"]
write_sdf -no_timestamp -no_version $sdf_out7 write_sdf -no_timestamp -no_version $sdf_out7
if { [file exists $sdf_out7] && [file size $sdf_out7] > 0 } {
}

592
search/test/CMakeLists.txt
View File

@ -1,519 +1,79 @@
add_test( sta_module_tests("search"
NAME tcl.search.timing TESTS
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> search_timing analysis
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR} annotated_write_verilog
assigned_delays
check_timing
check_types_deep
clk_skew_interclk
clk_skew_multiclock
corner_skew
crpr
crpr_data_checks
data_check_gated
exception_paths
fanin_fanout
fanin_fanout_deep
gated_clk
genclk
genclk_latch_deep
genclk_property_report
json_unconstrained
latch
latch_timing
levelize_loop_disabled
levelize_sim
limit_violations
limits_verbose
min_period_max_skew
min_period_short
multiclock
multicorner_analysis
network_edit_deep
network_edit_replace
network_sta_deep
path_delay_output
path_end_types
path_enum_deep
path_enum_groups
path_enum_nworst
port_pin_properties
power_activity
property
property_deep
property_extra
property_inst_cell
property_libport_deep
pvt_analysis
register
register_deep
register_filter_combos
register_latch_sim
report_fields_formats
report_formats
report_gated_datacheck
report_json_formats
report_path_detail
report_path_expanded
report_path_latch_expanded
report_path_pvt_cap
report_path_types
sdc_advanced
search_arrival_required
sim_const_prop
sim_logic_clk_network
spef_parasitics
sta_bidirect_extcap
sta_cmds
sta_extra
tag_path_analysis
timing
timing_model
timing_model_clktree
timing_model_deep
timing_model_readback
worst_slack_sta
write_sdf_model
) )
set_tests_properties(tcl.search.timing PROPERTIES LABELS "tcl;module_search")
add_test(
NAME tcl.search.report_formats
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> search_report_formats
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.search.report_formats PROPERTIES LABELS "tcl;module_search")
add_test(
NAME tcl.search.analysis
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> search_analysis
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.search.analysis PROPERTIES LABELS "tcl;module_search")
add_test(
NAME tcl.search.sdc_advanced
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> search_sdc_advanced
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.search.sdc_advanced PROPERTIES LABELS "tcl;module_search")
add_test(
NAME tcl.search.fanin_fanout
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> search_fanin_fanout
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.search.fanin_fanout PROPERTIES LABELS "tcl;module_search")
add_test(
NAME tcl.search.genclk
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> search_genclk
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.search.genclk PROPERTIES LABELS "tcl;module_search")
add_test(
NAME tcl.search.property
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> search_property
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.search.property PROPERTIES LABELS "tcl;module_search")
add_test(
NAME tcl.search.latch
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> search_latch
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.search.latch PROPERTIES LABELS "tcl;module_search")
add_test(
NAME tcl.search.crpr
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> search_crpr
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.search.crpr PROPERTIES LABELS "tcl;module_search")
add_test(
NAME tcl.search.register
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> search_register
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.search.register PROPERTIES LABELS "tcl;module_search")
add_test(
NAME tcl.search.check_timing
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> search_check_timing
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.search.check_timing PROPERTIES LABELS "tcl;module_search")
add_test(
NAME tcl.search.report_path_detail
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> search_report_path_detail
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.search.report_path_detail PROPERTIES LABELS "tcl;module_search")
add_test(
NAME tcl.search.timing_model
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> search_timing_model
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.search.timing_model PROPERTIES LABELS "tcl;module_search")
add_test(
NAME tcl.search.sta_cmds
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> search_sta_cmds
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.search.sta_cmds PROPERTIES LABELS "tcl;module_search")
add_test(
NAME tcl.search.min_period_max_skew
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> search_min_period_max_skew
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.search.min_period_max_skew PROPERTIES LABELS "tcl;module_search")
add_test(
NAME tcl.search.corner_skew
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> search_corner_skew
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.search.corner_skew PROPERTIES LABELS "tcl;module_search")
add_test(
NAME tcl.search.path_end_types
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> search_path_end_types
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.search.path_end_types PROPERTIES LABELS "tcl;module_search")
add_test(
NAME tcl.search.levelize_sim
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> search_levelize_sim
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.search.levelize_sim PROPERTIES LABELS "tcl;module_search")
add_test(
NAME tcl.search.multiclock
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> search_multiclock
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.search.multiclock PROPERTIES LABELS "tcl;module_search")
add_test(
NAME tcl.search.gated_clk
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> search_gated_clk
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.search.gated_clk PROPERTIES LABELS "tcl;module_search")
add_test(
NAME tcl.search.property_extra
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> search_property_extra
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.search.property_extra PROPERTIES LABELS "tcl;module_search")
add_test(
NAME tcl.search.sta_extra
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> search_sta_extra
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.search.sta_extra PROPERTIES LABELS "tcl;module_search")
add_test(
NAME tcl.search.json_unconstrained
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> search_json_unconstrained
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.search.json_unconstrained PROPERTIES LABELS "tcl;module_search")
add_test(
NAME tcl.search.port_pin_properties
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> search_port_pin_properties
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.search.port_pin_properties PROPERTIES LABELS "tcl;module_search")
add_test(
NAME tcl.search.min_period_short
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> search_min_period_short
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.search.min_period_short PROPERTIES LABELS "tcl;module_search")
add_test(
NAME tcl.search.worst_slack_sta
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> search_worst_slack_sta
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.search.worst_slack_sta PROPERTIES LABELS "tcl;module_search")
add_test(
NAME tcl.search.crpr_data_checks
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> search_crpr_data_checks
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.search.crpr_data_checks PROPERTIES LABELS "tcl;module_search")
add_test(
NAME tcl.search.multicorner_analysis
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> search_multicorner_analysis
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.search.multicorner_analysis PROPERTIES LABELS "tcl;module_search")
add_test(
NAME tcl.search.write_sdf_model
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> search_write_sdf_model
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.search.write_sdf_model PROPERTIES LABELS "tcl;module_search")
add_test(
NAME tcl.search.power_activity
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> search_power_activity
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.search.power_activity PROPERTIES LABELS "tcl;module_search")
add_test(
NAME tcl.search.path_enum_groups
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> search_path_enum_groups
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.search.path_enum_groups PROPERTIES LABELS "tcl;module_search")
add_test(
NAME tcl.search.latch_timing
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> search_latch_timing
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.search.latch_timing PROPERTIES LABELS "tcl;module_search")
add_test(
NAME tcl.search.report_path_expanded
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> search_report_path_expanded
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.search.report_path_expanded PROPERTIES LABELS "tcl;module_search")
add_test(
NAME tcl.search.limit_violations
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> search_limit_violations
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.search.limit_violations PROPERTIES LABELS "tcl;module_search")
add_test(
NAME tcl.search.data_check_gated
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> search_data_check_gated
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.search.data_check_gated PROPERTIES LABELS "tcl;module_search")
add_test(
NAME tcl.search.fanin_fanout_deep
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> search_fanin_fanout_deep
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.search.fanin_fanout_deep PROPERTIES LABELS "tcl;module_search")
add_test(
NAME tcl.search.network_edit_replace
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> search_network_edit_replace
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.search.network_edit_replace PROPERTIES LABELS "tcl;module_search")
add_test(
NAME tcl.search.annotated_write_verilog
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> search_annotated_write_verilog
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.search.annotated_write_verilog PROPERTIES LABELS "tcl;module_search")
add_test(
NAME tcl.search.report_path_pvt_cap
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> search_report_path_pvt_cap
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.search.report_path_pvt_cap PROPERTIES LABELS "tcl;module_search")
add_test(
NAME tcl.search.sim_logic_clk_network
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> search_sim_logic_clk_network
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.search.sim_logic_clk_network PROPERTIES LABELS "tcl;module_search")
add_test(
NAME tcl.search.exception_paths
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> search_exception_paths
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.search.exception_paths PROPERTIES LABELS "tcl;module_search")
add_test(
NAME tcl.search.timing_model_deep
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> search_timing_model_deep
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.search.timing_model_deep PROPERTIES LABELS "tcl;module_search")
add_test(
NAME tcl.search.property_deep
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> search_property_deep
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.search.property_deep PROPERTIES LABELS "tcl;module_search")
add_test(
NAME tcl.search.sim_const_prop
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> search_sim_const_prop
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.search.sim_const_prop PROPERTIES LABELS "tcl;module_search")
add_test(
NAME tcl.search.register_deep
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> search_register_deep
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.search.register_deep PROPERTIES LABELS "tcl;module_search")
add_test(
NAME tcl.search.network_sta_deep
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> search_network_sta_deep
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.search.network_sta_deep PROPERTIES LABELS "tcl;module_search")
add_test(
NAME tcl.search.genclk_latch_deep
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> search_genclk_latch_deep
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.search.genclk_latch_deep PROPERTIES LABELS "tcl;module_search")
add_test(
NAME tcl.search.limits_verbose
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> search_limits_verbose
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.search.limits_verbose PROPERTIES LABELS "tcl;module_search")
add_test(
NAME tcl.search.pvt_analysis
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> search_pvt_analysis
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.search.pvt_analysis PROPERTIES LABELS "tcl;module_search")
add_test(
NAME tcl.search.spef_parasitics
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> search_spef_parasitics
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.search.spef_parasitics PROPERTIES LABELS "tcl;module_search")
add_test(
NAME tcl.search.assigned_delays
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> search_assigned_delays
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.search.assigned_delays PROPERTIES LABELS "tcl;module_search")
add_test(
NAME tcl.search.report_json_formats
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> search_report_json_formats
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.search.report_json_formats PROPERTIES LABELS "tcl;module_search")
add_test(
NAME tcl.search.property_libport_deep
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> search_property_libport_deep
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.search.property_libport_deep PROPERTIES LABELS "tcl;module_search")
add_test(
NAME tcl.search.check_types_deep
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> search_check_types_deep
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.search.check_types_deep PROPERTIES LABELS "tcl;module_search")
add_test(
NAME tcl.search.property_inst_cell
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> search_property_inst_cell
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.search.property_inst_cell PROPERTIES LABELS "tcl;module_search")
add_test(
NAME tcl.search.report_path_latch_expanded
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> search_report_path_latch_expanded
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.search.report_path_latch_expanded PROPERTIES LABELS "tcl;module_search")
add_test(
NAME tcl.search.network_edit_deep
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> search_network_edit_deep
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.search.network_edit_deep PROPERTIES LABELS "tcl;module_search")
add_test(
NAME tcl.search.report_gated_datacheck
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> search_report_gated_datacheck
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.search.report_gated_datacheck PROPERTIES LABELS "tcl;module_search")
add_test(
NAME tcl.search.search_arrival_required
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> search_search_arrival_required
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.search.search_arrival_required PROPERTIES LABELS "tcl;module_search")
add_test(
NAME tcl.search.report_fields_formats
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> search_report_fields_formats
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.search.report_fields_formats PROPERTIES LABELS "tcl;module_search")
add_test(
NAME tcl.search.sta_bidirect_extcap
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> search_sta_bidirect_extcap
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.search.sta_bidirect_extcap PROPERTIES LABELS "tcl;module_search")
add_test(
NAME tcl.search.path_delay_output
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> search_path_delay_output
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.search.path_delay_output PROPERTIES LABELS "tcl;module_search")
add_test(
NAME tcl.search.genclk_property_report
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> search_genclk_property_report
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.search.genclk_property_report PROPERTIES LABELS "tcl;module_search")
add_test(
NAME tcl.search.path_enum_deep
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> search_path_enum_deep
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.search.path_enum_deep PROPERTIES LABELS "tcl;module_search")
add_test(
NAME tcl.search.timing_model_readback
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> search_timing_model_readback
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.search.timing_model_readback PROPERTIES LABELS "tcl;module_search")
add_test(
NAME tcl.search.clk_skew_multiclock
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> search_clk_skew_multiclock
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.search.clk_skew_multiclock PROPERTIES LABELS "tcl;module_search")
add_test(
NAME tcl.search.register_latch_sim
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> search_register_latch_sim
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.search.register_latch_sim PROPERTIES LABELS "tcl;module_search")
add_test(
NAME tcl.search.timing_model_clktree
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> search_timing_model_clktree
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.search.timing_model_clktree PROPERTIES LABELS "tcl;module_search")
add_test(
NAME tcl.search.path_enum_nworst
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> search_path_enum_nworst
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.search.path_enum_nworst PROPERTIES LABELS "tcl;module_search")
add_test(
NAME tcl.search.clk_skew_interclk
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> search_clk_skew_interclk
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.search.clk_skew_interclk PROPERTIES LABELS "tcl;module_search")
add_test(
NAME tcl.search.register_filter_combos
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> search_register_filter_combos
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.search.register_filter_combos PROPERTIES LABELS "tcl;module_search")
add_test(
NAME tcl.search.levelize_loop_disabled
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> search_levelize_loop_disabled
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.search.levelize_loop_disabled PROPERTIES LABELS "tcl;module_search")
add_test(
NAME tcl.search.tag_path_analysis
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> search_tag_path_analysis
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.search.tag_path_analysis PROPERTIES LABELS "tcl;module_search")
add_test(
NAME tcl.search.report_path_types
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> search_report_path_types
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.search.report_path_types PROPERTIES LABELS "tcl;module_search")
add_subdirectory(cpp) add_subdirectory(cpp)

72
spice/test/CMakeLists.txt
View File

@ -1,64 +1,14 @@
add_test( sta_module_tests("spice"
NAME tcl.spice.write TESTS
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> spice_write gate_advanced
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR} gate_cells
gcd_gate
gcd_path
multipath
path_min
subckt_file
write
write_options
) )
set_tests_properties(tcl.spice.write PROPERTIES LABELS "tcl;module_spice")
add_test(
NAME tcl.spice.write_options
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> spice_write_options
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.spice.write_options PROPERTIES LABELS "tcl;module_spice")
add_test(
NAME tcl.spice.gate_advanced
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> spice_gate_advanced
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.spice.gate_advanced PROPERTIES LABELS "tcl;module_spice")
add_test(
NAME tcl.spice.path_min
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> spice_path_min
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.spice.path_min PROPERTIES LABELS "tcl;module_spice")
add_test(
NAME tcl.spice.gate_cells
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> spice_gate_cells
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.spice.gate_cells PROPERTIES LABELS "tcl;module_spice")
add_test(
NAME tcl.spice.multipath
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> spice_multipath
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.spice.multipath PROPERTIES LABELS "tcl;module_spice")
add_test(
NAME tcl.spice.subckt_file
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> spice_subckt_file
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.spice.subckt_file PROPERTIES LABELS "tcl;module_spice")
add_test(
NAME tcl.spice.gcd_path
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> spice_gcd_path
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.spice.gcd_path PROPERTIES LABELS "tcl;module_spice")
add_test(
NAME tcl.spice.gcd_gate
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> spice_gcd_gate
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.spice.gcd_gate PROPERTIES LABELS "tcl;module_spice")
add_subdirectory(cpp) add_subdirectory(cpp)

11
spice/test/spice_gcd_gate.tcl
View File

@ -1,17 +1,6 @@
# Test write_gate_spice and write_path_spice with GCD sky130 design. # Test write_gate_spice and write_path_spice with GCD sky130 design.
# Uses a larger design to exercise different cell type handling, # Uses a larger design to exercise different cell type handling,
# multi-input gates, and varied simulator outputs. # multi-input gates, and varied simulator outputs.
# Targets: WriteSpice.cc uncovered:
# writeHeader: hspice ".options nomod" path
# writePrintStmt: xyce csv/gnuplot file generation path
# writeSubckts: subckt file parsing, cell matching
# recordSpicePortNames: port name extraction
# findCellSubckts: nested subckt discovery
# writeGnuplotFile: gnuplot command file generation
# replaceFileExt: filename extension replacement
# initPowerGnd: supply voltage lookup paths
# Also targets: WritePathSpice.cc path SPICE writing
source ../../test/helpers.tcl source ../../test/helpers.tcl
read_liberty ../../test/sky130hd/sky130_fd_sc_hd__tt_025C_1v80.lib read_liberty ../../test/sky130hd/sky130_fd_sc_hd__tt_025C_1v80.lib

9
spice/test/spice_gcd_path.tcl
View File

@ -1,13 +1,4 @@
# Test SPICE writing with the GCD sky130hd design (larger design with many cell types). # Test SPICE writing with the GCD sky130hd design (larger design with many cell types).
# Targets: WriteSpice.cc uncovered functions:
# writeSubckts (line 199+, parsing subckt definitions for many cell types),
# writeHeader, writePrintStmt, findCellSubckts, recordSpicePortNames,
# writeGnuplotFile, replaceFileExt, initPowerGnd,
# writeStageInstances, writeDcSweep, writeMeasure
# WritePathSpice.cc uncovered functions:
# writePathSpice with multi-stage paths, writePathStage,
# pathStagePins, writePowerBusConnect
source ../../test/helpers.tcl source ../../test/helpers.tcl
read_liberty ../../test/sky130hd/sky130_fd_sc_hd__tt_025C_1v80.lib read_liberty ../../test/sky130hd/sky130_fd_sc_hd__tt_025C_1v80.lib

8
test/regression
View File

@ -42,4 +42,10 @@ for arg in "$@"; do
done done
cd "${build_dir}" cd "${build_dir}"
ctest -L "module_${module}" "${args[@]}"
# The top-level test/ directory uses label "tcl" (not "module_test").
if [ "$module" = "test" ]; then
ctest -L "tcl" "${args[@]}"
else
ctest -L "module_${module}" "${args[@]}"
fi

72
util/test/CMakeLists.txt
View File

@ -1,64 +1,14 @@
add_test( sta_module_tests("util"
NAME tcl.util.msg_suppress TESTS
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> util_msg_suppress commands
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR} log_redirect
msg_suppress
parallel_misc
pattern_string
report_debug
report_format
report_redirect
report_string_log
) )
set_tests_properties(tcl.util.msg_suppress PROPERTIES LABELS "tcl;module_util")
add_test(
NAME tcl.util.commands
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> util_commands
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.util.commands PROPERTIES LABELS "tcl;module_util")
add_test(
NAME tcl.util.report_redirect
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> util_report_redirect
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.util.report_redirect PROPERTIES LABELS "tcl;module_util")
add_test(
NAME tcl.util.pattern_string
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> util_pattern_string
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.util.pattern_string PROPERTIES LABELS "tcl;module_util")
add_test(
NAME tcl.util.report_debug
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> util_report_debug
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.util.report_debug PROPERTIES LABELS "tcl;module_util")
add_test(
NAME tcl.util.parallel_misc
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> util_parallel_misc
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.util.parallel_misc PROPERTIES LABELS "tcl;module_util")
add_test(
NAME tcl.util.report_format
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> util_report_format
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.util.report_format PROPERTIES LABELS "tcl;module_util")
add_test(
NAME tcl.util.log_redirect
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> util_log_redirect
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.util.log_redirect PROPERTIES LABELS "tcl;module_util")
add_test(
NAME tcl.util.report_string_log
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> util_report_string_log
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.util.report_string_log PROPERTIES LABELS "tcl;module_util")
add_subdirectory(cpp) add_subdirectory(cpp)

9
util/test/util_log_redirect.tcl
View File

@ -1,14 +1,5 @@
# Test Report.cc log + redirect interaction, buffer growth, and # Test Report.cc log + redirect interaction, buffer growth, and
# simultaneous log+console output. # simultaneous log+console output.
# Targets: Report.cc uncovered functions:
# logBegin/logEnd with real report output,
# redirectFileAppendBegin with log active,
# redirectStringBegin/End with log active,
# printString with log_stream_ active (both redirect and log paths),
# printLine, printConsole, reportLine, reportLineString,
# buffer growth (printToBufferAppend with oversized strings),
# warn/fileWarn with suppressed IDs
source ../../test/helpers.tcl source ../../test/helpers.tcl
#--------------------------------------------------------------- #---------------------------------------------------------------

18
util/test/util_report_string_log.tcl
View File

@ -1,22 +1,4 @@
# Test Report.cc string output, log file, and buffer growth paths. # Test Report.cc string output, log file, and buffer growth paths.
# Targets: Report.cc uncovered:
# reportBlankLine (line 102-105)
# reportLineString (const char*) (line 108-111)
# reportLineString (const std::string&) (line 114-117)
# printToBuffer (non-varargs, line 122-129)
# printToBufferAppend: buffer growth path (line 158-168)
# printBufferLine (line 172-175)
# vwarn (line 196-206): va_list warn variant
# vfileWarn (line 227-239): va_list file warn variant
# verror (line 256-263): va_list error variant
# fileError (line 266-279)
# vfileError (line 282-292)
# logBegin / logEnd (line 348-362)
# redirectFileBegin / redirectFileEnd (line 365-386)
# redirectFileAppendBegin (line 373-378)
# redirectStringBegin / redirectStringEnd / redirectStringPrint
# Also targets: Debug.cc, PatternMatch.cc, StringUtil.cc
source ../../test/helpers.tcl source ../../test/helpers.tcl
#--------------------------------------------------------------- #---------------------------------------------------------------

216
verilog/test/CMakeLists.txt
View File

@ -1,190 +1,32 @@
add_test( sta_module_tests("verilog"
NAME tcl.verilog.roundtrip TESTS
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> verilog_roundtrip assign
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR} attributes
bus
bus_partselect
complex_bus
const_concat
coverage
error_paths
escaped_write
gcd_large
gcd_writer
hier_write
multimodule_write
preproc_param
read_asap7
remove_cells
roundtrip
specify
supply_tristate
write_asap7
write_assign_types
write_bus_types
write_complex_bus_types
write_nangate
write_options
write_sky130
writer_advanced
) )
set_tests_properties(tcl.verilog.roundtrip PROPERTIES LABELS "tcl;module_verilog")
add_test(
NAME tcl.verilog.write_options
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> verilog_write_options
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.verilog.write_options PROPERTIES LABELS "tcl;module_verilog")
add_test(
NAME tcl.verilog.read_asap7
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> verilog_read_asap7
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.verilog.read_asap7 PROPERTIES LABELS "tcl;module_verilog")
add_test(
NAME tcl.verilog.attributes
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> verilog_attributes
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.verilog.attributes PROPERTIES LABELS "tcl;module_verilog")
add_test(
NAME tcl.verilog.specify
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> verilog_specify
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.verilog.specify PROPERTIES LABELS "tcl;module_verilog")
add_test(
NAME tcl.verilog.writer_advanced
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> verilog_writer_advanced
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.verilog.writer_advanced PROPERTIES LABELS "tcl;module_verilog")
add_test(
NAME tcl.verilog.bus
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> verilog_bus
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.verilog.bus PROPERTIES LABELS "tcl;module_verilog")
add_test(
NAME tcl.verilog.assign
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> verilog_assign
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.verilog.assign PROPERTIES LABELS "tcl;module_verilog")
add_test(
NAME tcl.verilog.complex_bus
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> verilog_complex_bus
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.verilog.complex_bus PROPERTIES LABELS "tcl;module_verilog")
add_test(
NAME tcl.verilog.write_nangate
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> verilog_write_nangate
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.verilog.write_nangate PROPERTIES LABELS "tcl;module_verilog")
add_test(
NAME tcl.verilog.write_bus_types
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> verilog_write_bus_types
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.verilog.write_bus_types PROPERTIES LABELS "tcl;module_verilog")
add_test(
NAME tcl.verilog.write_assign_types
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> verilog_write_assign_types
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.verilog.write_assign_types PROPERTIES LABELS "tcl;module_verilog")
add_test(
NAME tcl.verilog.write_sky130
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> verilog_write_sky130
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.verilog.write_sky130 PROPERTIES LABELS "tcl;module_verilog")
add_test(
NAME tcl.verilog.write_asap7
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> verilog_write_asap7
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.verilog.write_asap7 PROPERTIES LABELS "tcl;module_verilog")
add_test(
NAME tcl.verilog.write_complex_bus_types
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> verilog_write_complex_bus_types
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.verilog.write_complex_bus_types PROPERTIES LABELS "tcl;module_verilog")
add_test(
NAME tcl.verilog.hier_write
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> verilog_hier_write
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.verilog.hier_write PROPERTIES LABELS "tcl;module_verilog")
add_test(
NAME tcl.verilog.supply_tristate
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> verilog_supply_tristate
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.verilog.supply_tristate PROPERTIES LABELS "tcl;module_verilog")
add_test(
NAME tcl.verilog.const_concat
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> verilog_const_concat
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.verilog.const_concat PROPERTIES LABELS "tcl;module_verilog")
add_test(
NAME tcl.verilog.escaped_write
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> verilog_escaped_write
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.verilog.escaped_write PROPERTIES LABELS "tcl;module_verilog")
add_test(
NAME tcl.verilog.remove_cells
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> verilog_remove_cells
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.verilog.remove_cells PROPERTIES LABELS "tcl;module_verilog")
add_test(
NAME tcl.verilog.error_paths
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> verilog_error_paths
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.verilog.error_paths PROPERTIES LABELS "tcl;module_verilog")
add_test(
NAME tcl.verilog.preproc_param
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> verilog_preproc_param
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.verilog.preproc_param PROPERTIES LABELS "tcl;module_verilog")
add_test(
NAME tcl.verilog.gcd_writer
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> verilog_gcd_writer
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.verilog.gcd_writer PROPERTIES LABELS "tcl;module_verilog")
add_test(
NAME tcl.verilog.bus_partselect
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> verilog_bus_partselect
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.verilog.bus_partselect PROPERTIES LABELS "tcl;module_verilog")
add_test(
NAME tcl.verilog.gcd_large
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> verilog_gcd_large
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.verilog.gcd_large PROPERTIES LABELS "tcl;module_verilog")
add_test(
NAME tcl.verilog.multimodule_write
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> verilog_multimodule_write
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.verilog.multimodule_write PROPERTIES LABELS "tcl;module_verilog")
add_test(
NAME tcl.verilog.coverage
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> verilog_coverage
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.verilog.coverage PROPERTIES LABELS "tcl;module_verilog")
add_subdirectory(cpp) add_subdirectory(cpp)

17
verilog/test/verilog_assign.tcl
View File

@ -1,14 +1,4 @@
# Test verilog with assign statements and continuous assignments # Test verilog with assign statements and continuous assignments
# Targets: VerilogReader.cc uncovered functions:
# makeAssign (line 510, hit=0), VerilogAssign constructor (line 1061, hit=0)
# mergeAssignNet (line 2102, hit=0)
# makeDclArg with VerilogAssign (line 454, hit=0)
# makeNetConstant (line 477, hit=0)
# VerilogDcl constructor (line 963, hit=0)
# VerilogDclBus constructor (line 1006, 1018, hit=0)
# Also exercises: VerilogLex.ll (assign keyword lexing)
# VerilogParse.yy (assign statement parsing)
# VerilogWriter.cc (writeAssigns, line 439)
source ../../test/helpers.tcl source ../../test/helpers.tcl
@ -97,17 +87,12 @@ puts "--- Test 4: write verilog ---"
set outfile [make_result_file verilog_assign_out.v] set outfile [make_result_file verilog_assign_out.v]
write_verilog $outfile write_verilog $outfile
if { [file exists $outfile] && [file size $outfile] > 0 } { puts "output size: [file size $outfile]"
puts "output size: [file size $outfile]"
}
# Write with pwr_gnd # Write with pwr_gnd
set outfile2 [make_result_file verilog_assign_pwr.v] set outfile2 [make_result_file verilog_assign_pwr.v]
write_verilog -include_pwr_gnd $outfile2 write_verilog -include_pwr_gnd $outfile2
if { [file exists $outfile2] && [file size $outfile2] > 0 } {
}
#--------------------------------------------------------------- #---------------------------------------------------------------
# Test 5: Get fanin/fanout through assign # Test 5: Get fanin/fanout through assign
#--------------------------------------------------------------- #---------------------------------------------------------------

8
verilog/test/verilog_attributes.tcl
View File

@ -52,14 +52,6 @@ puts "--- write_verilog and read back ---"
set outfile [make_result_file verilog_attr_out.v] set outfile [make_result_file verilog_attr_out.v]
write_verilog $outfile write_verilog $outfile
if { [file exists $outfile] && [file size $outfile] > 0 } {
} else {
puts "FAIL: output file issue"
}
# Write with include_pwr_gnd # Write with include_pwr_gnd
set outfile2 [make_result_file verilog_attr_pwr.v] set outfile2 [make_result_file verilog_attr_pwr.v]
write_verilog -include_pwr_gnd $outfile2 write_verilog -include_pwr_gnd $outfile2
if { [file exists $outfile2] && [file size $outfile2] > 0 } {
}

7
verilog/test/verilog_bus.tcl
View File

@ -82,17 +82,12 @@ puts "--- write_verilog with bus ports ---"
set outfile [make_result_file verilog_bus_out.v] set outfile [make_result_file verilog_bus_out.v]
write_verilog $outfile write_verilog $outfile
if { [file exists $outfile] && [file size $outfile] > 0 } { puts "output size: [file size $outfile]"
puts "output size: [file size $outfile]"
}
# Write with pwr_gnd to exercise pwr/gnd port direction paths # Write with pwr_gnd to exercise pwr/gnd port direction paths
set outfile2 [make_result_file verilog_bus_pwr.v] set outfile2 [make_result_file verilog_bus_pwr.v]
write_verilog -include_pwr_gnd $outfile2 write_verilog -include_pwr_gnd $outfile2
if { [file exists $outfile2] && [file size $outfile2] > 0 } {
}
#--------------------------------------------------------------- #---------------------------------------------------------------
# Test report_net with bus nets # Test report_net with bus nets
#--------------------------------------------------------------- #---------------------------------------------------------------

13
verilog/test/verilog_bus_partselect.tcl
View File

@ -1,19 +1,6 @@
# Test VerilogReader and VerilogWriter with bus part-select, bit-select, # Test VerilogReader and VerilogWriter with bus part-select, bit-select,
# concatenation expressions, hierarchical sub-modules with bus ports, # concatenation expressions, hierarchical sub-modules with bus ports,
# and write_verilog roundtrip of bus designs. # and write_verilog roundtrip of bus designs.
# Targets: VerilogReader.cc uncovered:
# net_part_select_count_ (part-select parsing, line ~209)
# net_bit_select_count_ (bit-select, line ~207)
# net_port_ref_bit_count_ / net_port_ref_part_count_ (port ref bus)
# concat_count_ (concatenation expression, line ~214)
# makeCellPorts bus port handling
# makeModule with port_dcls (bus declarations)
# linkNetwork with hierarchical bus connections
# Also targets: VerilogWriter.cc:
# writeInstBusPin / writeInstBusPinBit (bus port writing)
# writeWireDcls (bus wire declaration, parseBusName)
# findHierChildren (hierarchical child discovery)
# writeModule for hierarchical modules
source ../../test/helpers.tcl source ../../test/helpers.tcl

20
verilog/test/verilog_complex_bus.tcl
View File

@ -1,17 +1,4 @@
# Test verilog with complex bus/range constructs # Test verilog with complex bus/range constructs
# Targets: VerilogReader.cc uncovered functions:
# makeNetBitSelect (line 497, hit=0)
# makeNetPartSelect (line 461, hit=0)
# makeNetConcat (line 699, hit=0)
# makeNetNamedPortRefBit (line 671, hit=0)
# makeNetNamedPortRefPart (line 684, hit=0)
# makeNetNamedPortRefScalar (line 658, hit=0)
# VerilogDclBus constructor (line 1006, 1018, hit=0)
# makeNamedPortRefCellPorts (line 333, hit=0)
# Also exercises: VerilogLex.ll (bus index/range lexing)
# VerilogParse.yy (bus port, wire, range parsing)
# VerilogWriter.cc (writeInstBusPin, writeInstBusPinBit)
# ConcreteNetwork.cc (bus port operations)
source ../../test/helpers.tcl source ../../test/helpers.tcl
@ -145,16 +132,11 @@ puts "--- Test 5: write verilog with buses ---"
set outfile [make_result_file verilog_complex_bus_out.v] set outfile [make_result_file verilog_complex_bus_out.v]
write_verilog $outfile write_verilog $outfile
if { [file exists $outfile] && [file size $outfile] > 0 } { puts "output size: [file size $outfile]"
puts "output size: [file size $outfile]"
}
set outfile2 [make_result_file verilog_complex_bus_pwr.v] set outfile2 [make_result_file verilog_complex_bus_pwr.v]
write_verilog -include_pwr_gnd $outfile2 write_verilog -include_pwr_gnd $outfile2
if { [file exists $outfile2] && [file size $outfile2] > 0 } {
}
#--------------------------------------------------------------- #---------------------------------------------------------------
# Test 6: Timing analysis on bus design # Test 6: Timing analysis on bus design
#--------------------------------------------------------------- #---------------------------------------------------------------

13
verilog/test/verilog_const_concat.tcl
View File

@ -1,12 +1,4 @@
# Test verilog with net constants (1'b0, 1'b1), concatenation and part selects. # Test verilog with net constants (1'b0, 1'b1), concatenation and part selects.
# Targets VerilogReader.cc uncovered paths:
# makeNetConstant (line 478)
# VerilogNetConstant constructor/parsing
# constant net binding (ensureNetBinding with zero_/one_ net names)
# addConstantNet paths (lines 2190-2192)
# Multiple design link_design calls (exercises linkNetwork paths)
# Also targets VerilogWriter.cc:
# writeAssigns, writeChildren with constant connections
source ../../test/helpers.tcl source ../../test/helpers.tcl
@ -63,11 +55,6 @@ write_verilog $out1
set out2 [make_result_file verilog_const_concat_pwr.v] set out2 [make_result_file verilog_const_concat_pwr.v]
write_verilog -include_pwr_gnd $out2 write_verilog -include_pwr_gnd $out2
if { [file exists $out1] && [file size $out1] > 0 } {
}
if { [file exists $out2] && [file size $out2] > 0 } {
}
#--------------------------------------------------------------- #---------------------------------------------------------------
# Test 4: report_net for constant-related nets # Test 4: report_net for constant-related nets
#--------------------------------------------------------------- #---------------------------------------------------------------

5
verilog/test/verilog_error_paths.tcl
View File

@ -117,11 +117,6 @@ write_verilog $out1
set out2 [make_result_file verilog_error_paths_pwr.v] set out2 [make_result_file verilog_error_paths_pwr.v]
write_verilog -include_pwr_gnd $out2 write_verilog -include_pwr_gnd $out2
if { [file exists $out1] && [file size $out1] > 0 } {
}
if { [file exists $out2] && [file size $out2] > 0 } {
}
#--------------------------------------------------------------- #---------------------------------------------------------------
# Test 5: Report net for bus and assign-related nets # Test 5: Report net for bus and assign-related nets
#--------------------------------------------------------------- #---------------------------------------------------------------

30
verilog/test/verilog_escaped_write.tcl
View File

@ -34,16 +34,10 @@ puts "ports: [llength $ports]"
set out1 [make_result_file verilog_escaped_bus.v] set out1 [make_result_file verilog_escaped_bus.v]
write_verilog $out1 write_verilog $out1
if { [file exists $out1] && [file size $out1] > 0 } {
}
# Write with pwr_gnd # Write with pwr_gnd
set out2 [make_result_file verilog_escaped_bus_pwr.v] set out2 [make_result_file verilog_escaped_bus_pwr.v]
write_verilog -include_pwr_gnd $out2 write_verilog -include_pwr_gnd $out2
if { [file exists $out2] && [file size $out2] > 0 } {
}
# pwr_gnd should be larger # pwr_gnd should be larger
set sz1 [file size $out1] set sz1 [file size $out1]
set sz2 [file size $out2] set sz2 [file size $out2]
@ -94,15 +88,9 @@ link_design verilog_complex_bus_test
set out3 [make_result_file verilog_escaped_complex.v] set out3 [make_result_file verilog_escaped_complex.v]
write_verilog $out3 write_verilog $out3
if { [file exists $out3] && [file size $out3] > 0 } {
}
set out4 [make_result_file verilog_escaped_complex_pwr.v] set out4 [make_result_file verilog_escaped_complex_pwr.v]
write_verilog -include_pwr_gnd $out4 write_verilog -include_pwr_gnd $out4
if { [file exists $out4] && [file size $out4] > 0 } {
}
# Read back complex bus design # Read back complex bus design
puts "--- roundtrip complex bus ---" puts "--- roundtrip complex bus ---"
read_liberty ../../test/nangate45/Nangate45_typ.lib read_liberty ../../test/nangate45/Nangate45_typ.lib
@ -148,15 +136,9 @@ link_design network_hier_test
set out5 [make_result_file verilog_escaped_hier.v] set out5 [make_result_file verilog_escaped_hier.v]
write_verilog $out5 write_verilog $out5
if { [file exists $out5] && [file size $out5] > 0 } {
}
set out6 [make_result_file verilog_escaped_hier_pwr.v] set out6 [make_result_file verilog_escaped_hier_pwr.v]
write_verilog -include_pwr_gnd $out6 write_verilog -include_pwr_gnd $out6
if { [file exists $out6] && [file size $out6] > 0 } {
}
# Roundtrip hierarchical # Roundtrip hierarchical
read_liberty ../../test/nangate45/Nangate45_typ.lib read_liberty ../../test/nangate45/Nangate45_typ.lib
read_verilog $out5 read_verilog $out5
@ -191,15 +173,9 @@ link_design verilog_supply_tristate
set out7 [make_result_file verilog_escaped_supply.v] set out7 [make_result_file verilog_escaped_supply.v]
write_verilog $out7 write_verilog $out7
if { [file exists $out7] && [file size $out7] > 0 } {
}
set out8 [make_result_file verilog_escaped_supply_pwr.v] set out8 [make_result_file verilog_escaped_supply_pwr.v]
write_verilog -include_pwr_gnd $out8 write_verilog -include_pwr_gnd $out8
if { [file exists $out8] && [file size $out8] > 0 } {
}
#--------------------------------------------------------------- #---------------------------------------------------------------
# Test 6: Write constant/concat design # Test 6: Write constant/concat design
# Exercises: writeChildren with constant pin connections # Exercises: writeChildren with constant pin connections
@ -212,15 +188,9 @@ link_design verilog_const_concat
set out9 [make_result_file verilog_escaped_const.v] set out9 [make_result_file verilog_escaped_const.v]
write_verilog $out9 write_verilog $out9
if { [file exists $out9] && [file size $out9] > 0 } {
}
set out10 [make_result_file verilog_escaped_const_pwr.v] set out10 [make_result_file verilog_escaped_const_pwr.v]
write_verilog -include_pwr_gnd $out10 write_verilog -include_pwr_gnd $out10
if { [file exists $out10] && [file size $out10] > 0 } {
}
# Roundtrip constant design # Roundtrip constant design
read_liberty ../../test/nangate45/Nangate45_typ.lib read_liberty ../../test/nangate45/Nangate45_typ.lib
read_verilog $out9 read_verilog $out9

16
verilog/test/verilog_gcd_large.tcl
View File

@ -52,13 +52,9 @@ write_verilog -include_pwr_gnd $out2
set out3 [make_result_file verilog_gcd_large_sort.v] set out3 [make_result_file verilog_gcd_large_sort.v]
write_verilog -sort $out3 write_verilog -sort $out3
# Verify files are non-empty # Print file sizes
foreach outf [list $out1 $out2 $out3] { foreach outf [list $out1 $out2 $out3] {
if {[file exists $outf] && [file size $outf] > 0} { puts " $outf size=[file size $outf]"
puts " $outf size=[file size $outf]"
} else {
puts " WARNING: $outf missing or empty"
}
} }
############################################################ ############################################################
@ -90,13 +86,7 @@ report_checks -format full_clock
puts "--- Test 5: write with remove ---" puts "--- Test 5: write with remove ---"
set out4 [make_result_file verilog_gcd_large_remove.v] set out4 [make_result_file verilog_gcd_large_remove.v]
catch { write_verilog -remove_cells {sky130_fd_sc_hd__fill_1 sky130_fd_sc_hd__fill_2} $out4
write_verilog -remove_cells {sky130_fd_sc_hd__fill_1 sky130_fd_sc_hd__fill_2} $out4
} msg
if {[string match "*Error*" $msg]} {
# If -remove_cells is not supported, try without it
write_verilog $out4
}
############################################################ ############################################################
# Test 6: Instance and net reports # Test 6: Instance and net reports

7
verilog/test/verilog_gcd_writer.tcl
View File

@ -1,12 +1,5 @@
# Test verilog writer with GCD sky130 design (large design with bus nets, # Test verilog writer with GCD sky130 design (large design with bus nets,
# unconnected pins, many cell types, power/ground nets). # unconnected pins, many cell types, power/ground nets).
# Targets: VerilogWriter.cc uncovered:
# writeInstBusPin / writeInstBusPinBit (bus port handling)
# writeWireDcls (bus wire declarations, isBusName, parseBusName paths)
# findUnconnectedNetCount / findChildNCcount / findPortNCcount
# writeAssigns (assign statements from net connections)
# verilogPortDir for power/ground ports with -include_pwr_gnd
# Also targets: VerilogReader.cc paths from re-reading written output
source ../../test/helpers.tcl source ../../test/helpers.tcl

16
verilog/test/verilog_hier_write.tcl
View File

@ -43,10 +43,6 @@ foreach pname {clk reset req_val req_rdy resp_val resp_rdy} {
puts "--- Test 2: write_verilog basic ---" puts "--- Test 2: write_verilog basic ---"
set out1 [make_result_file verilog_hier_basic.v] set out1 [make_result_file verilog_hier_basic.v]
write_verilog $out1 write_verilog $out1
if { [file exists $out1] && [file size $out1] > 0 } {
} else {
puts "FAIL: basic write_verilog file missing or empty"
}
#--------------------------------------------------------------- #---------------------------------------------------------------
# Test 3: Write verilog with -include_pwr_gnd # Test 3: Write verilog with -include_pwr_gnd
@ -54,10 +50,6 @@ if { [file exists $out1] && [file size $out1] > 0 } {
puts "--- Test 3: write_verilog -include_pwr_gnd ---" puts "--- Test 3: write_verilog -include_pwr_gnd ---"
set out2 [make_result_file verilog_hier_pwr.v] set out2 [make_result_file verilog_hier_pwr.v]
write_verilog -include_pwr_gnd $out2 write_verilog -include_pwr_gnd $out2
if { [file exists $out2] && [file size $out2] > 0 } {
} else {
puts "FAIL: pwr_gnd write_verilog file missing or empty"
}
# pwr_gnd output should be >= basic output # pwr_gnd output should be >= basic output
set sz1 [file size $out1] set sz1 [file size $out1]
@ -71,8 +63,6 @@ if { $sz2 >= $sz1 } {
puts "--- Test 4: write_verilog -remove_cells ---" puts "--- Test 4: write_verilog -remove_cells ---"
set out3 [make_result_file verilog_hier_remove.v] set out3 [make_result_file verilog_hier_remove.v]
write_verilog -remove_cells {} $out3 write_verilog -remove_cells {} $out3
if { [file exists $out3] && [file size $out3] > 0 } {
}
#--------------------------------------------------------------- #---------------------------------------------------------------
# Test 5: Read back the written verilog (roundtrip) # Test 5: Read back the written verilog (roundtrip)
@ -94,8 +84,6 @@ puts "roundtrip ports: [llength $ports2]"
# Write again after roundtrip # Write again after roundtrip
set out4 [make_result_file verilog_hier_roundtrip.v] set out4 [make_result_file verilog_hier_roundtrip.v]
write_verilog $out4 write_verilog $out4
if { [file exists $out4] && [file size $out4] > 0 } {
}
#--------------------------------------------------------------- #---------------------------------------------------------------
# Test 6: Set up timing and report with bus ports # Test 6: Set up timing and report with bus ports
@ -117,10 +105,6 @@ report_checks -fields {slew cap input_pins nets fanout}
puts "--- Test 7: write after timing setup ---" puts "--- Test 7: write after timing setup ---"
set out5 [make_result_file verilog_hier_post_timing.v] set out5 [make_result_file verilog_hier_post_timing.v]
write_verilog $out5 write_verilog $out5
if { [file exists $out5] && [file size $out5] > 0 } {
}
set out6 [make_result_file verilog_hier_post_timing_pwr.v] set out6 [make_result_file verilog_hier_post_timing_pwr.v]
write_verilog -include_pwr_gnd $out6 write_verilog -include_pwr_gnd $out6
if { [file exists $out6] && [file size $out6] > 0 } {
}

4
verilog/test/verilog_multimodule_write.ok
View File

@ -2,10 +2,6 @@
cells: 5 cells: 5
Warning: verilog_multimodule_write.tcl line 1, The -sort flag is ignored. Warning: verilog_multimodule_write.tcl line 1, The -sort flag is ignored.
Warning: verilog_multimodule_write.tcl line 1, The -sort flag is ignored. Warning: verilog_multimodule_write.tcl line 1, The -sort flag is ignored.
/workspace/sta/OpenSTA/verilog/test/results/verilog_mm_default.v OK
/workspace/sta/OpenSTA/verilog/test/results/verilog_mm_pwr.v OK
/workspace/sta/OpenSTA/verilog/test/results/verilog_mm_sort.v OK
/workspace/sta/OpenSTA/verilog/test/results/verilog_mm_pwr_sort.v OK
--- Test 2: re-read default --- --- Test 2: re-read default ---
Warning: ../../test/nangate45/Nangate45_typ.lib line 37, library NangateOpenCellLibrary already exists. Warning: ../../test/nangate45/Nangate45_typ.lib line 37, library NangateOpenCellLibrary already exists.
re-read cells: 5 re-read cells: 5

7
verilog/test/verilog_multimodule_write.tcl
View File

@ -34,13 +34,6 @@ write_verilog -sort $out3
set out4 [make_result_file verilog_mm_pwr_sort.v] set out4 [make_result_file verilog_mm_pwr_sort.v]
write_verilog -include_pwr_gnd -sort $out4 write_verilog -include_pwr_gnd -sort $out4
# Verify sizes
foreach outf [list $out1 $out2 $out3 $out4] {
if {[file exists $outf] && [file size $outf] > 0} {
puts " $outf OK"
}
}
############################################################ ############################################################
# Test 2: Re-read written verilog # Test 2: Re-read written verilog
############################################################ ############################################################

3
verilog/test/verilog_preproc_param.tcl
View File

@ -64,9 +64,6 @@ write_verilog $out1
set out2 [make_result_file verilog_preproc_param_pwr.v] set out2 [make_result_file verilog_preproc_param_pwr.v]
write_verilog -include_pwr_gnd $out2 write_verilog -include_pwr_gnd $out2
if { [file exists $out1] && [file size $out1] > 0 } {
}
#--------------------------------------------------------------- #---------------------------------------------------------------
# Test 4: Instance and net reports # Test 4: Instance and net reports
#--------------------------------------------------------------- #---------------------------------------------------------------

3
verilog/test/verilog_specify.tcl
View File

@ -28,6 +28,3 @@ puts "ports: [llength $ports]"
puts "--- write_verilog ---" puts "--- write_verilog ---"
set outfile [make_result_file verilog_specify_out.v] set outfile [make_result_file verilog_specify_out.v]
write_verilog $outfile write_verilog $outfile
if { [file exists $outfile] && [file size $outfile] > 0 } {
}

6
verilog/test/verilog_supply_tristate.tcl
View File

@ -93,15 +93,9 @@ puts "--- Test 4: write_verilog ---"
set out1 [make_result_file verilog_supply_tri_out.v] set out1 [make_result_file verilog_supply_tri_out.v]
write_verilog $out1 write_verilog $out1
if { [file exists $out1] && [file size $out1] > 0 } {
}
set out2 [make_result_file verilog_supply_tri_pwr.v] set out2 [make_result_file verilog_supply_tri_pwr.v]
write_verilog -include_pwr_gnd $out2 write_verilog -include_pwr_gnd $out2
if { [file exists $out2] && [file size $out2] > 0 } {
}
#--------------------------------------------------------------- #---------------------------------------------------------------
# Test 5: Multiple read_verilog (re-read exercises deleteModules paths) # Test 5: Multiple read_verilog (re-read exercises deleteModules paths)
#--------------------------------------------------------------- #---------------------------------------------------------------

15
verilog/test/verilog_write_options.tcl
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@ -8,26 +8,14 @@ link_design verilog_test1
puts "--- write_verilog basic ---" puts "--- write_verilog basic ---"
set out1 [make_result_file verilog_write_options_out1.v] set out1 [make_result_file verilog_write_options_out1.v]
write_verilog $out1 write_verilog $out1
if { [file exists $out1] && [file size $out1] > 0 } {
} else {
puts "FAIL: basic write_verilog file missing or empty"
}
puts "--- write_verilog -include_pwr_gnd ---" puts "--- write_verilog -include_pwr_gnd ---"
set out2 [make_result_file verilog_write_options_out2.v] set out2 [make_result_file verilog_write_options_out2.v]
write_verilog -include_pwr_gnd $out2 write_verilog -include_pwr_gnd $out2
if { [file exists $out2] && [file size $out2] > 0 } {
} else {
puts "FAIL: write_verilog -include_pwr_gnd file missing or empty"
}
puts "--- write_verilog -remove_cells (empty list) ---" puts "--- write_verilog -remove_cells (empty list) ---"
set out3 [make_result_file verilog_write_options_out3.v] set out3 [make_result_file verilog_write_options_out3.v]
write_verilog -remove_cells {} $out3 write_verilog -remove_cells {} $out3
if { [file exists $out3] && [file size $out3] > 0 } {
} else {
puts "FAIL: write_verilog -remove_cells {} file missing or empty"
}
puts "--- compare pwr_gnd vs basic output ---" puts "--- compare pwr_gnd vs basic output ---"
set sz1 [file size $out1] set sz1 [file size $out1]
@ -46,9 +34,6 @@ puts "--- write_verilog -sort (deprecated, should warn) ---"
set out4 [make_result_file verilog_write_options_out4.v] set out4 [make_result_file verilog_write_options_out4.v]
catch {write_verilog -sort $out4} msg_sort catch {write_verilog -sort $out4} msg_sort
puts "write_verilog -sort: $msg_sort" puts "write_verilog -sort: $msg_sort"
if { [file exists $out4] && [file size $out4] > 0 } {
}
puts "--- read_verilog / write_verilog roundtrip ---" puts "--- read_verilog / write_verilog roundtrip ---"
# Read back the written verilog to exercise reader code paths # Read back the written verilog to exercise reader code paths
set out5 [make_result_file verilog_write_options_out5.v] set out5 [make_result_file verilog_write_options_out5.v]

174
verilog/test/verilog_write_types.tcl
View File

@ -1,174 +0,0 @@
# Test write verilog with various cell types and connections
# Targets: VerilogWriter.cc uncovered functions:
# writeInstBusPin (line 382, hit=0), writeInstBusPinBit (line 416, hit=0)
# findPortNCcount (line 499, hit=0)
# findHierChildren lambda (line 142, hit=0)
# verilogPortDir for various directions (line 240)
# writeAssigns (line 439)
# findUnconnectedNetCount (line 469)
# findChildNCcount (line 482)
# Also targets: VerilogReader.cc (various cell type reading paths)
# VerilogParse.yy (parser paths for different constructs)
source ../../test/helpers.tcl
#---------------------------------------------------------------
# Test 1: Write with multiple cell types (Nangate45)
#---------------------------------------------------------------
puts "--- Test 1: Write Nangate45 multi-type design ---"
read_liberty ../../test/nangate45/Nangate45_typ.lib
read_verilog verilog_test1.v
link_design verilog_test1
# Add various cell types to exercise more writer paths
set net_a [make_net wire_a]
set net_b [make_net wire_b]
set net_c [make_net wire_c]
set net_d [make_net wire_d]
set net_e [make_net wire_e]
# NAND gate
set inst_nand [make_instance nand1 NangateOpenCellLibrary/NAND2_X1]
connect_pin wire_a nand1/A1
connect_pin wire_b nand1/A2
# NOR gate
set inst_nor [make_instance nor1 NangateOpenCellLibrary/NOR2_X1]
connect_pin wire_c nor1/A1
connect_pin wire_d nor1/A2
# Another buffer with different drive
set inst_buf [make_instance buf_x4 NangateOpenCellLibrary/BUF_X4]
connect_pin wire_e buf_x4/A
puts "cells after additions: [llength [get_cells *]]"
puts "nets after additions: [llength [get_nets *]]"
# Write basic verilog
set out1 [make_result_file verilog_types_out1.v]
write_verilog $out1
if { [file exists $out1] && [file size $out1] > 0 } {
}
# Write with pwr_gnd
set out2 [make_result_file verilog_types_out2.v]
write_verilog -include_pwr_gnd $out2
if { [file exists $out2] && [file size $out2] > 0 } {
}
# Cleanup added instances/nets
disconnect_pin wire_a nand1/A1
disconnect_pin wire_b nand1/A2
disconnect_pin wire_c nor1/A1
disconnect_pin wire_d nor1/A2
disconnect_pin wire_e buf_x4/A
delete_instance nand1
delete_instance nor1
delete_instance buf_x4
delete_net wire_a
delete_net wire_b
delete_net wire_c
delete_net wire_d
delete_net wire_e
#---------------------------------------------------------------
# Test 2: Write bus design (exercises writeInstBusPin)
#---------------------------------------------------------------
puts "--- Test 2: Write bus design ---"
read_liberty ../../test/nangate45/Nangate45_typ.lib
read_verilog verilog_bus_test.v
link_design verilog_bus_test
set out3 [make_result_file verilog_types_bus.v]
write_verilog $out3
if { [file exists $out3] && [file size $out3] > 0 } {
}
set out4 [make_result_file verilog_types_bus_pwr.v]
write_verilog -include_pwr_gnd $out4
#---------------------------------------------------------------
# Test 3: Write assign design
#---------------------------------------------------------------
puts "--- Test 3: Write assign design ---"
read_liberty ../../test/nangate45/Nangate45_typ.lib
read_verilog verilog_assign_test.v
link_design verilog_assign_test
set out5 [make_result_file verilog_types_assign.v]
write_verilog $out5
if { [file exists $out5] && [file size $out5] > 0 } {
}
#---------------------------------------------------------------
# Test 4: Write attribute design (sky130)
#---------------------------------------------------------------
puts "--- Test 4: Write attribute design ---"
read_liberty ../../test/sky130hd/sky130_fd_sc_hd__tt_025C_1v80.lib
read_verilog ../../test/verilog_attribute.v
link_design counter
set out6 [make_result_file verilog_types_attr.v]
write_verilog $out6
if { [file exists $out6] && [file size $out6] > 0 } {
}
set out7 [make_result_file verilog_types_attr_pwr.v]
write_verilog -include_pwr_gnd $out7
if { [file exists $out7] && [file size $out7] > 0 } {
}
#---------------------------------------------------------------
# Test 5: Write ASAP7 design (different cell naming)
#---------------------------------------------------------------
puts "--- Test 5: Write ASAP7 design ---"
read_liberty ../../test/asap7/asap7sc7p5t_SEQ_RVT_FF_nldm_220123.lib
read_liberty ../../test/asap7/asap7sc7p5t_INVBUF_RVT_FF_nldm_220122.lib.gz
read_liberty ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz
read_liberty ../../test/asap7/asap7sc7p5t_OA_RVT_FF_nldm_211120.lib.gz
read_liberty ../../test/asap7/asap7sc7p5t_AO_RVT_FF_nldm_211120.lib.gz
read_verilog ../../test/reg1_asap7.v
link_design top
set out8 [make_result_file verilog_types_asap7.v]
write_verilog $out8
if { [file exists $out8] && [file size $out8] > 0 } {
}
set out9 [make_result_file verilog_types_asap7_pwr.v]
write_verilog -include_pwr_gnd $out9
# Write with remove_cells
set out10 [make_result_file verilog_types_asap7_remove.v]
write_verilog -remove_cells {} $out10
# Compare sizes
set sz8 [file size $out8]
set sz9 [file size $out9]
set sz10 [file size $out10]
puts "ASAP7 basic: $sz8, pwr_gnd: $sz9, remove_cells: $sz10"
#---------------------------------------------------------------
# Test 6: Write complex bus design
#---------------------------------------------------------------
puts "--- Test 6: Write complex bus design ---"
read_liberty ../../test/nangate45/Nangate45_typ.lib
read_verilog verilog_complex_bus_test.v
link_design verilog_complex_bus_test
set out11 [make_result_file verilog_types_complex_bus.v]
write_verilog $out11
if { [file exists $out11] && [file size $out11] > 0 } {
}
set out12 [make_result_file verilog_types_complex_bus_pwr.v]
write_verilog -include_pwr_gnd $out12

16
verilog/test/verilog_writer_advanced.tcl
View File

@ -1,12 +1,4 @@
# Test advanced verilog writer options for coverage improvement # Test advanced verilog writer options
# Targets: VerilogWriter.cc (67.0% coverage)
# - writeModules hierarchy paths
# - writeInstBusPin / writeInstBusPinBit
# - writeWireDcls
# - writeAssigns
# - findUnconnectedNetCount / findChildNCcount / findPortNCcount
# - verilogPortDir for various directions
source ../../test/helpers.tcl source ../../test/helpers.tcl
#--------------------------------------------------------------- #---------------------------------------------------------------
@ -46,9 +38,6 @@ puts "basic size: $sz1"
puts "pwr_gnd size: $sz2" puts "pwr_gnd size: $sz2"
puts "remove_cells size: $sz3" puts "remove_cells size: $sz3"
if { $sz2 >= $sz1 } {
}
#--------------------------------------------------------------- #---------------------------------------------------------------
# Test 2: Write after network modification # Test 2: Write after network modification
#--------------------------------------------------------------- #---------------------------------------------------------------
@ -64,9 +53,6 @@ write_verilog $out4
set sz4 [file size $out4] set sz4 [file size $out4]
puts "modified size: $sz4" puts "modified size: $sz4"
if { $sz4 > $sz1 } {
}
# Disconnect and delete # Disconnect and delete
disconnect_pin extra_net extra_buf/A disconnect_pin extra_net extra_buf/A
delete_instance extra_buf delete_instance extra_buf